[llvm] AMDGPU/GlobalISel: RegBankLegalize rules for split barrier intrinsics (PR #192170)

[Chinmay Deshpande via llvm-commits]

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@@ -1528,6 +1516,19 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
   addRulesForIOpcs({amdgcn_s_sleep_var})
       .Any({{}, {{}, {IntrId, SgprB32_ReadFirstLane}}});
 
+  addRulesForIOpcs({amdgcn_s_barrier_join, amdgcn_s_wakeup_barrier})
+      .Any({{}, {{}, {IntrId, SgprB32_M0}}});
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chinmaydd wrote:

The `s.barrier.join` intrinsic definition says :
```
// void @llvm.amdgcn.s.barrier.join(ptr addrspace(3) %barrier)
// The %barrier argument must be uniform, otherwise behavior is undefined.
```

If we expect the argument to be uniform, can we use the stricter `SgprB32` here or `SgprB32_M0` is the more complete solution ?

https://github.com/llvm/llvm-project/pull/192170