[llvm] [AArch64][ISel] Fix interleave3 crash (PR #192046)

[David Sherwood via llvm-commits]

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@@ -32322,6 +32322,63 @@ SDValue AArch64TargetLowering::LowerVECTOR_INTERLEAVE(SDValue Op,
     return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, Op->getVTList(), Ops);
   }
 
+  if (Op->getNumOperands() == 3 && (OpVT == MVT::v2f64 || OpVT == MVT::v2i64)) {
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david-arm wrote:

Why is this only required for 64-bit elements? It would be good to add some comments here explaining the rationale.

https://github.com/llvm/llvm-project/pull/192046