[llvm] [AMDGPU] PreRA Peephole: EliminateSaveRestore (PR #191583)

[Zeng Wu via llvm-commits]

https://github.com/zwu-2025 updated https://github.com/llvm/llvm-project/pull/191583

>From 31aa2fa61cd748ece35c89cf23fe6f67ce329d2e Mon Sep 17 00:00:00 2001
From: root <Zeng.Wu2 at amd.com>
Date: Tue, 14 Apr 2026 04:52:31 +0000
Subject: [PATCH] [AMDGPU] Add a mir test to verify register-coalesce works for
 eliminate-save-restore pattern

---
 .../AMDGPU/amdgcn-eliminate-save-restore.mir  | 44 +++++++++++++++++++
 1 file changed, 44 insertions(+)
 create mode 100644 llvm/test/CodeGen/AMDGPU/amdgcn-eliminate-save-restore.mir

diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn-eliminate-save-restore.mir b/llvm/test/CodeGen/AMDGPU/amdgcn-eliminate-save-restore.mir
new file mode 100644
index 0000000000000..45d2ec48aad89
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn-eliminate-save-restore.mir
@@ -0,0 +1,44 @@
+# RUN: llc -march=amdgcn -mcpu=gfx950 -run-pass="phi-node-elimination,register-coalescer"  --verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name:            test_basic_case
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    successors: %bb.1(0x40000000)
+    liveins: $vgpr0
+
+    %orig_0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    S_BRANCH %bb.1
+
+  bb.1:
+    successors: %bb.1(0x40000000)
+    %tmp:vgpr_32 = PHI %orig_0, %bb.0, %orig_next, %bb.1
+    
+    %other:vgpr_32 = V_MOV_B32_e32 42, implicit $exec
+    %orig:vgpr_32 = V_ADD_U32_e32 %tmp, %other, implicit $exec
+    %2:vgpr_32 = V_MUL_LO_U32_e64 %orig, %orig, implicit $exec
+    %orig_next:vgpr_32 = V_MOV_B32_e32 %tmp, implicit $exec
+
+    S_BRANCH %bb.1
+
+...
+
+
+# CHECK-LABEL: body:
+
+# bb.0
+# CHECK:  bb.0:
+# CHECK-NEXT:    successors: %bb.1
+# CHECK-NEXT:    liveins: $vgpr0
+# CHECK:    [[R1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+# CHECK-NEXT:    S_BRANCH %bb.1
+
+# bb.1
+# CHECK:  bb.1:
+# CHECK-NEXT:    successors: %bb.1
+# CHECK:         %other:vgpr_32 = V_MOV_B32_e32 42, implicit $exec
+# CHECK-NEXT:    %orig:vgpr_32 = V_ADD_U32_e32 [[R1]], %other, implicit $exec
+# CHECK-NEXT:    dead %{{[0-9]+}}:vgpr_32 = V_MUL_LO_U32_e64 %orig, %orig, implicit $exec
+# CHECK-NEXT:    [[R1]]:vgpr_32 = V_MOV_B32_e32 [[R1]], implicit $exec
+# CHECK-NEXT:    S_BRANCH %bb.1