[llvm] [AArch64] Add tablegen patterns for store of high-half. (PR #190320)

[David Green via llvm-commits]

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@@ -86,18 +55,11 @@ define void @v16i8(<16 x i8> %a, ptr %p1, ptr %p2) {
 }
 
 define void @v2f64(<2 x double> %a, ptr %p1, ptr %p2) {
-; CHECK-SD-LABEL: v2f64:
-; CHECK-SD:       // %bb.0:
-; CHECK-SD-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-SD-NEXT:    str d0, [x0]
-; CHECK-SD-NEXT:    str d1, [x1]
-; CHECK-SD-NEXT:    ret
-;
-; CHECK-GI-LABEL: v2f64:
-; CHECK-GI:       // %bb.0:
-; CHECK-GI-NEXT:    str d0, [x0]
-; CHECK-GI-NEXT:    st1 { v0.d }[1], [x1]
-; CHECK-GI-NEXT:    ret
+; CHECK-LABEL: v2f64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    str d0, [x0]
+; CHECK-NEXT:    st1 { v0.d }[1], [x1]
----------------
davemgreen wrote:

Hi - The `str d0, [x0]` was OK before - that should stay the same. It stores the low half of the vector.
The `ext v1.16b, v0.16b, v0.16b, #8; str d1, [x1]` we are transforming into `st1 { v0.d }[1], [x1]` that performs the extract high half and store as one operation. Which is hopefully an improvement most of the time.

https://github.com/llvm/llvm-project/pull/190320