[llvm] [AArch64] Codegen for AArch64 Return Address Signing Hardening (PR #176187)

[Anatoly Trosinenko via llvm-commits]

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atrosinenko wrote:

IIUC `RegScavenger` is able to insert spills / reloads of registers but is used here in an analysis-only mode and is re-initialized for each processed basic block. If this is correct, this line looks useless.

https://github.com/llvm/llvm-project/pull/176187