[llvm] [AMDGPU] Remove implicit defs on expanded mov64 pseudos (PR #190379)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 3 11:06:12 PDT 2026
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Joe Nash (Sisyph)
<details>
<summary>Changes</summary>
The mov64 pseudo is split into two 32 bit movs, but those 32 bit movs
had the full 64-bit register still implicitly defined. VOPD formation is
affected, so we can emit more of them.
---
Patch is 951.46 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/190379.diff
96 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/SIInstrInfo.cpp (+8-16)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_minmax.ll (+28-32)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_udec_wrap.ll (+77-83)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll (+121-135)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll (+7-8)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll (+26-26)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll (+6-12)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll (+147-174)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll (+101-127)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll (+14-14)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.rsq.clamp.ll (+24-40)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll (+10-10)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll (+14-14)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll (+21-25)
- (modified) llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll (+30-39)
- (modified) llvm/test/CodeGen/AMDGPU/av_movimm_pseudo_expansion.mir (+38-38)
- (modified) llvm/test/CodeGen/AMDGPU/calling-conventions.ll (+73-70)
- (modified) llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll (+9-11)
- (modified) llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll (+8-16)
- (modified) llvm/test/CodeGen/AMDGPU/dag-divergence-atomic.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/div_i128.ll (+9-9)
- (modified) llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll (+9-12)
- (modified) llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/extract_vector_elt-i8.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/fcanonicalize.ll (+166-278)
- (modified) llvm/test/CodeGen/AMDGPU/fp-atomics-gfx1200.ll (+4-8)
- (modified) llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/fptoi.i128.ll (+13-13)
- (modified) llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll (+8-10)
- (modified) llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll (+10-12)
- (modified) llvm/test/CodeGen/AMDGPU/fptoui-sat-scalar.ll (+6-8)
- (modified) llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll (+6-8)
- (modified) llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll (+53-80)
- (modified) llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll (+12-12)
- (modified) llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll (+12-12)
- (modified) llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll (+57-57)
- (modified) llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll (+30-33)
- (modified) llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll (+30-33)
- (modified) llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll (+57-57)
- (modified) llvm/test/CodeGen/AMDGPU/inflate-av-remat-imm.mir (+10-10)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.dec.ll (+22-22)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.inc.ll (+22-22)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.pk.add.ll (+4-8)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w64.ll (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ll (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.quadmask.ll (+5-7)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readlane.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.chain.arg.ll (+3-7)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.exp.f64.ll (+184-184)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.exp10.f64.ll (+279-279)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.exp2.f64.ll (+254-254)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.set.rounding.ll (+14-16)
- (modified) llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll (+8-16)
- (modified) llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll (+8-16)
- (modified) llvm/test/CodeGen/AMDGPU/lrint.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/lround.ll (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/mad_64_32.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/memset-pattern.ll (+8-8)
- (modified) llvm/test/CodeGen/AMDGPU/misaligned-vgpr-regsequence.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/move-to-valu-lshl_add.ll (+1-2)
- (modified) llvm/test/CodeGen/AMDGPU/offset-split-global.ll (+12-12)
- (modified) llvm/test/CodeGen/AMDGPU/packed-fp32.ll (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/rem_i128.ll (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/roundeven.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/rsq.f64.ll (+7-7)
- (modified) llvm/test/CodeGen/AMDGPU/sdiv64.ll (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/shift-i128.ll (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/siloadstoreopt-misaligned-regsequence.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/srem64.ll (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/swdev380865.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/udiv.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/udiv64.ll (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/urem64.ll (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/v_mov_b64_expand_and_shrink.mir (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/v_mov_b64_expansion.mir (+20-20)
- (modified) llvm/test/CodeGen/AMDGPU/vgpr-mark-last-scratch-load.ll (+17-20)
- (modified) llvm/test/CodeGen/AMDGPU/wave32.ll (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/widen-smrd-loads.ll (+27-30)
- (modified) llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/wwm-reserved.ll (+2-2)
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index bafa6cd800b5e..aaabcb71fce5e 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -2162,11 +2162,9 @@ bool SIInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
Register DstLo = RI.getSubReg(Dst, AMDGPU::sub0);
Register DstHi = RI.getSubReg(Dst, AMDGPU::sub1);
BuildMI(MBB, MI, DL, get(AMDGPU::V_ACCVGPR_WRITE_B32_e64), DstLo)
- .addImm(SignExtend64<32>(Imm))
- .addReg(Dst, RegState::Implicit | RegState::Define);
+ .addImm(SignExtend64<32>(Imm));
BuildMI(MBB, MI, DL, get(AMDGPU::V_ACCVGPR_WRITE_B32_e64), DstHi)
- .addImm(SignExtend64<32>(Imm >> 32))
- .addReg(Dst, RegState::Implicit | RegState::Define);
+ .addImm(SignExtend64<32>(Imm >> 32));
MI.eraseFromParent();
break;
}
@@ -2211,11 +2209,9 @@ bool SIInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
.addImm(0); // clamp
} else {
BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
- .addImm(Lo.getSExtValue())
- .addReg(Dst, RegState::Implicit | RegState::Define);
+ .addImm(Lo.getSExtValue());
BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
- .addImm(Hi.getSExtValue())
- .addReg(Dst, RegState::Implicit | RegState::Define);
+ .addImm(Hi.getSExtValue());
}
} else {
assert(SrcOp.isReg());
@@ -2233,11 +2229,9 @@ bool SIInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
.addImm(0); // clamp
} else {
BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
- .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub0))
- .addReg(Dst, RegState::Implicit | RegState::Define);
+ .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub0));
BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
- .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub1))
- .addReg(Dst, RegState::Implicit | RegState::Define);
+ .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub1));
}
}
MI.eraseFromParent();
@@ -2269,11 +2263,9 @@ bool SIInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
APInt Lo(32, Imm.getLoBits(32).getZExtValue());
APInt Hi(32, Imm.getHiBits(32).getZExtValue());
BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DstLo)
- .addImm(Lo.getSExtValue())
- .addReg(Dst, RegState::Implicit | RegState::Define);
+ .addImm(Lo.getSExtValue());
BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DstHi)
- .addImm(Hi.getSExtValue())
- .addReg(Dst, RegState::Implicit | RegState::Define);
+ .addImm(Hi.getSExtValue());
MI.eraseFromParent();
break;
}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll
index a20387b17c53d..68d15b91932ce 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll
@@ -658,10 +658,10 @@ define amdgpu_ps i48 @s_andn2_v3i16(<3 x i16> inreg %src0, <3 x i16> inreg %src1
; GFX6-LABEL: s_andn2_v3i16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshr_b32 s7, s4, 16
-; GFX6-NEXT: s_mov_b32 s0, -1
; GFX6-NEXT: s_and_b32 s4, s4, 0xffff
; GFX6-NEXT: s_lshl_b32 s7, s7, 16
; GFX6-NEXT: s_lshr_b32 s6, s2, 16
+; GFX6-NEXT: s_mov_b32 s0, -1
; GFX6-NEXT: s_mov_b32 s1, 0xffff
; GFX6-NEXT: s_or_b32 s4, s4, s7
; GFX6-NEXT: s_and_b32 s5, s5, 0xffff
@@ -711,10 +711,10 @@ define amdgpu_ps i48 @s_andn2_v3i16_commute(<3 x i16> inreg %src0, <3 x i16> inr
; GFX6-LABEL: s_andn2_v3i16_commute:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshr_b32 s7, s4, 16
-; GFX6-NEXT: s_mov_b32 s0, -1
; GFX6-NEXT: s_and_b32 s4, s4, 0xffff
; GFX6-NEXT: s_lshl_b32 s7, s7, 16
; GFX6-NEXT: s_lshr_b32 s6, s2, 16
+; GFX6-NEXT: s_mov_b32 s0, -1
; GFX6-NEXT: s_mov_b32 s1, 0xffff
; GFX6-NEXT: s_or_b32 s4, s4, s7
; GFX6-NEXT: s_and_b32 s5, s5, 0xffff
@@ -764,10 +764,10 @@ define amdgpu_ps { i48, i48 } @s_andn2_v3i16_multi_use(<3 x i16> inreg %src0, <3
; GFX6-LABEL: s_andn2_v3i16_multi_use:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshr_b32 s7, s4, 16
-; GFX6-NEXT: s_mov_b32 s0, -1
; GFX6-NEXT: s_and_b32 s4, s4, 0xffff
; GFX6-NEXT: s_lshl_b32 s7, s7, 16
; GFX6-NEXT: s_lshr_b32 s6, s2, 16
+; GFX6-NEXT: s_mov_b32 s0, -1
; GFX6-NEXT: s_mov_b32 s1, 0xffff
; GFX6-NEXT: s_or_b32 s4, s4, s7
; GFX6-NEXT: s_and_b32 s5, s5, 0xffff
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_minmax.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_minmax.ll
index 2b70d83c20330..d233423e69135 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_minmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_minmax.ll
@@ -91,8 +91,8 @@ define amdgpu_kernel void @global_atomic_min_ret_i64(ptr addrspace(1) %out, ptr
; GFX11-LABEL: global_atomic_min_ret_i64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
-; GFX11-NEXT: v_mov_b32_e32 v0, 42
-; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, 0
+; GFX11-NEXT: v_dual_mov_b32 v0, 42 :: v_dual_mov_b32 v1, 0
+; GFX11-NEXT: v_mov_b32_e32 v2, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: global_atomic_min_i64 v[0:1], v2, v[0:1], s[2:3] glc
; GFX11-NEXT: s_waitcnt vmcnt(0)
@@ -164,8 +164,8 @@ define amdgpu_kernel void @flat_atomic_min_ret_i64(ptr addrspace(1) %out, ptr %p
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
; GFX9-NEXT: s_add_u32 flat_scratch_lo, s12, s17
-; GFX9-NEXT: v_mov_b32_e32 v0, 42
; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s13, 0
+; GFX9-NEXT: v_mov_b32_e32 v0, 42
; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v2, s2
@@ -200,10 +200,9 @@ define amdgpu_kernel void @flat_atomic_min_ret_i64(ptr addrspace(1) %out, ptr %p
; GFX11-LABEL: flat_atomic_min_ret_i64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
-; GFX11-NEXT: v_mov_b32_e32 v0, 42
+; GFX11-NEXT: v_dual_mov_b32 v0, 42 :: v_dual_mov_b32 v1, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s2
-; GFX11-NEXT: v_mov_b32_e32 v3, s3
+; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX11-NEXT: flat_atomic_min_i64 v[0:1], v[2:3], v[0:1] glc
; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-NEXT: buffer_gl1_inv
@@ -297,9 +296,9 @@ define amdgpu_kernel void @local_atomic_min_ret_i64(ptr addrspace(1) %out, ptr a
; GFX11-LABEL: local_atomic_min_ret_i64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x8
-; GFX11-NEXT: v_mov_b32_e32 v0, 42
+; GFX11-NEXT: v_dual_mov_b32 v0, 42 :: v_dual_mov_b32 v1, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s0
+; GFX11-NEXT: v_mov_b32_e32 v2, s0
; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: ds_min_rtn_i64 v[0:1], v2, v[0:1]
@@ -390,8 +389,8 @@ define amdgpu_kernel void @global_atomic_max_ret_i64(ptr addrspace(1) %out, ptr
; GFX11-LABEL: global_atomic_max_ret_i64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
-; GFX11-NEXT: v_mov_b32_e32 v0, 42
-; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, 0
+; GFX11-NEXT: v_dual_mov_b32 v0, 42 :: v_dual_mov_b32 v1, 0
+; GFX11-NEXT: v_mov_b32_e32 v2, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: global_atomic_max_i64 v[0:1], v2, v[0:1], s[2:3] glc
; GFX11-NEXT: s_waitcnt vmcnt(0)
@@ -463,8 +462,8 @@ define amdgpu_kernel void @flat_atomic_max_ret_i64(ptr addrspace(1) %out, ptr %p
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
; GFX9-NEXT: s_add_u32 flat_scratch_lo, s12, s17
-; GFX9-NEXT: v_mov_b32_e32 v0, 42
; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s13, 0
+; GFX9-NEXT: v_mov_b32_e32 v0, 42
; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v2, s2
@@ -499,10 +498,9 @@ define amdgpu_kernel void @flat_atomic_max_ret_i64(ptr addrspace(1) %out, ptr %p
; GFX11-LABEL: flat_atomic_max_ret_i64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
-; GFX11-NEXT: v_mov_b32_e32 v0, 42
+; GFX11-NEXT: v_dual_mov_b32 v0, 42 :: v_dual_mov_b32 v1, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s2
-; GFX11-NEXT: v_mov_b32_e32 v3, s3
+; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX11-NEXT: flat_atomic_max_i64 v[0:1], v[2:3], v[0:1] glc
; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-NEXT: buffer_gl1_inv
@@ -596,9 +594,9 @@ define amdgpu_kernel void @local_atomic_max_ret_i64(ptr addrspace(1) %out, ptr a
; GFX11-LABEL: local_atomic_max_ret_i64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x8
-; GFX11-NEXT: v_mov_b32_e32 v0, 42
+; GFX11-NEXT: v_dual_mov_b32 v0, 42 :: v_dual_mov_b32 v1, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s0
+; GFX11-NEXT: v_mov_b32_e32 v2, s0
; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: ds_max_rtn_i64 v[0:1], v2, v[0:1]
@@ -689,8 +687,8 @@ define amdgpu_kernel void @global_atomic_umin_ret_i64(ptr addrspace(1) %out, ptr
; GFX11-LABEL: global_atomic_umin_ret_i64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
-; GFX11-NEXT: v_mov_b32_e32 v0, 42
-; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, 0
+; GFX11-NEXT: v_dual_mov_b32 v0, 42 :: v_dual_mov_b32 v1, 0
+; GFX11-NEXT: v_mov_b32_e32 v2, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: global_atomic_min_u64 v[0:1], v2, v[0:1], s[2:3] glc
; GFX11-NEXT: s_waitcnt vmcnt(0)
@@ -762,8 +760,8 @@ define amdgpu_kernel void @flat_atomic_umin_ret_i64(ptr addrspace(1) %out, ptr %
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
; GFX9-NEXT: s_add_u32 flat_scratch_lo, s12, s17
-; GFX9-NEXT: v_mov_b32_e32 v0, 42
; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s13, 0
+; GFX9-NEXT: v_mov_b32_e32 v0, 42
; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v2, s2
@@ -798,10 +796,9 @@ define amdgpu_kernel void @flat_atomic_umin_ret_i64(ptr addrspace(1) %out, ptr %
; GFX11-LABEL: flat_atomic_umin_ret_i64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
-; GFX11-NEXT: v_mov_b32_e32 v0, 42
+; GFX11-NEXT: v_dual_mov_b32 v0, 42 :: v_dual_mov_b32 v1, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s2
-; GFX11-NEXT: v_mov_b32_e32 v3, s3
+; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX11-NEXT: flat_atomic_min_u64 v[0:1], v[2:3], v[0:1] glc
; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-NEXT: buffer_gl1_inv
@@ -895,9 +892,9 @@ define amdgpu_kernel void @local_atomic_umin_ret_i64(ptr addrspace(1) %out, ptr
; GFX11-LABEL: local_atomic_umin_ret_i64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x8
-; GFX11-NEXT: v_mov_b32_e32 v0, 42
+; GFX11-NEXT: v_dual_mov_b32 v0, 42 :: v_dual_mov_b32 v1, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s0
+; GFX11-NEXT: v_mov_b32_e32 v2, s0
; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: ds_min_rtn_u64 v[0:1], v2, v[0:1]
@@ -988,8 +985,8 @@ define amdgpu_kernel void @global_atomic_umax_ret_i64(ptr addrspace(1) %out, ptr
; GFX11-LABEL: global_atomic_umax_ret_i64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
-; GFX11-NEXT: v_mov_b32_e32 v0, 42
-; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, 0
+; GFX11-NEXT: v_dual_mov_b32 v0, 42 :: v_dual_mov_b32 v1, 0
+; GFX11-NEXT: v_mov_b32_e32 v2, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: global_atomic_max_u64 v[0:1], v2, v[0:1], s[2:3] glc
; GFX11-NEXT: s_waitcnt vmcnt(0)
@@ -1061,8 +1058,8 @@ define amdgpu_kernel void @flat_atomic_umax_ret_i64(ptr addrspace(1) %out, ptr %
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
; GFX9-NEXT: s_add_u32 flat_scratch_lo, s12, s17
-; GFX9-NEXT: v_mov_b32_e32 v0, 42
; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s13, 0
+; GFX9-NEXT: v_mov_b32_e32 v0, 42
; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v2, s2
@@ -1097,10 +1094,9 @@ define amdgpu_kernel void @flat_atomic_umax_ret_i64(ptr addrspace(1) %out, ptr %
; GFX11-LABEL: flat_atomic_umax_ret_i64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
-; GFX11-NEXT: v_mov_b32_e32 v0, 42
+; GFX11-NEXT: v_dual_mov_b32 v0, 42 :: v_dual_mov_b32 v1, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s2
-; GFX11-NEXT: v_mov_b32_e32 v3, s3
+; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX11-NEXT: flat_atomic_max_u64 v[0:1], v[2:3], v[0:1] glc
; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-NEXT: buffer_gl1_inv
@@ -1194,9 +1190,9 @@ define amdgpu_kernel void @local_atomic_umax_ret_i64(ptr addrspace(1) %out, ptr
; GFX11-LABEL: local_atomic_umax_ret_i64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x8
-; GFX11-NEXT: v_mov_b32_e32 v0, 42
+; GFX11-NEXT: v_dual_mov_b32 v0, 42 :: v_dual_mov_b32 v1, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s0
+; GFX11-NEXT: v_mov_b32_e32 v2, s0
; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: ds_max_rtn_u64 v[0:1], v2, v[0:1]
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_udec_wrap.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_udec_wrap.ll
index df3693620bdb7..f0c8dae40280a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_udec_wrap.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_udec_wrap.ll
@@ -1716,9 +1716,9 @@ define amdgpu_kernel void @flat_atomic_dec_ret_i64(ptr %out, ptr %ptr) #1 {
; CI: ; %bb.0:
; CI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
; CI-NEXT: s_add_i32 s12, s12, s17
-; CI-NEXT: v_mov_b32_e32 v0, 42
; CI-NEXT: s_mov_b32 flat_scratch_lo, s13
; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; CI-NEXT: v_mov_b32_e32 v0, 42
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v2, s2
; CI-NEXT: v_mov_b32_e32 v1, 0
@@ -1740,9 +1740,9 @@ define amdgpu_kernel void @flat_atomic_dec_ret_i64(ptr %out, ptr %ptr) #1 {
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
; VI-NEXT: s_add_i32 s12, s12, s17
-; VI-NEXT: v_mov_b32_e32 v0, 42
; VI-NEXT: s_mov_b32 flat_scratch_lo, s13
; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; VI-NEXT: v_mov_b32_e32 v0, 42
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v1, 0
@@ -1764,8 +1764,8 @@ define amdgpu_kernel void @flat_atomic_dec_ret_i64(ptr %out, ptr %ptr) #1 {
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
; GFX9-NEXT: s_add_u32 flat_scratch_lo, s12, s17
-; GFX9-NEXT: v_mov_b32_e32 v0, 42
; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s13, 0
+; GFX9-NEXT: v_mov_b32_e32 v0, 42
; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v2, s2
@@ -1802,10 +1802,9 @@ define amdgpu_kernel void @flat_atomic_dec_ret_i64(ptr %out, ptr %ptr) #1 {
; GFX11-LABEL: flat_atomic_dec_ret_i64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
-; GFX11-NEXT: v_mov_b32_e32 v0, 42
+; GFX11-NEXT: v_dual_mov_b32 v0, 42 :: v_dual_mov_b32 v1, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s2
-; GFX11-NEXT: v_mov_b32_e32 v3, s3
+; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX11-NEXT: flat_atomic_dec_u64 v[0:1], v[2:3], v[0:1] glc
; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-NEXT: buffer_gl1_inv
@@ -1824,8 +1823,8 @@ define amdgpu_kernel void @flat_atomic_dec_ret_i64_offset(ptr %out, ptr %ptr) #1
; CI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
; CI-NEXT: s_add_i32 s12, s12, s17
; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
-; CI-NEXT: v_mov_b32_e32 v0, 42
; CI-NEXT: s_mov_b32 flat_scratch_lo, s13
+; CI-NEXT: v_mov_b32_e32 v0, 42
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_add_u32 s2, s2, 32
; CI-NEXT: s_addc_u32 s3, s3, 0
@@ -1850,8 +1849,8 @@ define amdgpu_kernel void @flat_atomic_dec_ret_i64_offset(ptr %out, ptr %ptr) #1
; VI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
; VI-NEXT: s_add_i32 s12, s12, s17
; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
-; VI-NEXT: v_mov_b32_e32 v0, 42
; VI-NEXT: s_mov_b32 flat_scratch_lo, s13
+; VI-NEXT: v_mov_b32_e32 v0, 42
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_add_u32 s2, s2, 32
; VI-NEXT: s_addc_u32 s3, s3, 0
@@ -1875,8 +1874,8 @@ define amdgpu_kernel void @flat_atomic_dec_ret_i64_offset(ptr %out, ptr %ptr) #1
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
; GFX9-NEXT: s_add_u32 flat_scratch_lo, s12, s17
-; GFX9-NEXT: v_mov_b32_e32 v0, 42
; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s13, 0
+; GFX9-NEXT: v_mov_b32_e32 v0, 42
; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v2, s2
@@ -1915,10 +1914,9 @@ define amdgpu_kernel void @flat_atomic_dec_ret_i64_offset(ptr %out, ptr %ptr) #1
; GFX11-LABEL: flat_atomic_dec_ret_i64_offset:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
-; GFX11-NEXT: v_mov_b32_e32 v0, 42
+; GFX11-NEXT: v_dual_mov_b32 v0, 42 :: v_dual_mov_b32 v1, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s2
-; GFX11-NEXT: v_mov_b32_e32 v3, s3
+; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX11-NEXT: flat_atomic_dec_u64 v[0:1], v[2:3], v[0:1] offset:32 glc
; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-NEXT: buffer_gl1_inv
@@ -1937,9 +1935,9 @@ define amdgpu_kernel void @flat_atomic_dec_noret_i64(ptr %ptr) #1 {
; CI: ; %bb.0:
; CI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
; CI-NEXT: s_add_i32 s12, s12, s17
-; CI-NEXT: v_mov_b32_e32 v0, 42
; CI-NEXT: s_mov_b32 flat_scratch_lo, s13
; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; CI-NEXT: v_mov_b32_e32 v0, 42
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v3, s1
; CI-NEXT: v_mov_b32_e32 v1, 0
@@ -1953,9 +1951,9 @@ define amdgpu_kernel void @flat_atomic_dec_noret_i64(ptr %ptr) #1 {
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
; VI-NEXT: s_add_i32 s12, s12, s17
-; VI-NEXT: v_mov_b32_e32 v0, 42
; VI-NEXT: s_mov_b32 flat_scratch_lo, s13
; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; VI-NEXT: v_mov_b32_e32 v0, 42
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v1, 0
@@ -1969,8 +1967,8 @@ define amdgpu_kernel void @flat_atomic_dec_noret_i64(ptr %ptr) #1 {
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
; GFX9-NEXT: s_add_u32 flat_scratch_lo, s12, s17
-; GFX9-NEXT: v_mov_b32_e32 v0, 42
; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s13, 0
+; GFX9-NEXT: v_mov_b32_e32 v0, 42
; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v3, s1
@@ -2002,8 +2000,7 @@ define amdgpu_kernel void @flat_atomic_dec_noret_i64(ptr %ptr) #1 {
; GFX11-LABEL: flat_atomic_dec_noret_i64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
-; GFX11-NEXT: v_mov_b32_e32 v0, 42
-; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: v_dual_mov_b32 v0, 42 :: v_dual_mov_b32 v1, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: ...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/190379
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