[llvm] [Target] Add ProcResGroupWithBufferSum TableGen class (PR #190337)

[Tomer Shafir via llvm-commits]

https://github.com/tomershafir created https://github.com/llvm/llvm-project/pull/190337

This patch adds a new class that should improve RS modeling for out-of-order processors, and MCA accuracy. `ProcResGroupWithBufferSum` sums `BufferSize` of the units that compose the resource group.

>From 393bb1fee25caef8d251c57c6a0da66a28bedc22 Mon Sep 17 00:00:00 2001
From: tomershafir <tomer.shafir8 at gmail.com>
Date: Fri, 3 Apr 2026 15:01:05 +0300
Subject: [PATCH] [Target] Add ProcResGroupWithBufferSum TableGen class

This patch adds a new class that should improve RS modeling for out-of-order processors, and MCA accuracy. `ProcResGroupWithBufferSum` sums `BufferSize` of the units that compose the resource group.
---
 llvm/include/llvm/Target/TargetSchedule.td    |  9 ++++
 .../TableGen/ProcResGroupWithBufferSum.td     | 49 +++++++++++++++++++
 2 files changed, 58 insertions(+)
 create mode 100644 llvm/test/TableGen/ProcResGroupWithBufferSum.td

diff --git a/llvm/include/llvm/Target/TargetSchedule.td b/llvm/include/llvm/Target/TargetSchedule.td
index c68323389b827..182b39a625174 100644
--- a/llvm/include/llvm/Target/TargetSchedule.td
+++ b/llvm/include/llvm/Target/TargetSchedule.td
@@ -203,6 +203,15 @@ class ProcResGroup<list<ProcResource> resources> : ProcResourceKind {
   int BufferSize = -1;
 }
 
+// Define resource groups where the buffer size is the sum of individual 
+// resource buffer sizes. This is useful for modeling a distributed reservation
+// station (RS) micro-architecture, where each execution unit has its own RS,
+// and the group's total capacity is the sum of all individual unit capacities.
+class ProcResGroupWithBufferSum<list<ProcResource> resources>
+    : ProcResGroup<resources> {
+  let BufferSize = !foldl(0, Resources, acc, unit, !add(acc, unit.BufferSize));
+}
+
 // A target architecture may define SchedReadWrite types and associate
 // them with instruction operands.
 class SchedReadWrite;
diff --git a/llvm/test/TableGen/ProcResGroupWithBufferSum.td b/llvm/test/TableGen/ProcResGroupWithBufferSum.td
new file mode 100644
index 0000000000000..5e93fe6d0d16a
--- /dev/null
+++ b/llvm/test/TableGen/ProcResGroupWithBufferSum.td
@@ -0,0 +1,49 @@
+// RUN: llvm-tblgen -gen-subtarget -I %p/../../include %s 2>&1 | FileCheck %s
+
+// Verify that ProcResGroupWithBufferSum computes BufferSize as the sum of
+// individual resource buffer sizes.
+
+include "llvm/Target/Target.td"
+
+def MyTarget : Target;
+
+let OutOperandList = (outs), InOperandList = (ins) in {
+  def Inst_A : Instruction;
+}
+
+let CompleteModel = 0 in {
+  def SchedModel_A : SchedMachineModel;
+}
+
+def WriteInst_A : SchedWrite;
+
+let SchedModel = SchedModel_A in {
+
+def ResA : ProcResource<1> {
+  let BufferSize = 3;
+}
+
+def ResB : ProcResource<1> {
+  let BufferSize = 5;
+}
+
+def ResC : ProcResource<1> {
+  let BufferSize = 2;
+}
+
+// BufferSize should be 3 + 5 + 2 = 10.
+def ResGroup : ProcResGroupWithBufferSum<[ResA, ResB, ResC]>;
+
+def : WriteRes<WriteInst_A, [ResGroup]>;
+def : InstRW<[WriteInst_A], (instrs Inst_A)>;
+
+} // let SchedModel = SchedModel_A
+
+def ProcessorA : ProcessorModel<"ProcessorA", SchedModel_A, []>;
+
+// CHECK: // {Name, NumUnits, SuperIdx, BufferSize, SubUnitsIdxBegin}
+// CHECK: static const llvm::MCProcResourceDesc SchedModel_AProcResources[]
+// CHECK-DAG: {"ResA", 1, 0, 3, nullptr}
+// CHECK-DAG: {"ResB", 1, 0, 5, nullptr}
+// CHECK-DAG: {"ResC", 1, 0, 2, nullptr}
+// CHECK: {"ResGroup", 3, 0, 10, SchedModel_AProcResourceSubUnits