[llvm] [RFC][IR] Add llvm.masked.{udiv, sdiv, urem, srem} intrinsics (PR #189705)

[Luke Lau via llvm-commits]

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@@ -5348,6 +5433,19 @@ SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) {
                      {InOp1, InOp2, Mask, N->getOperand(3)}, N->getFlags());
 }
 
+SDValue DAGTypeLegalizer::WidenVecRes_MaskedBinary(SDNode *N) {
+  SDLoc dl(N);
+  EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
+  SDValue InOp1 = GetWidenedVector(N->getOperand(0));
+  SDValue InOp2 = GetWidenedVector(N->getOperand(1));
+  SDValue Mask = N->getOperand(2);
+  EVT WideMaskVT = WidenVT.changeVectorElementType(
+      *DAG.getContext(), Mask.getValueType().getVectorElementType());
+  Mask = ModifyToType(Mask, WideMaskVT, true);
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lukel97 wrote:

Done in ffd9d6753fd1ac9e79fdfb4360bbb9023125c080

https://github.com/llvm/llvm-project/pull/189705