[llvm] [RFC][IR] Add llvm.masked.{udiv, sdiv, urem, srem} intrinsics (PR #189705)

[Luke Lau via llvm-commits]

================
@@ -27895,6 +27895,116 @@ The '``llvm.masked.compressstore``' intrinsic is designed for compressing data i
 
 Other targets may support this intrinsic differently, for example, by lowering it into a sequence of branches that guard scalar store operations.
 
+Masked Vector Arithmetic Intrinsics
+-----------------------------------
+
+'``llvm.masked.udiv.*``' Intrinsics
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Syntax:
+"""""""
+This is an overloaded intrinsic.
+
+::
+
+      declare <8 x i32> @llvm.masked.udiv.v8i32(<8 x i32> <op1>, <8 x i32> <op2>, <8 x i1> <mask>)
+      declare <vscale x 2 x i64> @llvm.masked.udiv.nxv2i64(<vscale x 2 x i64> <op1>, <vscale x 2 x i64> <op2>, <vscale x 2 x i1> <mask>)
+
+Overview:
+"""""""""
+
+Performs unsigned division (:ref:`udiv <i_udiv>`) of two vectors of integers, but only on enabled lanes.
+
+Arguments:
+""""""""""
+
+The first two arguments and the result have the same vector of integer type. The third argument is the vector mask and has the same number of elements as the result vector type.
+
+Semantics:
+""""""""""
+
+Unlike :ref:`udiv <i_udiv>`, disabled lanes produce poison and division by zero on disabled lanes is not undefined behavior. Division by zero on enabled lanes is still undefined behavior.
----------------
lukel97 wrote:

Changed the wording in 3724e9ed03e018a917f29bead0ddb8a9988eabce

https://github.com/llvm/llvm-project/pull/189705