[llvm] [RFC][IR] Add llvm.masked.{udiv, sdiv, urem, srem} intrinsics (PR #189705)

[Luke Lau via llvm-commits]

================
@@ -27895,6 +27895,116 @@ The '``llvm.masked.compressstore``' intrinsic is designed for compressing data i
 
 Other targets may support this intrinsic differently, for example, by lowering it into a sequence of branches that guard scalar store operations.
 
+Masked Vector Arithmetic Intrinsics
+-----------------------------------
+
+'``llvm.masked.udiv.*``' Intrinsics
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Syntax:
+"""""""
+This is an overloaded intrinsic.
+
+::
+
+      declare <8 x i32> @llvm.masked.udiv.v8i32(<8 x i32> <op1>, <8 x i32> <op2>, <8 x i1> <mask>)
----------------
lukel97 wrote:

RISC-V can have a passthru on the divide instructions, I'm not sure about SVE. 

But the way we usually represent passthru semantics on RISC-V with VP intrinsics is by using a vp.merge. A RISC-V MIR pass then folds the vp.merge into the passthru. The equivalent here would be with a select:

```llvm
%div = call <4 x i32> @llvm.masked.udiv(<4 x i32> %x, <4 x i32> %y, <4 x i> %m)
%res = select <4 x i1> %m, <4 x i32> %div, <4 x i32> %passthru
```

I guess in theory if we had something that wanted to preserve a passthru then having it in the intrinsic itself would make the cost modelling a bit easier. But as you say we don't have any users for it currently, so I just went with the passthru-less version in this PR since it was simpler. 


https://github.com/llvm/llvm-project/pull/189705