[llvm] [RFC][IR] Add llvm.masked.{udiv, sdiv, urem, srem} intrinsics (PR #189705)

[David Green via llvm-commits]

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@@ -27895,6 +27895,116 @@ The '``llvm.masked.compressstore``' intrinsic is designed for compressing data i
 
 Other targets may support this intrinsic differently, for example, by lowering it into a sequence of branches that guard scalar store operations.
 
+Masked Vector Arithmetic Intrinsics
+-----------------------------------
+
+'``llvm.masked.udiv.*``' Intrinsics
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Syntax:
+"""""""
+This is an overloaded intrinsic.
+
+::
+
+      declare <8 x i32> @llvm.masked.udiv.v8i32(<8 x i32> <op1>, <8 x i32> <op2>, <8 x i1> <mask>)
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davemgreen wrote:

Is it worth adding a passthru argument for what happens with off lanes, like the one present on masked loads? In practice we might always use poison, but it lets the intrinsics be more useful for architectures that have a separate passthru on the instruction. (I don't know of any architectures where that is true through, MVE doesn't have a vector divide. It has other vector instructions that update a destination register though, acting as a passthru argument).

https://github.com/llvm/llvm-project/pull/189705