[llvm] [CHERIoT] Define a RISCV target feature for XCheriot. (PR #189968)

[Owen Anderson via llvm-commits]

resistor wrote:

> That is, for RVY, the intent is that AUIPC gives an integer result for I/E and a capability result for Y. Whereas for Xcheriot you're RVE yet always(?) in capability mode (or perhaps borrowing the orthogonal "cap-mode" feature we did for the University's Xcheri)?

The plan that @arichardson and I had discussed was that there "cap-mode" won't be a feature in upstream, but will be a `Predicate`, which will be defined as something like "Subtarget->isYBase() || Subtarget->hasVendorFeatureXCheriot()", so that we don't have to add additional `NotCheriot` qualifiers on things like integer `AUIPC`

https://github.com/llvm/llvm-project/pull/189968