[llvm] [CHERIoT] Define a RISCV target feature for XCheriot. (PR #189968)

[Jessica Clarke via llvm-commits]

jrtc27 wrote:

That is, for RVY, the intent is that AUIPC gives an integer result for I/E and a capability result for Y. Whereas for Xcheriot you're RVE yet always(?) in capability mode (or perhaps borrowing the orthogonal "cap-mode" feature we did for the University's Xcheri)?

https://github.com/llvm/llvm-project/pull/189968