[llvm] [RegisterScavenging] Respect early-clobber when scavenging registers (PR #184814)

[Dominik Steenken via llvm-commits]

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@@ -295,14 +295,39 @@ RegScavenger::spill(Register Reg, const TargetRegisterClass &RC, int SPAdj,
 Register RegScavenger::scavengeRegisterBackwards(const TargetRegisterClass &RC,
                                                  MachineBasicBlock::iterator To,
                                                  bool RestoreAfter, int SPAdj,
-                                                 bool AllowSpill) {
+                                                 bool AllowSpill,
+                                                 bool InspectNext) {
   const MachineBasicBlock &MBB = *To->getParent();
   const MachineFunction &MF = *MBB.getParent();
 
+  // Obtain a list of candidate registers in allocation order of RC.
+  // If the instruction at MBBI has any early-clobber def regs, we must exclude
+  // them from the candidates, without including the whole of that instruction's
+  // constraints. We achieve this by filtering the allocation order of RC.
+  // First, determine if there are any such early-clobber def regs.
+  SmallVector<MCPhysReg> FilteredAllocationOrder;
+  SmallVector<MCPhysReg> ECDefs;
+  if (InspectNext)
+    for (const MachineOperand &Op : MBBI->operands())
+      if (Op.isReg() && Op.isDef() && Op.isEarlyClobber())
+        ECDefs.push_back(Op.getReg());
+  if (!ECDefs.empty()) {
+    // If so, obtain the filtered version.
+    for (MCPhysReg Reg : RC.getRawAllocationOrder(MF)) {
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dominik-steenken wrote:

I can and i have in this most recent version. Personally, i find this considerably less readable, but am fine going ahead with either version.

https://github.com/llvm/llvm-project/pull/184814