[llvm] [BOLT] Optimize the codegen of createLoadImmediate for AArch64. (PR #137413)

[Shanzhi Chen via llvm-commits]

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@@ -2867,28 +2174,86 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
 
   InstructionListType createLoadImmediate(const MCPhysReg Dest,
                                           uint64_t Imm) const override {
+    const MCRegisterClass RC = RegInfo->getRegClass(Dest);
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chenshanzhi wrote:

Hi, @rcorcs . Thanks for your code to handle both 32-bit and 64-bit registers. 
And I think the input argument of `getRegClass()` should be an `enum` value of register class like `AArch64::GPR64RegClassID`, rather than an `enum` value of register like `AArch64::X0`.

https://github.com/llvm/llvm-project/pull/137413