[llvm] [RISCV] Add guard to prevent GPRPair merge on targets without Zdinx or P (PR #186600)

[Kavin Gnanapandithan via llvm-commits]

https://github.com/KavinTheG created https://github.com/llvm/llvm-project/pull/186600

Resolves #186527.

The issue points out that GPRPair merge logic in the RISCVMoveMerger pass was being called on a target without `zdinx` or `experimental-P`, triggering an unreachable in `getGPRPairCopyOpcode`.

This patch fixes this issue by guarding `isEvenRegisterCopy` and `isOddRegisterCopy` to return false when neither Zdinx nor P is present.

>From a3d0b8e02f0074df3c487195920fd5301d38aee0 Mon Sep 17 00:00:00 2001
From: Kavin Gnanapandithan <kavin.balag at gmail.com>
Date: Fri, 13 Mar 2026 23:18:31 -0400
Subject: [PATCH] [RISCV] Add guard to prevent GPRPair merge on targets without
 Zdinx or P

In the RISCVMoveMerger pass, mergeGPRPairInsns was being called on
targets with zcmp/xqccmp enabled, triggering an unreachable in
getGPRPairCopyOpcode. Fix by guarding isEvenRegisterCopy and
isOddRegisterCopy to return false when neither Zdinx nor P is present.
---
 llvm/lib/Target/RISCV/RISCVMoveMerger.cpp     |  4 ++
 .../CodeGen/RISCV/rv32-move-merge-crash.ll    | 67 +++++++++++++++++++
 2 files changed, 71 insertions(+)
 create mode 100644 llvm/test/CodeGen/RISCV/rv32-move-merge-crash.ll

diff --git a/llvm/lib/Target/RISCV/RISCVMoveMerger.cpp b/llvm/lib/Target/RISCV/RISCVMoveMerger.cpp
index 278b76c05b849..367399a905b27 100644
--- a/llvm/lib/Target/RISCV/RISCVMoveMerger.cpp
+++ b/llvm/lib/Target/RISCV/RISCVMoveMerger.cpp
@@ -95,6 +95,8 @@ bool RISCVMoveMerge::isEvenRegisterCopy(const DestSourcePair &RegPair) {
   if (Source == Destination)
     return false;
 
+  if (!ST->hasStdExtZdinx() && !ST->hasStdExtP())
+    return false;
   Register SrcPair = TRI->getMatchingSuperReg(Source, RISCV::sub_gpr_even,
                                               &RISCV::GPRPairRegClass);
   Register DestPair = TRI->getMatchingSuperReg(Destination, RISCV::sub_gpr_even,
@@ -110,6 +112,8 @@ bool RISCVMoveMerge::isOddRegisterCopy(const DestSourcePair &RegPair) {
   if (Source == Destination)
     return false;
 
+  if (!ST->hasStdExtZdinx() && !ST->hasStdExtP())
+    return false;
   Register SrcPair = TRI->getMatchingSuperReg(Source, RISCV::sub_gpr_odd,
                                               &RISCV::GPRPairRegClass);
   Register DestPair = TRI->getMatchingSuperReg(Destination, RISCV::sub_gpr_odd,
diff --git a/llvm/test/CodeGen/RISCV/rv32-move-merge-crash.ll b/llvm/test/CodeGen/RISCV/rv32-move-merge-crash.ll
new file mode 100644
index 0000000000000..a9a6077ab7051
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rv32-move-merge-crash.ll
@@ -0,0 +1,67 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=riscv32 -mattr=+m,+zcmp -verify-machineinstrs < %s | FileCheck %s --check-prefix=ZCMP
+; RUN: llc -mtriple=riscv32 -mattr=+m,+xqccmp -verify-machineinstrs < %s | FileCheck %s --check-prefix=XQCCMP
+; RUN: llc -mtriple=riscv32 -mattr=+m,+zcmp,+experimental-p -verify-machineinstrs < %s | FileCheck %s --check-prefix=ZCMP-P
+
+; This source code exposed a crash in the RISC-V Zcmp move merging pass.
+; The root cause was: mergeGPRPairInsns being called on targets without
+; Zdinx or P extension support, triggering an unreachable in
+; getGPRPairCopyOpcode.
+
+define void @test(i32 %arg0, i32 %arg1) nounwind {
+; ZCMP-LABEL: test:
+; ZCMP:       # %bb.0: # %entry
+; ZCMP-NEXT:    #APP
+; ZCMP-NEXT:    csrr a4, 66
+; ZCMP-NEXT:    #NO_APP
+; ZCMP-NEXT:    #APP
+; ZCMP-NEXT:    csrr a5, 67
+; ZCMP-NEXT:    #NO_APP
+; ZCMP-NEXT:    #APP
+; ZCMP-NEXT:    #NO_APP
+; ZCMP-NEXT:    mv a0, a4
+; ZCMP-NEXT:    mv a1, a5
+; ZCMP-NEXT:    tail foo
+;
+; XQCCMP-LABEL: test:
+; XQCCMP:       # %bb.0: # %entry
+; XQCCMP-NEXT:    #APP
+; XQCCMP-NEXT:    csrr a4, 66
+; XQCCMP-NEXT:    #NO_APP
+; XQCCMP-NEXT:    #APP
+; XQCCMP-NEXT:    csrr a5, 67
+; XQCCMP-NEXT:    #NO_APP
+; XQCCMP-NEXT:    #APP
+; XQCCMP-NEXT:    #NO_APP
+; XQCCMP-NEXT:    mv a0, a4
+; XQCCMP-NEXT:    mv a1, a5
+; XQCCMP-NEXT:    tail foo
+;
+; ZCMP-P-LABEL: test:
+; ZCMP-P:       # %bb.0: # %entry
+; ZCMP-P-NEXT:    #APP
+; ZCMP-P-NEXT:    csrr a4, 66
+; ZCMP-P-NEXT:    #NO_APP
+; ZCMP-P-NEXT:    #APP
+; ZCMP-P-NEXT:    csrr a5, 67
+; ZCMP-P-NEXT:    #NO_APP
+; ZCMP-P-NEXT:    #APP
+; ZCMP-P-NEXT:    #NO_APP
+; ZCMP-P-NEXT:    padd.dw a0, a4, zero
+; ZCMP-P-NEXT:    tail foo
+entry:
+  %0 = tail call i32 asm sideeffect "csrr $0, 0x42", "=r"()
+  %1 = tail call i32 asm sideeffect "csrr $0, 0x43", "=r"()
+  tail call void asm sideeffect "", "~{x17},~{x10},~{x11},~{x12},~{x13}"()
+  %cmp = icmp eq i32 %0, 11
+  br i1 %cmp, label %if.else, label %if.else
+
+if.else:
+  %call = tail call i32 @foo(i32 %0, i32 %1)
+  br label %if.end
+
+if.end:
+  ret void
+}
+
+declare i32 @foo(i32, i32)