[llvm] 696208b - [RISCV] Add codegen patterns to support short forward branches with immediates (#185643)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 13 16:55:44 PDT 2026
Author: quic_hchandel
Date: 2026-03-13T16:55:39-07:00
New Revision: 696208b72ce88372e23ab41435939e09aa5a9594
URL: https://github.com/llvm/llvm-project/commit/696208b72ce88372e23ab41435939e09aa5a9594
DIFF: https://github.com/llvm/llvm-project/commit/696208b72ce88372e23ab41435939e09aa5a9594.diff
LOG: [RISCV] Add codegen patterns to support short forward branches with immediates (#185643)
This is a follow-up to #182456. This PR adds support for short forward
branches where branches are from Qualcomm uC `Xqcibi` extension.
Added:
llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_32_eq.ll
llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_32_ne.ll
llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_32_sge.ll
llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_32_slt.ll
llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_32_uge.ll
llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_32_ult.ll
llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_48_eq.ll
llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_48_ne.ll
llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_48_sge.ll
llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_48_slt.ll
llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_48_uge.ll
llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_48_ult.ll
Modified:
llvm/lib/Target/RISCV/RISCVFeatures.td
llvm/lib/Target/RISCV/RISCVInstrInfoSFB.td
llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
llvm/test/CodeGen/RISCV/features-info.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 356e742dbbec9..01ab6054c5e64 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -2001,6 +2001,13 @@ def TuneShortForwardBranchILoad
[TuneShortForwardBranchIALU]>;
def HasShortForwardBranchILoad : Predicate<"Subtarget->hasShortForwardBranchILoad()">;
+def TuneShortForwardBranchImm
+ : SubtargetFeature<"short-forward-branch-imm", "HasShortForwardBranchImm",
+ "true", "Enable short forward branch optimization for branches with immediates",
+ [TuneShortForwardBranchIALU]>;
+def HasShortForwardBranchImm : Predicate<"Subtarget->hasShortForwardBranchImm()">;
+def NoShortForwardBranchImm : Predicate<"!Subtarget->hasShortForwardBranchImm()">;
+
// Some subtargets require a S2V transfer buffer to move scalars into vectors.
// FIXME: Forming .vx/.vf/.wx/.wf can reduce register pressure.
def TuneNoSinkSplatOperands
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoSFB.td b/llvm/lib/Target/RISCV/RISCVInstrInfoSFB.td
index c02aa06c66c64..3838c1c4b1095 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoSFB.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoSFB.td
@@ -29,6 +29,46 @@ def CCtoRISCVBCC : SDNodeXForm<cond, [{
return CurDAG->getTargetConstant(BccOpcode, SDLoc(N), MVT::i32);
}]>;
+// cond -> bcc_opcode (QC_E_BccI)
+def CCtoQC_E_BccI : SDNodeXForm<cond, [{
+ ISD::CondCode CC = N->get();
+ RISCVCC::CondCode RvCC = getRISCVCCForIntCC(CC);
+ RvCC = RISCVCC::getInverseBranchCondition(RvCC);
+ unsigned SelectOpc;
+ switch (RvCC) {
+ case RISCVCC::COND_LTU:
+ case RISCVCC::COND_GEU:
+ SelectOpc = RISCV::Select_GPRNoX0_Using_CC_UImm16NonZero_QC;
+ break;
+ default:
+ // EQ/NE/LT/GE treated as signed condition codes
+ SelectOpc = RISCV::Select_GPRNoX0_Using_CC_SImm16NonZero_QC;
+ break;
+ }
+ unsigned BccOpcode = RISCVCC::getBrCond(RvCC, SelectOpc);
+ return CurDAG->getTargetConstant(BccOpcode, SDLoc(N), MVT::i32);
+}]>;
+
+// cond -> bcc_opcode (QC_BeqI)
+def CCtoQC_BccI : SDNodeXForm<cond, [{
+ ISD::CondCode CC = N->get();
+ RISCVCC::CondCode RvCC = getRISCVCCForIntCC(CC);
+ RvCC = RISCVCC::getInverseBranchCondition(RvCC);
+ unsigned SelectOpc;
+ switch (RvCC) {
+ case RISCVCC::COND_LTU:
+ case RISCVCC::COND_GEU:
+ SelectOpc = RISCV::Select_GPRNoX0_Using_CC_UImm5NonZero_QC;
+ break;
+ default:
+ // EQ/NE/LT/GE treated as signed condition codes
+ SelectOpc = RISCV::Select_GPRNoX0_Using_CC_SImm5NonZero_QC;
+ break;
+ }
+ unsigned BccOpcode = RISCVCC::getBrCond(RvCC, SelectOpc);
+ return CurDAG->getTargetConstant(BccOpcode, SDLoc(N), MVT::i32);
+}]>;
+
// For each of the short forward branch pseudos, corresponding code for
// getting correct size of the pseduo is needed in getInstSizeInBytes.
let Predicates = [HasShortForwardBranchIALU], isSelect = 1,
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index c2051973be186..efcbefd4f3900 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -1500,6 +1500,12 @@ class SelectQCbi<CondCode Cond, DAGOperand InTyImm, Pseudo OpNode >
(OpNode GPRNoX0:$lhs, InTyImm:$Constant, (CCtoRISCVCC $cc),
GPRNoX0:$truev, GPRNoX0:$falsev)>;
+class SelectQCbiSFB<CondCode Cond, DAGOperand InTyImm, SDNodeXForm xform>
+ : Pat<(riscv_selectcc (i32 GPRNoX0:$lhs), InTyImm:$Constant, Cond:$cc,
+ (i32 GPR:$truev), GPR:$falsev),
+ (PseudoCCMOVGPR GPR:$falsev, GPR:$truev, (xform $cc), GPRNoX0:$lhs,
+ InTyImm:$Constant)>;
+
let Predicates = [HasVendorXqciac, IsRV32] in {
def : Pat<(i32 (add GPRNoX0:$rd, (mul GPRNoX0:$rs1, simm12_lo:$imm12))),
(QC_MULIADD GPRNoX0:$rd, GPRNoX0:$rs1, simm12_lo:$imm12)>;
@@ -1563,6 +1569,22 @@ def : PatGprNoX0GprNoX0<ushlsat, QC_SHLUSAT>;
def : PatGprNoX0GprNoX0<sshlsat, QC_SHLSAT>;
} // Predicates = [HasVendorXqcia, IsRV32]
+let Predicates = [HasShortForwardBranchImm, HasVendorXqcibi, IsRV32] in {
+def : SelectQCbiSFB<SETEQ, simm5nonzero, CCtoQC_BccI>;
+def : SelectQCbiSFB<SETNE, simm5nonzero, CCtoQC_BccI>;
+def : SelectQCbiSFB<SETGE, simm5nonzero, CCtoQC_BccI>;
+def : SelectQCbiSFB<SETLT, simm5nonzero, CCtoQC_BccI>;
+def : SelectQCbiSFB<SETULT, uimm5nonzero, CCtoQC_BccI>;
+def : SelectQCbiSFB<SETUGE, uimm5nonzero, CCtoQC_BccI>;
+
+def : SelectQCbiSFB<SETEQ, simm16nonzero, CCtoQC_E_BccI>;
+def : SelectQCbiSFB<SETGE, simm16nonzero, CCtoQC_E_BccI>;
+def : SelectQCbiSFB<SETLT, simm16nonzero, CCtoQC_E_BccI>;
+def : SelectQCbiSFB<SETNE, simm16nonzero, CCtoQC_E_BccI>;
+def : SelectQCbiSFB<SETULT, uimm16nonzero, CCtoQC_E_BccI>;
+def : SelectQCbiSFB<SETUGE, uimm16nonzero, CCtoQC_E_BccI>;
+}
+
/// Branches
let Predicates = [HasVendorXqcibi, IsRV32] in {
@@ -1579,7 +1601,9 @@ def : Bcci48Pat<SETLT, QC_E_BLTI, simm16nonzero>;
def : Bcci48Pat<SETGE, QC_E_BGEI, simm16nonzero>;
def : Bcci48Pat<SETULT, QC_E_BLTUI, uimm16nonzero>;
def : Bcci48Pat<SETUGE, QC_E_BGEUI, uimm16nonzero>;
+} // let Predicates = [HasVendorXqcibi, IsRV32]
+let Predicates = [HasVendorXqcibi, NoShortForwardBranchImm, IsRV32] in {
def : SelectQCbi<SETEQ, simm5nonzero, Select_GPRNoX0_Using_CC_SImm5NonZero_QC>;
def : SelectQCbi<SETNE, simm5nonzero, Select_GPRNoX0_Using_CC_SImm5NonZero_QC>;
def : SelectQCbi<SETLT, simm5nonzero, Select_GPRNoX0_Using_CC_SImm5NonZero_QC>;
@@ -1593,7 +1617,7 @@ def : SelectQCbi<SETLT, simm16nonzero, Select_GPRNoX0_Using_CC_SImm16NonZero_QC>
def : SelectQCbi<SETGE, simm16nonzero, Select_GPRNoX0_Using_CC_SImm16NonZero_QC>;
def : SelectQCbi<SETULT, uimm16nonzero, Select_GPRNoX0_Using_CC_UImm16NonZero_QC>;
def : SelectQCbi<SETUGE, uimm16nonzero, Select_GPRNoX0_Using_CC_UImm16NonZero_QC>;
-} // let Predicates = [HasVendorXqcibi, IsRV32]
+} // let Predicates = [HasVendorXqcibi, NoShortForwardBranchImm, IsRV32]
def QC_EXTXForm : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(llvm::countr_zero(N->getZExtValue() + 1),
@@ -1654,7 +1678,7 @@ def : QCIMVCCIZeroPat<SETGE, QC_MVGEI>;
def : QCIMVCCIZeroPat<SETUGE, QC_MVGEUI>;
}
-let Predicates = [HasVendorXqcicm, IsRV32] in {
+let Predicates = [HasVendorXqcicm, NoShortForwardBranchImm, IsRV32] in {
// These all use *imm5nonzero because we want to use PseudoCCMOVGPR with X0 when SFB is enabled.
// When SFB is not enabled, the `QCIMVCCIZeroPat`s above will be used if RHS=0.
def : QCIMVCCIPat<SETEQ, QC_MVEQI, simm5nonzero>;
@@ -1716,15 +1740,17 @@ def : QCISELECTICCIPat<SETNE, QC_SELECTINEI>;
def : QCISELECTICCIPatInv<SETEQ, QC_SELECTINEI>;
def : QCISELECTICCIPatInv<SETNE, QC_SELECTIEQI>;
+def : QCISELECTIICCPat<SETEQ, QC_SELECTIIEQ>;
+def : QCISELECTIICCPat<SETNE, QC_SELECTIINE>;
+} // Predicates = [HasVendorXqcics, IsRV32]
+
+let Predicates = [HasVendorXqcics, NoShortForwardBranchImm, IsRV32] in {
def : QCISELECTICCPat<SETEQ, QC_SELECTIEQ>;
def : QCISELECTICCPat<SETNE, QC_SELECTINE>;
def : QCISELECTICCPatInv<SETEQ, QC_SELECTINE>;
def : QCISELECTICCPatInv<SETNE, QC_SELECTIEQ>;
-
-def : QCISELECTIICCPat<SETEQ, QC_SELECTIIEQ>;
-def : QCISELECTIICCPat<SETNE, QC_SELECTIINE>;
-} // Predicates = [HasVendorXqcics, IsRV32]
+} // Predicates = [HasVendorXqcics, NoShortForwardBranchImm, IsRV32]
// Prioritize Xqcicm over these patterns, because Xqcicm is compressible.
let Predicates = [HasVendorXqcics, NoVendorXqcicm, IsRV32] in {
diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll
index 347a53f0fbf79..51d63ac15f36c 100644
--- a/llvm/test/CodeGen/RISCV/features-info.ll
+++ b/llvm/test/CodeGen/RISCV/features-info.ll
@@ -134,6 +134,7 @@
; CHECK-NEXT: short-forward-branch-ialu - Enable short forward branch optimization for RVI base instructions.
; CHECK-NEXT: short-forward-branch-iload - Enable short forward branch optimization for load instructions.
; CHECK-NEXT: short-forward-branch-iminmax - Enable short forward branch optimization for MIN,MAX instructions in Zbb.
+; CHECK-NEXT: short-forward-branch-imm - Enable short forward branch optimization for branches with immediates.
; CHECK-NEXT: short-forward-branch-imul - Enable short forward branch optimization for MUL instruction.
; CHECK-NEXT: shtvala - 'Shtvala' (htval provides all needed values).
; CHECK-NEXT: shvsatpa - 'Shvsatpa' (vsatp supports all modes supported by satp).
diff --git a/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_32_eq.ll b/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_32_eq.ll
new file mode 100644
index 0000000000000..c3cae128b3754
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_32_eq.ll
@@ -0,0 +1,906 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 | FileCheck %s --check-prefixes=RV32I
+; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 -mattr=+xqci,+short-forward-branch-ialu,+short-forward-branch-imul,+short-forward-branch-iload,+short-forward-branch-imm,+m | \
+; RUN: FileCheck %s --check-prefixes=RV32I-SFB-WITH-IMM
+
+define i32 @branch_with_immSFB_mv(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_mv:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 2
+; RV32I-NEXT: beq a2, a3, .LBB0_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: .LBB0_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mv:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.beqi a2, 2, .LBB0_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB0_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %d, 2
+ %sel = select i1 %x, i32 %a, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_mv_zerofalsev(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_mv_zerofalsev:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: addi a2, a2, -2
+; RV32I-NEXT: snez a1, a2
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: and a0, a1, a0
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mv_zerofalsev:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.selectieqi a2, 2, a0, 0
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %d, 2
+ %sel = select i1 %x, i32 %a, i32 0
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_mv_zerofalsev_swapped(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_mv_zerofalsev_swapped:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: addi a2, a2, -2
+; RV32I-NEXT: seqz a1, a2
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: and a0, a1, a0
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mv_zerofalsev_swapped:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.selectinei a2, 2, a0, 0
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %d, 2
+ %sel = select i1 %x, i32 0, i32 %a
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_mv_minusOnefalsev(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_mv_minusOnefalsev:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: addi a2, a2, -2
+; RV32I-NEXT: seqz a1, a2
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: or a0, a1, a0
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mv_minusOnefalsev:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.selectieqi a2, 2, a0, -1
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %d, 2
+ %sel = select i1 %x, i32 %a, i32 -1
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_mv_minusOnefalsev_swapped(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_mv_minusOnefalsev_swapped:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: addi a2, a2, -2
+; RV32I-NEXT: snez a1, a2
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: or a0, a1, a0
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mv_minusOnefalsev_swapped:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.selectinei a2, 2, a0, -1
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %d, 2
+ %sel = select i1 %x, i32 -1, i32 %a
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_add(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_add:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a4, 2
+; RV32I-NEXT: bne a3, a4, .LBB5_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: add a2, a0, a1
+; RV32I-NEXT: .LBB5_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_add:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bnei a3, 2, .LBB5_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: add a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB5_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %d, 2
+ %addi = add i32 %a, %b
+ %sel = select i1 %x, i32 %addi, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_sub(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_sub:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a4, 2
+; RV32I-NEXT: bne a3, a4, .LBB6_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: sub a2, a0, a1
+; RV32I-NEXT: .LBB6_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_sub:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bnei a3, 2, .LBB6_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: sub a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB6_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %d, 2
+ %subi = sub i32 %a, %b
+ %sel = select i1 %x, i32 %subi, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_shl(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_shl:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a4, 2
+; RV32I-NEXT: bne a3, a4, .LBB7_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: sll a2, a0, a1
+; RV32I-NEXT: .LBB7_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_shl:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bnei a3, 2, .LBB7_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: sll a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB7_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %d, 2
+ %shli = shl i32 %a, %b
+ %sel = select i1 %x, i32 %shli, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_lshr(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_lshr:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a4, 2
+; RV32I-NEXT: bne a3, a4, .LBB8_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: srl a2, a0, a1
+; RV32I-NEXT: .LBB8_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lshr:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bnei a3, 2, .LBB8_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: srl a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB8_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %d, 2
+ %lshri = lshr i32 %a, %b
+ %sel = select i1 %x, i32 %lshri, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_ashr(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_ashr:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a4, 2
+; RV32I-NEXT: bne a3, a4, .LBB9_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: sra a2, a0, a1
+; RV32I-NEXT: .LBB9_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_ashr:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bnei a3, 2, .LBB9_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: sra a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB9_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %d, 2
+ %ashri = ashr i32 %a, %b
+ %sel = select i1 %x, i32 %ashri, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_xor(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_xor:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a4, 2
+; RV32I-NEXT: bne a3, a4, .LBB10_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: xor a2, a0, a1
+; RV32I-NEXT: .LBB10_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_xor:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bnei a3, 2, .LBB10_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: xor a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB10_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %d, 2
+ %xori = xor i32 %a, %b
+ %sel = select i1 %x, i32 %xori, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_and(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_and:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a4, 2
+; RV32I-NEXT: bne a3, a4, .LBB11_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: and a2, a0, a1
+; RV32I-NEXT: .LBB11_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_and:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bnei a3, 2, .LBB11_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: and a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB11_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %d, 2
+ %andi = and i32 %a, %b
+ %sel = select i1 %x, i32 %andi, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_or(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_or:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a4, 2
+; RV32I-NEXT: bne a3, a4, .LBB12_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: or a2, a0, a1
+; RV32I-NEXT: .LBB12_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_or:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bnei a3, 2, .LBB12_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: or a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB12_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %d, 2
+ %ori = or i32 %a, %b
+ %sel = select i1 %x, i32 %ori, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_addi(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_addi:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 2
+; RV32I-NEXT: bne a3, a1, .LBB13_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: addi a2, a0, 11
+; RV32I-NEXT: .LBB13_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_addi:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bnei a3, 2, .LBB13_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: addi a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB13_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %d, 2
+ %addi = add i32 %a, 11
+ %sel = select i1 %x, i32 %addi, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_xori(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_xori:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 2
+; RV32I-NEXT: bne a3, a1, .LBB14_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: xori a2, a0, 11
+; RV32I-NEXT: .LBB14_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_xori:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bnei a3, 2, .LBB14_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: xori a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB14_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %d, 2
+ %xori = xor i32 %a, 11
+ %sel = select i1 %x, i32 %xori, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_shli(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_shli:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 2
+; RV32I-NEXT: bne a3, a1, .LBB15_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: slli a2, a0, 11
+; RV32I-NEXT: .LBB15_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_shli:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bnei a3, 2, .LBB15_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: slli a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB15_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %d, 2
+ %shli = shl i32 %a, 11
+ %sel = select i1 %x, i32 %shli, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_lshri(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_lshri:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 2
+; RV32I-NEXT: bne a3, a1, .LBB16_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: srli a2, a0, 11
+; RV32I-NEXT: .LBB16_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lshri:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bnei a3, 2, .LBB16_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: srli a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB16_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %d, 2
+ %lshri = lshr i32 %a, 11
+ %sel = select i1 %x, i32 %lshri, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_ashri(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_ashri:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 2
+; RV32I-NEXT: bne a3, a1, .LBB17_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: srai a2, a0, 11
+; RV32I-NEXT: .LBB17_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_ashri:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bnei a3, 2, .LBB17_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: srai a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB17_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %d, 2
+ %ashri = ashr i32 %a, 11
+ %sel = select i1 %x, i32 %ashri, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_andi(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_andi:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 2
+; RV32I-NEXT: bne a3, a1, .LBB18_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: andi a2, a0, 11
+; RV32I-NEXT: .LBB18_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_andi:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bnei a3, 2, .LBB18_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: andi a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB18_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %d, 2
+ %andi = and i32 %a, 11
+ %sel = select i1 %x, i32 %andi, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_ori(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_ori:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 2
+; RV32I-NEXT: bne a3, a1, .LBB19_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: ori a2, a0, 11
+; RV32I-NEXT: .LBB19_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_ori:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bnei a3, 2, .LBB19_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ori a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB19_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %d, 2
+ %ori = or i32 %a, 11
+ %sel = select i1 %x, i32 %ori, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_mul(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_mul:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: .cfi_def_cfa_offset 16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: .cfi_offset ra, -4
+; RV32I-NEXT: .cfi_offset s0, -8
+; RV32I-NEXT: .cfi_offset s1, -12
+; RV32I-NEXT: mv s1, a3
+; RV32I-NEXT: mv s0, a2
+; RV32I-NEXT: call __mulsi3
+; RV32I-NEXT: li a1, 2
+; RV32I-NEXT: beq s1, a1, .LBB20_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: .LBB20_2: # %entry
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: .cfi_restore ra
+; RV32I-NEXT: .cfi_restore s0
+; RV32I-NEXT: .cfi_restore s1
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: .cfi_def_cfa_offset 0
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mul:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bnei a3, 2, .LBB20_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mul a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB20_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %d, 2
+ %muli = mul i32 %a, %b
+ %sel = select i1 %x, i32 %muli, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_li(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_li:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 2
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: bne a2, a3, .LBB21_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: lui a0, 16
+; RV32I-NEXT: addi a0, a0, 7
+; RV32I-NEXT: .LBB21_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_li:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: qc.bnei a2, 2, .LBB21_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.li a0, 65543
+; RV32I-SFB-WITH-IMM-NEXT: .LBB21_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %d, 2
+ %sel = select i1 %x, i32 65543, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_qc_e_li(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_qc_e_li:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 2
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: bne a2, a3, .LBB22_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: lui a0, 1025
+; RV32I-NEXT: addi a0, a0, 528
+; RV32I-NEXT: .LBB22_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_qc_e_li:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: qc.bnei a2, 2, .LBB22_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.li a0, 4198928
+; RV32I-SFB-WITH-IMM-NEXT: .LBB22_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %d, 2
+ %sel = select i1 %x, i32 4198928, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_lui(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_lui:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 2
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: bne a2, a3, .LBB23_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: lui a0, 16
+; RV32I-NEXT: .LBB23_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lui:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: qc.bnei a2, 2, .LBB23_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lui a0, 16
+; RV32I-SFB-WITH-IMM-NEXT: .LBB23_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %d, 2
+ %sel = select i1 %x, i32 65536, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_lb(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lb:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 2
+; RV32I-NEXT: bne a1, a3, .LBB24_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lb a2, 4(a0)
+; RV32I-NEXT: .LBB24_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lb:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bnei a1, 2, .LBB24_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lb a2, 4(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB24_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %a, 2
+ %addr = getelementptr i8, ptr %base, i32 4 ; compute base + 4
+ %val = load i8, ptr %addr ; load 8-bit value
+ %ext = sext i8 %val to i32 ; sign-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lbu(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lbu:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 2
+; RV32I-NEXT: bne a1, a3, .LBB25_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lbu a2, 4(a0)
+; RV32I-NEXT: .LBB25_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lbu:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bnei a1, 2, .LBB25_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lbu a2, 4(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB25_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %a, 2
+ %addr = getelementptr i8, ptr %base, i32 4 ; compute base + 4
+ %val = load i8, ptr %addr ; load 8-bit value
+ %ext = zext i8 %val to i32 ; zero-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lh(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lh:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 2
+; RV32I-NEXT: bne a1, a3, .LBB26_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lh a2, 8(a0)
+; RV32I-NEXT: .LBB26_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lh:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bnei a1, 2, .LBB26_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lh a2, 8(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB26_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %a, 2
+ %addr = getelementptr i16, ptr %base, i32 4 ; compute base + 4
+ %val = load i16, ptr %addr ; load 16-bit value
+ %ext = sext i16 %val to i32 ; sign-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lhu(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lhu:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 2
+; RV32I-NEXT: bne a1, a3, .LBB27_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lhu a2, 8(a0)
+; RV32I-NEXT: .LBB27_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lhu:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bnei a1, 2, .LBB27_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lhu a2, 8(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB27_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %a, 2
+ %addr = getelementptr i16, ptr %base, i32 4 ; compute base + 4
+ %val = load i16, ptr %addr ; load 16-bit value
+ %ext = zext i16 %val to i32 ; zero-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lw(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lw:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 2
+; RV32I-NEXT: bne a1, a3, .LBB28_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lw a2, 16(a0)
+; RV32I-NEXT: .LBB28_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lw:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bnei a1, 2, .LBB28_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lw a2, 16(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB28_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %a, 2
+ %addr = getelementptr i32, ptr %base, i32 4 ; compute base + 4
+ %val = load i32, ptr %addr ; load 32-bit value
+ %res = select i1 %x, i32 %val, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lb_qc_e(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lb_qc_e:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 2
+; RV32I-NEXT: bne a1, a3, .LBB29_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: add a0, a0, a1
+; RV32I-NEXT: lb a2, 1808(a0)
+; RV32I-NEXT: .LBB29_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lb_qc_e:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bnei a1, 2, .LBB29_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.lb a2, 10000(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB29_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %a, 2
+ %addr = getelementptr i8, ptr %base, i32 10000 ; compute base + 10000
+ %val = load i8, ptr %addr ; load 8-bit value
+ %ext = sext i8 %val to i32 ; sign-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lbu_qc_e(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lbu_qc_e:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 2
+; RV32I-NEXT: bne a1, a3, .LBB30_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: add a0, a0, a1
+; RV32I-NEXT: lbu a2, 1808(a0)
+; RV32I-NEXT: .LBB30_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lbu_qc_e:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bnei a1, 2, .LBB30_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.lbu a2, 10000(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB30_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %a, 2
+ %addr = getelementptr i8, ptr %base, i32 10000 ; compute base + 10000
+ %val = load i8, ptr %addr ; load 8-bit value
+ %ext = zext i8 %val to i32 ; zero-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lh_qc_e(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lh_qc_e:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 2
+; RV32I-NEXT: bne a1, a3, .LBB31_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lui a1, 5
+; RV32I-NEXT: add a0, a0, a1
+; RV32I-NEXT: lh a2, -480(a0)
+; RV32I-NEXT: .LBB31_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lh_qc_e:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bnei a1, 2, .LBB31_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.lh a2, 20000(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB31_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %a, 2
+ %addr = getelementptr i16, ptr %base, i32 10000 ; compute base + 10000
+ %val = load i16, ptr %addr ; load 16-bit value
+ %ext = sext i16 %val to i32 ; sign-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lhu_qc_e(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lhu_qc_e:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 2
+; RV32I-NEXT: bne a1, a3, .LBB32_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lui a1, 5
+; RV32I-NEXT: add a0, a0, a1
+; RV32I-NEXT: lhu a2, -480(a0)
+; RV32I-NEXT: .LBB32_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lhu_qc_e:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bnei a1, 2, .LBB32_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.lhu a2, 20000(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB32_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %a, 2
+ %addr = getelementptr i16, ptr %base, i32 10000 ; compute base + 10000
+ %val = load i16, ptr %addr ; load 16-bit value
+ %ext = zext i16 %val to i32 ; zero-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lw_qc_e(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lw_qc_e:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 2
+; RV32I-NEXT: bne a1, a3, .LBB33_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lui a1, 10
+; RV32I-NEXT: add a0, a0, a1
+; RV32I-NEXT: lw a2, -960(a0)
+; RV32I-NEXT: .LBB33_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lw_qc_e:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bnei a1, 2, .LBB33_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.lw a2, 40000(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB33_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %a, 2
+ %addr = getelementptr i32, ptr %base, i32 10000 ; compute base + 10000
+ %val = load i32, ptr %addr ; load 32-bit value
+ %res = select i1 %x, i32 %val, i32 %b
+ ret i32 %res
+}
diff --git a/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_32_ne.ll b/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_32_ne.ll
new file mode 100644
index 0000000000000..d8836606f3cec
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_32_ne.ll
@@ -0,0 +1,906 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 | FileCheck %s --check-prefixes=RV32I
+; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 -mattr=+xqci,+short-forward-branch-ialu,+short-forward-branch-imul,+short-forward-branch-iload,+short-forward-branch-imm,+m | \
+; RUN: FileCheck %s --check-prefixes=RV32I-SFB-WITH-IMM
+
+define i32 @branch_with_immSFB_mv(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_mv:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 2
+; RV32I-NEXT: bne a2, a3, .LBB0_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: .LBB0_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mv:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bnei a2, 2, .LBB0_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB0_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %d, 2
+ %sel = select i1 %x, i32 %a, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_mv_zerofalsev(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_mv_zerofalsev:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: addi a2, a2, -2
+; RV32I-NEXT: seqz a1, a2
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: and a0, a1, a0
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mv_zerofalsev:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.selectinei a2, 2, a0, 0
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %d, 2
+ %sel = select i1 %x, i32 %a, i32 0
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_mv_zerofalsev_swapped(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_mv_zerofalsev_swapped:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: addi a2, a2, -2
+; RV32I-NEXT: snez a1, a2
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: and a0, a1, a0
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mv_zerofalsev_swapped:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.selectieqi a2, 2, a0, 0
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %d, 2
+ %sel = select i1 %x, i32 0, i32 %a
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_mv_minusOnefalsev(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_mv_minusOnefalsev:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: addi a2, a2, -2
+; RV32I-NEXT: snez a1, a2
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: or a0, a1, a0
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mv_minusOnefalsev:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.selectinei a2, 2, a0, -1
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %d, 2
+ %sel = select i1 %x, i32 %a, i32 -1
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_mv_minusOnefalsev_swapped(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_mv_minusOnefalsev_swapped:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: addi a2, a2, -2
+; RV32I-NEXT: seqz a1, a2
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: or a0, a1, a0
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mv_minusOnefalsev_swapped:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.selectieqi a2, 2, a0, -1
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %d, 2
+ %sel = select i1 %x, i32 -1, i32 %a
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_add(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_add:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a4, 2
+; RV32I-NEXT: beq a3, a4, .LBB5_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: add a2, a0, a1
+; RV32I-NEXT: .LBB5_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_add:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.beqi a3, 2, .LBB5_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: add a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB5_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %d, 2
+ %addi = add i32 %a, %b
+ %sel = select i1 %x, i32 %addi, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_sub(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_sub:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a4, 2
+; RV32I-NEXT: beq a3, a4, .LBB6_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: sub a2, a0, a1
+; RV32I-NEXT: .LBB6_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_sub:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.beqi a3, 2, .LBB6_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: sub a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB6_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %d, 2
+ %subi = sub i32 %a, %b
+ %sel = select i1 %x, i32 %subi, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_shl(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_shl:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a4, 2
+; RV32I-NEXT: beq a3, a4, .LBB7_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: sll a2, a0, a1
+; RV32I-NEXT: .LBB7_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_shl:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.beqi a3, 2, .LBB7_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: sll a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB7_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %d, 2
+ %shli = shl i32 %a, %b
+ %sel = select i1 %x, i32 %shli, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_lshr(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_lshr:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a4, 2
+; RV32I-NEXT: beq a3, a4, .LBB8_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: srl a2, a0, a1
+; RV32I-NEXT: .LBB8_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lshr:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.beqi a3, 2, .LBB8_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: srl a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB8_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %d, 2
+ %lshri = lshr i32 %a, %b
+ %sel = select i1 %x, i32 %lshri, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_ashr(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_ashr:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a4, 2
+; RV32I-NEXT: beq a3, a4, .LBB9_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: sra a2, a0, a1
+; RV32I-NEXT: .LBB9_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_ashr:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.beqi a3, 2, .LBB9_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: sra a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB9_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %d, 2
+ %ashri = ashr i32 %a, %b
+ %sel = select i1 %x, i32 %ashri, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_xor(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_xor:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a4, 2
+; RV32I-NEXT: beq a3, a4, .LBB10_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: xor a2, a0, a1
+; RV32I-NEXT: .LBB10_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_xor:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.beqi a3, 2, .LBB10_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: xor a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB10_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %d, 2
+ %xori = xor i32 %a, %b
+ %sel = select i1 %x, i32 %xori, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_and(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_and:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a4, 2
+; RV32I-NEXT: beq a3, a4, .LBB11_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: and a2, a0, a1
+; RV32I-NEXT: .LBB11_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_and:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.beqi a3, 2, .LBB11_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: and a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB11_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %d, 2
+ %andi = and i32 %a, %b
+ %sel = select i1 %x, i32 %andi, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_or(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_or:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a4, 2
+; RV32I-NEXT: beq a3, a4, .LBB12_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: or a2, a0, a1
+; RV32I-NEXT: .LBB12_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_or:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.beqi a3, 2, .LBB12_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: or a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB12_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %d, 2
+ %ori = or i32 %a, %b
+ %sel = select i1 %x, i32 %ori, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_addi(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_addi:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 2
+; RV32I-NEXT: beq a3, a1, .LBB13_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: addi a2, a0, 11
+; RV32I-NEXT: .LBB13_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_addi:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.beqi a3, 2, .LBB13_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: addi a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB13_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %d, 2
+ %addi = add i32 %a, 11
+ %sel = select i1 %x, i32 %addi, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_xori(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_xori:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 2
+; RV32I-NEXT: beq a3, a1, .LBB14_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: xori a2, a0, 11
+; RV32I-NEXT: .LBB14_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_xori:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.beqi a3, 2, .LBB14_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: xori a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB14_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %d, 2
+ %xori = xor i32 %a, 11
+ %sel = select i1 %x, i32 %xori, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_shli(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_shli:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 2
+; RV32I-NEXT: beq a3, a1, .LBB15_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: slli a2, a0, 11
+; RV32I-NEXT: .LBB15_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_shli:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.beqi a3, 2, .LBB15_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: slli a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB15_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %d, 2
+ %shli = shl i32 %a, 11
+ %sel = select i1 %x, i32 %shli, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_lshri(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_lshri:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 2
+; RV32I-NEXT: beq a3, a1, .LBB16_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: srli a2, a0, 11
+; RV32I-NEXT: .LBB16_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lshri:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.beqi a3, 2, .LBB16_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: srli a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB16_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %d, 2
+ %lshri = lshr i32 %a, 11
+ %sel = select i1 %x, i32 %lshri, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_ashri(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_ashri:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 2
+; RV32I-NEXT: beq a3, a1, .LBB17_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: srai a2, a0, 11
+; RV32I-NEXT: .LBB17_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_ashri:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.beqi a3, 2, .LBB17_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: srai a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB17_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %d, 2
+ %ashri = ashr i32 %a, 11
+ %sel = select i1 %x, i32 %ashri, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_andi(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_andi:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 2
+; RV32I-NEXT: beq a3, a1, .LBB18_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: andi a2, a0, 11
+; RV32I-NEXT: .LBB18_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_andi:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.beqi a3, 2, .LBB18_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: andi a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB18_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %d, 2
+ %andi = and i32 %a, 11
+ %sel = select i1 %x, i32 %andi, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_ori(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_ori:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 2
+; RV32I-NEXT: beq a3, a1, .LBB19_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: ori a2, a0, 11
+; RV32I-NEXT: .LBB19_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_ori:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.beqi a3, 2, .LBB19_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ori a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB19_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %d, 2
+ %ori = or i32 %a, 11
+ %sel = select i1 %x, i32 %ori, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_mul(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_mul:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: .cfi_def_cfa_offset 16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: .cfi_offset ra, -4
+; RV32I-NEXT: .cfi_offset s0, -8
+; RV32I-NEXT: .cfi_offset s1, -12
+; RV32I-NEXT: mv s1, a3
+; RV32I-NEXT: mv s0, a2
+; RV32I-NEXT: call __mulsi3
+; RV32I-NEXT: li a1, 2
+; RV32I-NEXT: bne s1, a1, .LBB20_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: .LBB20_2: # %entry
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: .cfi_restore ra
+; RV32I-NEXT: .cfi_restore s0
+; RV32I-NEXT: .cfi_restore s1
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: .cfi_def_cfa_offset 0
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mul:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.beqi a3, 2, .LBB20_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mul a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB20_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %d, 2
+ %muli = mul i32 %a, %b
+ %sel = select i1 %x, i32 %muli, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_li(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_li:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 2
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: beq a2, a3, .LBB21_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: lui a0, 16
+; RV32I-NEXT: addi a0, a0, 7
+; RV32I-NEXT: .LBB21_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_li:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: qc.beqi a2, 2, .LBB21_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.li a0, 65543
+; RV32I-SFB-WITH-IMM-NEXT: .LBB21_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %d, 2
+ %sel = select i1 %x, i32 65543, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_qc_e_li(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_qc_e_li:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 2
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: beq a2, a3, .LBB22_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: lui a0, 1025
+; RV32I-NEXT: addi a0, a0, 528
+; RV32I-NEXT: .LBB22_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_qc_e_li:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: qc.beqi a2, 2, .LBB22_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.li a0, 4198928
+; RV32I-SFB-WITH-IMM-NEXT: .LBB22_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %d, 2
+ %sel = select i1 %x, i32 4198928, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_lui(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_lui:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 2
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: beq a2, a3, .LBB23_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: lui a0, 16
+; RV32I-NEXT: .LBB23_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lui:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: qc.beqi a2, 2, .LBB23_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lui a0, 16
+; RV32I-SFB-WITH-IMM-NEXT: .LBB23_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %d, 2
+ %sel = select i1 %x, i32 65536, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_lb(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lb:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 2
+; RV32I-NEXT: beq a1, a3, .LBB24_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lb a2, 4(a0)
+; RV32I-NEXT: .LBB24_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lb:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.beqi a1, 2, .LBB24_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lb a2, 4(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB24_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %a, 2
+ %addr = getelementptr i8, ptr %base, i32 4 ; compute base + 4
+ %val = load i8, ptr %addr ; load 8-bit value
+ %ext = sext i8 %val to i32 ; sign-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lbu(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lbu:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 2
+; RV32I-NEXT: beq a1, a3, .LBB25_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lbu a2, 4(a0)
+; RV32I-NEXT: .LBB25_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lbu:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.beqi a1, 2, .LBB25_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lbu a2, 4(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB25_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %a, 2
+ %addr = getelementptr i8, ptr %base, i32 4 ; compute base + 4
+ %val = load i8, ptr %addr ; load 8-bit value
+ %ext = zext i8 %val to i32 ; zero-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lh(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lh:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 2
+; RV32I-NEXT: beq a1, a3, .LBB26_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lh a2, 8(a0)
+; RV32I-NEXT: .LBB26_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lh:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.beqi a1, 2, .LBB26_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lh a2, 8(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB26_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %a, 2
+ %addr = getelementptr i16, ptr %base, i32 4 ; compute base + 4
+ %val = load i16, ptr %addr ; load 16-bit value
+ %ext = sext i16 %val to i32 ; sign-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lhu(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lhu:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 2
+; RV32I-NEXT: beq a1, a3, .LBB27_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lhu a2, 8(a0)
+; RV32I-NEXT: .LBB27_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lhu:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.beqi a1, 2, .LBB27_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lhu a2, 8(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB27_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %a, 2
+ %addr = getelementptr i16, ptr %base, i32 4 ; compute base + 4
+ %val = load i16, ptr %addr ; load 16-bit value
+ %ext = zext i16 %val to i32 ; zero-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lw(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lw:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 2
+; RV32I-NEXT: beq a1, a3, .LBB28_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lw a2, 16(a0)
+; RV32I-NEXT: .LBB28_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lw:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.beqi a1, 2, .LBB28_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lw a2, 16(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB28_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %a, 2
+ %addr = getelementptr i32, ptr %base, i32 4 ; compute base + 4
+ %val = load i32, ptr %addr ; load 32-bit value
+ %res = select i1 %x, i32 %val, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lb_qc_e(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lb_qc_e:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 2
+; RV32I-NEXT: beq a1, a3, .LBB29_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: add a0, a0, a1
+; RV32I-NEXT: lb a2, 1808(a0)
+; RV32I-NEXT: .LBB29_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lb_qc_e:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.beqi a1, 2, .LBB29_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.lb a2, 10000(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB29_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %a, 2
+ %addr = getelementptr i8, ptr %base, i32 10000 ; compute base + 10000
+ %val = load i8, ptr %addr ; load 8-bit value
+ %ext = sext i8 %val to i32 ; sign-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lbu_qc_e(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lbu_qc_e:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 2
+; RV32I-NEXT: beq a1, a3, .LBB30_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: add a0, a0, a1
+; RV32I-NEXT: lbu a2, 1808(a0)
+; RV32I-NEXT: .LBB30_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lbu_qc_e:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.beqi a1, 2, .LBB30_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.lbu a2, 10000(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB30_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %a, 2
+ %addr = getelementptr i8, ptr %base, i32 10000 ; compute base + 10000
+ %val = load i8, ptr %addr ; load 8-bit value
+ %ext = zext i8 %val to i32 ; zero-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lh_qc_e(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lh_qc_e:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 2
+; RV32I-NEXT: beq a1, a3, .LBB31_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lui a1, 5
+; RV32I-NEXT: add a0, a0, a1
+; RV32I-NEXT: lh a2, -480(a0)
+; RV32I-NEXT: .LBB31_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lh_qc_e:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.beqi a1, 2, .LBB31_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.lh a2, 20000(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB31_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %a, 2
+ %addr = getelementptr i16, ptr %base, i32 10000 ; compute base + 10000
+ %val = load i16, ptr %addr ; load 16-bit value
+ %ext = sext i16 %val to i32 ; sign-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lhu_qc_e(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lhu_qc_e:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 2
+; RV32I-NEXT: beq a1, a3, .LBB32_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lui a1, 5
+; RV32I-NEXT: add a0, a0, a1
+; RV32I-NEXT: lhu a2, -480(a0)
+; RV32I-NEXT: .LBB32_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lhu_qc_e:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.beqi a1, 2, .LBB32_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.lhu a2, 20000(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB32_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %a, 2
+ %addr = getelementptr i16, ptr %base, i32 10000 ; compute base + 10000
+ %val = load i16, ptr %addr ; load 16-bit value
+ %ext = zext i16 %val to i32 ; zero-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lw_qc_e(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lw_qc_e:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 2
+; RV32I-NEXT: beq a1, a3, .LBB33_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lui a1, 10
+; RV32I-NEXT: add a0, a0, a1
+; RV32I-NEXT: lw a2, -960(a0)
+; RV32I-NEXT: .LBB33_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lw_qc_e:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.beqi a1, 2, .LBB33_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.lw a2, 40000(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB33_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %a, 2
+ %addr = getelementptr i32, ptr %base, i32 10000 ; compute base + 10000
+ %val = load i32, ptr %addr ; load 32-bit value
+ %res = select i1 %x, i32 %val, i32 %b
+ ret i32 %res
+}
diff --git a/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_32_sge.ll b/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_32_sge.ll
new file mode 100644
index 0000000000000..8598c4aa2c5cb
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_32_sge.ll
@@ -0,0 +1,898 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 | FileCheck %s --check-prefixes=RV32I
+; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 -mattr=+xqci,+short-forward-branch-ialu,+short-forward-branch-imul,+short-forward-branch-iload,+short-forward-branch-imm,+m | \
+; RUN: FileCheck %s --check-prefixes=RV32I-SFB-WITH-IMM
+
+define i32 @branch_with_immSFB_mv(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_mv:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 1
+; RV32I-NEXT: blt a3, a2, .LBB0_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: .LBB0_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mv:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bgei a2, 2, .LBB0_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB0_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %d, 2
+ %sel = select i1 %x, i32 %a, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_mv_zerofalsev(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_mv_zerofalsev:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: slti a1, a2, 2
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: and a0, a1, a0
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mv_zerofalsev:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.lilti a0, a2, 2, 0
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %d, 2
+ %sel = select i1 %x, i32 %a, i32 0
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_mv_zerofalsev_swapped(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_mv_zerofalsev_swapped:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: slti a1, a2, 2
+; RV32I-NEXT: neg a1, a1
+; RV32I-NEXT: and a0, a1, a0
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mv_zerofalsev_swapped:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.ligei a0, a2, 2, 0
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %d, 2
+ %sel = select i1 %x, i32 0, i32 %a
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_mv_minusOnefalsev(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_mv_minusOnefalsev:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: slti a1, a2, 2
+; RV32I-NEXT: neg a1, a1
+; RV32I-NEXT: or a0, a1, a0
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mv_minusOnefalsev:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.lilti a0, a2, 2, -1
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %d, 2
+ %sel = select i1 %x, i32 %a, i32 -1
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_mv_minusOnefalsev_swapped(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_mv_minusOnefalsev_swapped:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: slti a1, a2, 2
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: or a0, a1, a0
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mv_minusOnefalsev_swapped:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.ligei a0, a2, 2, -1
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %d, 2
+ %sel = select i1 %x, i32 -1, i32 %a
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_add(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_add:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a4, 1
+; RV32I-NEXT: bge a4, a3, .LBB5_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: add a2, a0, a1
+; RV32I-NEXT: .LBB5_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_add:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.blti a3, 2, .LBB5_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: add a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB5_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %d, 2
+ %addi = add i32 %a, %b
+ %sel = select i1 %x, i32 %addi, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_sub(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_sub:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a4, 1
+; RV32I-NEXT: bge a4, a3, .LBB6_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: sub a2, a0, a1
+; RV32I-NEXT: .LBB6_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_sub:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.blti a3, 2, .LBB6_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: sub a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB6_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %d, 2
+ %subi = sub i32 %a, %b
+ %sel = select i1 %x, i32 %subi, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_shl(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_shl:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a4, 1
+; RV32I-NEXT: bge a4, a3, .LBB7_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: sll a2, a0, a1
+; RV32I-NEXT: .LBB7_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_shl:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.blti a3, 2, .LBB7_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: sll a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB7_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %d, 2
+ %shli = shl i32 %a, %b
+ %sel = select i1 %x, i32 %shli, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_lshr(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_lshr:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a4, 1
+; RV32I-NEXT: bge a4, a3, .LBB8_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: srl a2, a0, a1
+; RV32I-NEXT: .LBB8_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lshr:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.blti a3, 2, .LBB8_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: srl a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB8_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %d, 2
+ %lshri = lshr i32 %a, %b
+ %sel = select i1 %x, i32 %lshri, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_ashr(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_ashr:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a4, 1
+; RV32I-NEXT: bge a4, a3, .LBB9_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: sra a2, a0, a1
+; RV32I-NEXT: .LBB9_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_ashr:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.blti a3, 2, .LBB9_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: sra a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB9_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %d, 2
+ %ashri = ashr i32 %a, %b
+ %sel = select i1 %x, i32 %ashri, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_xor(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_xor:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a4, 1
+; RV32I-NEXT: bge a4, a3, .LBB10_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: xor a2, a0, a1
+; RV32I-NEXT: .LBB10_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_xor:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.blti a3, 2, .LBB10_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: xor a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB10_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %d, 2
+ %xori = xor i32 %a, %b
+ %sel = select i1 %x, i32 %xori, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_and(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_and:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a4, 1
+; RV32I-NEXT: bge a4, a3, .LBB11_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: and a2, a0, a1
+; RV32I-NEXT: .LBB11_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_and:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.blti a3, 2, .LBB11_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: and a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB11_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %d, 2
+ %andi = and i32 %a, %b
+ %sel = select i1 %x, i32 %andi, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_or(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_or:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a4, 1
+; RV32I-NEXT: bge a4, a3, .LBB12_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: or a2, a0, a1
+; RV32I-NEXT: .LBB12_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_or:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.blti a3, 2, .LBB12_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: or a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB12_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %d, 2
+ %ori = or i32 %a, %b
+ %sel = select i1 %x, i32 %ori, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_addi(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_addi:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 1
+; RV32I-NEXT: bge a1, a3, .LBB13_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: addi a2, a0, 11
+; RV32I-NEXT: .LBB13_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_addi:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.blti a3, 2, .LBB13_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: addi a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB13_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %d, 2
+ %addi = add i32 %a, 11
+ %sel = select i1 %x, i32 %addi, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_xori(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_xori:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 1
+; RV32I-NEXT: bge a1, a3, .LBB14_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: xori a2, a0, 11
+; RV32I-NEXT: .LBB14_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_xori:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.blti a3, 2, .LBB14_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: xori a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB14_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %d, 2
+ %xori = xor i32 %a, 11
+ %sel = select i1 %x, i32 %xori, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_shli(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_shli:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 1
+; RV32I-NEXT: bge a1, a3, .LBB15_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: slli a2, a0, 11
+; RV32I-NEXT: .LBB15_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_shli:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.blti a3, 2, .LBB15_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: slli a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB15_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %d, 2
+ %shli = shl i32 %a, 11
+ %sel = select i1 %x, i32 %shli, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_lshri(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_lshri:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 1
+; RV32I-NEXT: bge a1, a3, .LBB16_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: srli a2, a0, 11
+; RV32I-NEXT: .LBB16_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lshri:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.blti a3, 2, .LBB16_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: srli a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB16_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %d, 2
+ %lshri = lshr i32 %a, 11
+ %sel = select i1 %x, i32 %lshri, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_ashri(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_ashri:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 1
+; RV32I-NEXT: bge a1, a3, .LBB17_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: srai a2, a0, 11
+; RV32I-NEXT: .LBB17_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_ashri:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.blti a3, 2, .LBB17_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: srai a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB17_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %d, 2
+ %ashri = ashr i32 %a, 11
+ %sel = select i1 %x, i32 %ashri, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_andi(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_andi:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 1
+; RV32I-NEXT: bge a1, a3, .LBB18_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: andi a2, a0, 11
+; RV32I-NEXT: .LBB18_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_andi:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.blti a3, 2, .LBB18_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: andi a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB18_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %d, 2
+ %andi = and i32 %a, 11
+ %sel = select i1 %x, i32 %andi, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_ori(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_ori:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 1
+; RV32I-NEXT: bge a1, a3, .LBB19_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: ori a2, a0, 11
+; RV32I-NEXT: .LBB19_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_ori:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.blti a3, 2, .LBB19_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ori a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB19_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %d, 2
+ %ori = or i32 %a, 11
+ %sel = select i1 %x, i32 %ori, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_mul(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_mul:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: .cfi_def_cfa_offset 16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: .cfi_offset ra, -4
+; RV32I-NEXT: .cfi_offset s0, -8
+; RV32I-NEXT: .cfi_offset s1, -12
+; RV32I-NEXT: mv s1, a3
+; RV32I-NEXT: mv s0, a2
+; RV32I-NEXT: call __mulsi3
+; RV32I-NEXT: li a1, 1
+; RV32I-NEXT: blt a1, s1, .LBB20_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: .LBB20_2: # %entry
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: .cfi_restore ra
+; RV32I-NEXT: .cfi_restore s0
+; RV32I-NEXT: .cfi_restore s1
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: .cfi_def_cfa_offset 0
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mul:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.blti a3, 2, .LBB20_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mul a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB20_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %d, 2
+ %muli = mul i32 %a, %b
+ %sel = select i1 %x, i32 %muli, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_li(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_li:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 1
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: bge a3, a2, .LBB21_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: lui a0, 16
+; RV32I-NEXT: addi a0, a0, 7
+; RV32I-NEXT: .LBB21_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_li:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: qc.blti a2, 2, .LBB21_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.li a0, 65543
+; RV32I-SFB-WITH-IMM-NEXT: .LBB21_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %d, 2
+ %sel = select i1 %x, i32 65543, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_qc_e_li(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_qc_e_li:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 1
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: bge a3, a2, .LBB22_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: lui a0, 1025
+; RV32I-NEXT: addi a0, a0, 528
+; RV32I-NEXT: .LBB22_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_qc_e_li:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: qc.blti a2, 2, .LBB22_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.li a0, 4198928
+; RV32I-SFB-WITH-IMM-NEXT: .LBB22_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %d, 2
+ %sel = select i1 %x, i32 4198928, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_lui(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_lui:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 1
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: bge a3, a2, .LBB23_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: lui a0, 16
+; RV32I-NEXT: .LBB23_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lui:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: qc.blti a2, 2, .LBB23_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lui a0, 16
+; RV32I-SFB-WITH-IMM-NEXT: .LBB23_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %d, 2
+ %sel = select i1 %x, i32 65536, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_lb(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lb:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 1
+; RV32I-NEXT: bge a3, a1, .LBB24_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lb a2, 4(a0)
+; RV32I-NEXT: .LBB24_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lb:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.blti a1, 2, .LBB24_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lb a2, 4(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB24_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %a, 2
+ %addr = getelementptr i8, ptr %base, i32 4 ; compute base + 4
+ %val = load i8, ptr %addr ; load 8-bit value
+ %ext = sext i8 %val to i32 ; sign-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lbu(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lbu:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 1
+; RV32I-NEXT: bge a3, a1, .LBB25_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lbu a2, 4(a0)
+; RV32I-NEXT: .LBB25_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lbu:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.blti a1, 2, .LBB25_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lbu a2, 4(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB25_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %a, 2
+ %addr = getelementptr i8, ptr %base, i32 4 ; compute base + 4
+ %val = load i8, ptr %addr ; load 8-bit value
+ %ext = zext i8 %val to i32 ; zero-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lh(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lh:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 1
+; RV32I-NEXT: bge a3, a1, .LBB26_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lh a2, 8(a0)
+; RV32I-NEXT: .LBB26_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lh:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.blti a1, 2, .LBB26_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lh a2, 8(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB26_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %a, 2
+ %addr = getelementptr i16, ptr %base, i32 4 ; compute base + 4
+ %val = load i16, ptr %addr ; load 16-bit value
+ %ext = sext i16 %val to i32 ; sign-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lhu(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lhu:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 1
+; RV32I-NEXT: bge a3, a1, .LBB27_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lhu a2, 8(a0)
+; RV32I-NEXT: .LBB27_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lhu:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.blti a1, 2, .LBB27_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lhu a2, 8(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB27_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %a, 2
+ %addr = getelementptr i16, ptr %base, i32 4 ; compute base + 4
+ %val = load i16, ptr %addr ; load 16-bit value
+ %ext = zext i16 %val to i32 ; zero-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lw(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lw:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 1
+; RV32I-NEXT: bge a3, a1, .LBB28_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lw a2, 16(a0)
+; RV32I-NEXT: .LBB28_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lw:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.blti a1, 2, .LBB28_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lw a2, 16(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB28_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %a, 2
+ %addr = getelementptr i32, ptr %base, i32 4 ; compute base + 4
+ %val = load i32, ptr %addr ; load 32-bit value
+ %res = select i1 %x, i32 %val, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lb_qc_e(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lb_qc_e:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 1
+; RV32I-NEXT: bge a3, a1, .LBB29_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: add a0, a0, a1
+; RV32I-NEXT: lb a2, 1808(a0)
+; RV32I-NEXT: .LBB29_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lb_qc_e:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.blti a1, 2, .LBB29_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.lb a2, 10000(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB29_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %a, 2
+ %addr = getelementptr i8, ptr %base, i32 10000 ; compute base + 10000
+ %val = load i8, ptr %addr ; load 8-bit value
+ %ext = sext i8 %val to i32 ; sign-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lbu_qc_e(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lbu_qc_e:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 1
+; RV32I-NEXT: bge a3, a1, .LBB30_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: add a0, a0, a1
+; RV32I-NEXT: lbu a2, 1808(a0)
+; RV32I-NEXT: .LBB30_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lbu_qc_e:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.blti a1, 2, .LBB30_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.lbu a2, 10000(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB30_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %a, 2
+ %addr = getelementptr i8, ptr %base, i32 10000 ; compute base + 10000
+ %val = load i8, ptr %addr ; load 8-bit value
+ %ext = zext i8 %val to i32 ; zero-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lh_qc_e(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lh_qc_e:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 1
+; RV32I-NEXT: bge a3, a1, .LBB31_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lui a1, 5
+; RV32I-NEXT: add a0, a0, a1
+; RV32I-NEXT: lh a2, -480(a0)
+; RV32I-NEXT: .LBB31_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lh_qc_e:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.blti a1, 2, .LBB31_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.lh a2, 20000(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB31_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %a, 2
+ %addr = getelementptr i16, ptr %base, i32 10000 ; compute base + 10000
+ %val = load i16, ptr %addr ; load 16-bit value
+ %ext = sext i16 %val to i32 ; sign-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lhu_qc_e(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lhu_qc_e:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 1
+; RV32I-NEXT: bge a3, a1, .LBB32_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lui a1, 5
+; RV32I-NEXT: add a0, a0, a1
+; RV32I-NEXT: lhu a2, -480(a0)
+; RV32I-NEXT: .LBB32_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lhu_qc_e:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.blti a1, 2, .LBB32_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.lhu a2, 20000(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB32_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %a, 2
+ %addr = getelementptr i16, ptr %base, i32 10000 ; compute base + 10000
+ %val = load i16, ptr %addr ; load 16-bit value
+ %ext = zext i16 %val to i32 ; zero-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lw_qc_e(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lw_qc_e:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 1
+; RV32I-NEXT: bge a3, a1, .LBB33_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lui a1, 10
+; RV32I-NEXT: add a0, a0, a1
+; RV32I-NEXT: lw a2, -960(a0)
+; RV32I-NEXT: .LBB33_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lw_qc_e:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.blti a1, 2, .LBB33_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.lw a2, 40000(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB33_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %a, 2
+ %addr = getelementptr i32, ptr %base, i32 10000 ; compute base + 10000
+ %val = load i32, ptr %addr ; load 32-bit value
+ %res = select i1 %x, i32 %val, i32 %b
+ ret i32 %res
+}
diff --git a/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_32_slt.ll b/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_32_slt.ll
new file mode 100644
index 0000000000000..2e2d017f5bd61
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_32_slt.ll
@@ -0,0 +1,898 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 | FileCheck %s --check-prefixes=RV32I
+; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 -mattr=+xqci,+short-forward-branch-ialu,+short-forward-branch-imul,+short-forward-branch-iload,+short-forward-branch-imm,+m | \
+; RUN: FileCheck %s --check-prefixes=RV32I-SFB-WITH-IMM
+
+define i32 @branch_with_immSFB_mv(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_mv:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 2
+; RV32I-NEXT: blt a2, a3, .LBB0_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: .LBB0_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mv:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.blti a2, 2, .LBB0_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB0_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %d, 2
+ %sel = select i1 %x, i32 %a, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_mv_zerofalsev(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_mv_zerofalsev:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: slti a1, a2, 2
+; RV32I-NEXT: neg a1, a1
+; RV32I-NEXT: and a0, a1, a0
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mv_zerofalsev:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.ligei a0, a2, 2, 0
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %d, 2
+ %sel = select i1 %x, i32 %a, i32 0
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_mv_zerofalsev_swapped(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_mv_zerofalsev_swapped:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: slti a1, a2, 2
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: and a0, a1, a0
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mv_zerofalsev_swapped:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.lilti a0, a2, 2, 0
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %d, 2
+ %sel = select i1 %x, i32 0, i32 %a
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_mv_minusOnefalsev(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_mv_minusOnefalsev:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: slti a1, a2, 2
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: or a0, a1, a0
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mv_minusOnefalsev:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.ligei a0, a2, 2, -1
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %d, 2
+ %sel = select i1 %x, i32 %a, i32 -1
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_mv_minusOnefalsev_swapped(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_mv_minusOnefalsev_swapped:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: slti a1, a2, 2
+; RV32I-NEXT: neg a1, a1
+; RV32I-NEXT: or a0, a1, a0
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mv_minusOnefalsev_swapped:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.lilti a0, a2, 2, -1
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %d, 2
+ %sel = select i1 %x, i32 -1, i32 %a
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_add(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_add:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a4, 2
+; RV32I-NEXT: bge a3, a4, .LBB5_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: add a2, a0, a1
+; RV32I-NEXT: .LBB5_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_add:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bgei a3, 2, .LBB5_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: add a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB5_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %d, 2
+ %addi = add i32 %a, %b
+ %sel = select i1 %x, i32 %addi, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_sub(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_sub:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a4, 2
+; RV32I-NEXT: bge a3, a4, .LBB6_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: sub a2, a0, a1
+; RV32I-NEXT: .LBB6_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_sub:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bgei a3, 2, .LBB6_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: sub a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB6_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %d, 2
+ %subi = sub i32 %a, %b
+ %sel = select i1 %x, i32 %subi, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_shl(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_shl:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a4, 2
+; RV32I-NEXT: bge a3, a4, .LBB7_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: sll a2, a0, a1
+; RV32I-NEXT: .LBB7_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_shl:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bgei a3, 2, .LBB7_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: sll a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB7_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %d, 2
+ %shli = shl i32 %a, %b
+ %sel = select i1 %x, i32 %shli, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_lshr(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_lshr:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a4, 2
+; RV32I-NEXT: bge a3, a4, .LBB8_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: srl a2, a0, a1
+; RV32I-NEXT: .LBB8_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lshr:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bgei a3, 2, .LBB8_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: srl a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB8_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %d, 2
+ %lshri = lshr i32 %a, %b
+ %sel = select i1 %x, i32 %lshri, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_ashr(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_ashr:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a4, 2
+; RV32I-NEXT: bge a3, a4, .LBB9_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: sra a2, a0, a1
+; RV32I-NEXT: .LBB9_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_ashr:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bgei a3, 2, .LBB9_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: sra a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB9_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %d, 2
+ %ashri = ashr i32 %a, %b
+ %sel = select i1 %x, i32 %ashri, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_xor(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_xor:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a4, 2
+; RV32I-NEXT: bge a3, a4, .LBB10_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: xor a2, a0, a1
+; RV32I-NEXT: .LBB10_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_xor:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bgei a3, 2, .LBB10_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: xor a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB10_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %d, 2
+ %xori = xor i32 %a, %b
+ %sel = select i1 %x, i32 %xori, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_and(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_and:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a4, 2
+; RV32I-NEXT: bge a3, a4, .LBB11_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: and a2, a0, a1
+; RV32I-NEXT: .LBB11_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_and:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bgei a3, 2, .LBB11_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: and a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB11_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %d, 2
+ %andi = and i32 %a, %b
+ %sel = select i1 %x, i32 %andi, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_or(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_or:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a4, 2
+; RV32I-NEXT: bge a3, a4, .LBB12_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: or a2, a0, a1
+; RV32I-NEXT: .LBB12_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_or:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bgei a3, 2, .LBB12_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: or a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB12_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %d, 2
+ %ori = or i32 %a, %b
+ %sel = select i1 %x, i32 %ori, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_addi(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_addi:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 2
+; RV32I-NEXT: bge a3, a1, .LBB13_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: addi a2, a0, 11
+; RV32I-NEXT: .LBB13_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_addi:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bgei a3, 2, .LBB13_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: addi a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB13_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %d, 2
+ %addi = add i32 %a, 11
+ %sel = select i1 %x, i32 %addi, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_xori(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_xori:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 2
+; RV32I-NEXT: bge a3, a1, .LBB14_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: xori a2, a0, 11
+; RV32I-NEXT: .LBB14_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_xori:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bgei a3, 2, .LBB14_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: xori a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB14_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %d, 2
+ %xori = xor i32 %a, 11
+ %sel = select i1 %x, i32 %xori, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_shli(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_shli:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 2
+; RV32I-NEXT: bge a3, a1, .LBB15_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: slli a2, a0, 11
+; RV32I-NEXT: .LBB15_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_shli:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bgei a3, 2, .LBB15_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: slli a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB15_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %d, 2
+ %shli = shl i32 %a, 11
+ %sel = select i1 %x, i32 %shli, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_lshri(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_lshri:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 2
+; RV32I-NEXT: bge a3, a1, .LBB16_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: srli a2, a0, 11
+; RV32I-NEXT: .LBB16_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lshri:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bgei a3, 2, .LBB16_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: srli a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB16_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %d, 2
+ %lshri = lshr i32 %a, 11
+ %sel = select i1 %x, i32 %lshri, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_ashri(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_ashri:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 2
+; RV32I-NEXT: bge a3, a1, .LBB17_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: srai a2, a0, 11
+; RV32I-NEXT: .LBB17_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_ashri:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bgei a3, 2, .LBB17_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: srai a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB17_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %d, 2
+ %ashri = ashr i32 %a, 11
+ %sel = select i1 %x, i32 %ashri, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_andi(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_andi:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 2
+; RV32I-NEXT: bge a3, a1, .LBB18_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: andi a2, a0, 11
+; RV32I-NEXT: .LBB18_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_andi:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bgei a3, 2, .LBB18_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: andi a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB18_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %d, 2
+ %andi = and i32 %a, 11
+ %sel = select i1 %x, i32 %andi, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_ori(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_ori:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 2
+; RV32I-NEXT: bge a3, a1, .LBB19_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: ori a2, a0, 11
+; RV32I-NEXT: .LBB19_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_ori:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bgei a3, 2, .LBB19_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ori a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB19_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %d, 2
+ %ori = or i32 %a, 11
+ %sel = select i1 %x, i32 %ori, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_mul(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_mul:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: .cfi_def_cfa_offset 16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: .cfi_offset ra, -4
+; RV32I-NEXT: .cfi_offset s0, -8
+; RV32I-NEXT: .cfi_offset s1, -12
+; RV32I-NEXT: mv s1, a3
+; RV32I-NEXT: mv s0, a2
+; RV32I-NEXT: call __mulsi3
+; RV32I-NEXT: li a1, 2
+; RV32I-NEXT: blt s1, a1, .LBB20_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: .LBB20_2: # %entry
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: .cfi_restore ra
+; RV32I-NEXT: .cfi_restore s0
+; RV32I-NEXT: .cfi_restore s1
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: .cfi_def_cfa_offset 0
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mul:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bgei a3, 2, .LBB20_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mul a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB20_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %d, 2
+ %muli = mul i32 %a, %b
+ %sel = select i1 %x, i32 %muli, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_li(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_li:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 2
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: bge a2, a3, .LBB21_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: lui a0, 16
+; RV32I-NEXT: addi a0, a0, 7
+; RV32I-NEXT: .LBB21_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_li:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: qc.bgei a2, 2, .LBB21_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.li a0, 65543
+; RV32I-SFB-WITH-IMM-NEXT: .LBB21_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %d, 2
+ %sel = select i1 %x, i32 65543, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_qc_e_li(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_qc_e_li:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 2
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: bge a2, a3, .LBB22_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: lui a0, 1025
+; RV32I-NEXT: addi a0, a0, 528
+; RV32I-NEXT: .LBB22_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_qc_e_li:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: qc.bgei a2, 2, .LBB22_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.li a0, 4198928
+; RV32I-SFB-WITH-IMM-NEXT: .LBB22_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %d, 2
+ %sel = select i1 %x, i32 4198928, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_lui(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_lui:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 2
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: bge a2, a3, .LBB23_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: lui a0, 16
+; RV32I-NEXT: .LBB23_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lui:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: qc.bgei a2, 2, .LBB23_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lui a0, 16
+; RV32I-SFB-WITH-IMM-NEXT: .LBB23_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %d, 2
+ %sel = select i1 %x, i32 65536, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_lb(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lb:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 2
+; RV32I-NEXT: bge a1, a3, .LBB24_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lb a2, 4(a0)
+; RV32I-NEXT: .LBB24_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lb:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bgei a1, 2, .LBB24_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lb a2, 4(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB24_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %a, 2
+ %addr = getelementptr i8, ptr %base, i32 4 ; compute base + 4
+ %val = load i8, ptr %addr ; load 8-bit value
+ %ext = sext i8 %val to i32 ; sign-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lbu(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lbu:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 2
+; RV32I-NEXT: bge a1, a3, .LBB25_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lbu a2, 4(a0)
+; RV32I-NEXT: .LBB25_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lbu:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bgei a1, 2, .LBB25_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lbu a2, 4(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB25_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %a, 2
+ %addr = getelementptr i8, ptr %base, i32 4 ; compute base + 4
+ %val = load i8, ptr %addr ; load 8-bit value
+ %ext = zext i8 %val to i32 ; zero-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lh(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lh:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 2
+; RV32I-NEXT: bge a1, a3, .LBB26_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lh a2, 8(a0)
+; RV32I-NEXT: .LBB26_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lh:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bgei a1, 2, .LBB26_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lh a2, 8(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB26_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %a, 2
+ %addr = getelementptr i16, ptr %base, i32 4 ; compute base + 4
+ %val = load i16, ptr %addr ; load 16-bit value
+ %ext = sext i16 %val to i32 ; sign-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lhu(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lhu:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 2
+; RV32I-NEXT: bge a1, a3, .LBB27_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lhu a2, 8(a0)
+; RV32I-NEXT: .LBB27_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lhu:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bgei a1, 2, .LBB27_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lhu a2, 8(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB27_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %a, 2
+ %addr = getelementptr i16, ptr %base, i32 4 ; compute base + 4
+ %val = load i16, ptr %addr ; load 16-bit value
+ %ext = zext i16 %val to i32 ; zero-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lw(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lw:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 2
+; RV32I-NEXT: bge a1, a3, .LBB28_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lw a2, 16(a0)
+; RV32I-NEXT: .LBB28_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lw:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bgei a1, 2, .LBB28_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lw a2, 16(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB28_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %a, 2
+ %addr = getelementptr i32, ptr %base, i32 4 ; compute base + 4
+ %val = load i32, ptr %addr ; load 32-bit value
+ %res = select i1 %x, i32 %val, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lb_qc_e(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lb_qc_e:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 2
+; RV32I-NEXT: bge a1, a3, .LBB29_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: add a0, a0, a1
+; RV32I-NEXT: lb a2, 1808(a0)
+; RV32I-NEXT: .LBB29_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lb_qc_e:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bgei a1, 2, .LBB29_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.lb a2, 10000(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB29_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %a, 2
+ %addr = getelementptr i8, ptr %base, i32 10000 ; compute base + 10000
+ %val = load i8, ptr %addr ; load 8-bit value
+ %ext = sext i8 %val to i32 ; sign-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lbu_qc_e(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lbu_qc_e:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 2
+; RV32I-NEXT: bge a1, a3, .LBB30_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: add a0, a0, a1
+; RV32I-NEXT: lbu a2, 1808(a0)
+; RV32I-NEXT: .LBB30_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lbu_qc_e:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bgei a1, 2, .LBB30_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.lbu a2, 10000(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB30_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %a, 2
+ %addr = getelementptr i8, ptr %base, i32 10000 ; compute base + 10000
+ %val = load i8, ptr %addr ; load 8-bit value
+ %ext = zext i8 %val to i32 ; zero-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lh_qc_e(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lh_qc_e:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 2
+; RV32I-NEXT: bge a1, a3, .LBB31_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lui a1, 5
+; RV32I-NEXT: add a0, a0, a1
+; RV32I-NEXT: lh a2, -480(a0)
+; RV32I-NEXT: .LBB31_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lh_qc_e:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bgei a1, 2, .LBB31_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.lh a2, 20000(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB31_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %a, 2
+ %addr = getelementptr i16, ptr %base, i32 10000 ; compute base + 10000
+ %val = load i16, ptr %addr ; load 16-bit value
+ %ext = sext i16 %val to i32 ; sign-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lhu_qc_e(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lhu_qc_e:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 2
+; RV32I-NEXT: bge a1, a3, .LBB32_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lui a1, 5
+; RV32I-NEXT: add a0, a0, a1
+; RV32I-NEXT: lhu a2, -480(a0)
+; RV32I-NEXT: .LBB32_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lhu_qc_e:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bgei a1, 2, .LBB32_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.lhu a2, 20000(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB32_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %a, 2
+ %addr = getelementptr i16, ptr %base, i32 10000 ; compute base + 10000
+ %val = load i16, ptr %addr ; load 16-bit value
+ %ext = zext i16 %val to i32 ; zero-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lw_qc_e(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lw_qc_e:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 2
+; RV32I-NEXT: bge a1, a3, .LBB33_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lui a1, 10
+; RV32I-NEXT: add a0, a0, a1
+; RV32I-NEXT: lw a2, -960(a0)
+; RV32I-NEXT: .LBB33_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lw_qc_e:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bgei a1, 2, .LBB33_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.lw a2, 40000(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB33_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %a, 2
+ %addr = getelementptr i32, ptr %base, i32 10000 ; compute base + 10000
+ %val = load i32, ptr %addr ; load 32-bit value
+ %res = select i1 %x, i32 %val, i32 %b
+ ret i32 %res
+}
diff --git a/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_32_uge.ll b/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_32_uge.ll
new file mode 100644
index 0000000000000..fa1e5ad46257d
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_32_uge.ll
@@ -0,0 +1,898 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 | FileCheck %s --check-prefixes=RV32I
+; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 -mattr=+xqci,+short-forward-branch-ialu,+short-forward-branch-imul,+short-forward-branch-iload,+short-forward-branch-imm,+m | \
+; RUN: FileCheck %s --check-prefixes=RV32I-SFB-WITH-IMM
+
+define i32 @branch_with_immSFB_mv(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_mv:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 1
+; RV32I-NEXT: bltu a3, a2, .LBB0_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: .LBB0_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mv:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bgeui a2, 2, .LBB0_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB0_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %d, 2
+ %sel = select i1 %x, i32 %a, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_mv_zerofalsev(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_mv_zerofalsev:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: sltiu a1, a2, 2
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: and a0, a1, a0
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mv_zerofalsev:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.liltui a0, a2, 2, 0
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %d, 2
+ %sel = select i1 %x, i32 %a, i32 0
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_mv_zerofalsev_swapped(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_mv_zerofalsev_swapped:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: sltiu a1, a2, 2
+; RV32I-NEXT: neg a1, a1
+; RV32I-NEXT: and a0, a1, a0
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mv_zerofalsev_swapped:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.ligeui a0, a2, 2, 0
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %d, 2
+ %sel = select i1 %x, i32 0, i32 %a
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_mv_minusOnefalsev(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_mv_minusOnefalsev:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: sltiu a1, a2, 2
+; RV32I-NEXT: neg a1, a1
+; RV32I-NEXT: or a0, a1, a0
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mv_minusOnefalsev:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.liltui a0, a2, 2, -1
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %d, 2
+ %sel = select i1 %x, i32 %a, i32 -1
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_mv_minusOnefalsev_swapped(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_mv_minusOnefalsev_swapped:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: sltiu a1, a2, 2
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: or a0, a1, a0
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mv_minusOnefalsev_swapped:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.ligeui a0, a2, 2, -1
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %d, 2
+ %sel = select i1 %x, i32 -1, i32 %a
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_add(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_add:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a4, 1
+; RV32I-NEXT: bgeu a4, a3, .LBB5_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: add a2, a0, a1
+; RV32I-NEXT: .LBB5_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_add:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bltui a3, 2, .LBB5_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: add a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB5_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %d, 2
+ %addi = add i32 %a, %b
+ %sel = select i1 %x, i32 %addi, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_sub(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_sub:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a4, 1
+; RV32I-NEXT: bgeu a4, a3, .LBB6_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: sub a2, a0, a1
+; RV32I-NEXT: .LBB6_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_sub:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bltui a3, 2, .LBB6_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: sub a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB6_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %d, 2
+ %subi = sub i32 %a, %b
+ %sel = select i1 %x, i32 %subi, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_shl(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_shl:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a4, 1
+; RV32I-NEXT: bgeu a4, a3, .LBB7_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: sll a2, a0, a1
+; RV32I-NEXT: .LBB7_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_shl:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bltui a3, 2, .LBB7_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: sll a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB7_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %d, 2
+ %shli = shl i32 %a, %b
+ %sel = select i1 %x, i32 %shli, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_lshr(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_lshr:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a4, 1
+; RV32I-NEXT: bgeu a4, a3, .LBB8_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: srl a2, a0, a1
+; RV32I-NEXT: .LBB8_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lshr:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bltui a3, 2, .LBB8_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: srl a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB8_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %d, 2
+ %lshri = lshr i32 %a, %b
+ %sel = select i1 %x, i32 %lshri, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_ashr(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_ashr:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a4, 1
+; RV32I-NEXT: bgeu a4, a3, .LBB9_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: sra a2, a0, a1
+; RV32I-NEXT: .LBB9_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_ashr:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bltui a3, 2, .LBB9_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: sra a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB9_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %d, 2
+ %ashri = ashr i32 %a, %b
+ %sel = select i1 %x, i32 %ashri, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_xor(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_xor:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a4, 1
+; RV32I-NEXT: bgeu a4, a3, .LBB10_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: xor a2, a0, a1
+; RV32I-NEXT: .LBB10_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_xor:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bltui a3, 2, .LBB10_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: xor a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB10_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %d, 2
+ %xori = xor i32 %a, %b
+ %sel = select i1 %x, i32 %xori, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_and(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_and:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a4, 1
+; RV32I-NEXT: bgeu a4, a3, .LBB11_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: and a2, a0, a1
+; RV32I-NEXT: .LBB11_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_and:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bltui a3, 2, .LBB11_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: and a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB11_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %d, 2
+ %andi = and i32 %a, %b
+ %sel = select i1 %x, i32 %andi, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_or(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_or:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a4, 1
+; RV32I-NEXT: bgeu a4, a3, .LBB12_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: or a2, a0, a1
+; RV32I-NEXT: .LBB12_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_or:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bltui a3, 2, .LBB12_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: or a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB12_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %d, 2
+ %ori = or i32 %a, %b
+ %sel = select i1 %x, i32 %ori, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_addi(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_addi:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 1
+; RV32I-NEXT: bgeu a1, a3, .LBB13_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: addi a2, a0, 11
+; RV32I-NEXT: .LBB13_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_addi:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bltui a3, 2, .LBB13_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: addi a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB13_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %d, 2
+ %addi = add i32 %a, 11
+ %sel = select i1 %x, i32 %addi, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_xori(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_xori:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 1
+; RV32I-NEXT: bgeu a1, a3, .LBB14_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: xori a2, a0, 11
+; RV32I-NEXT: .LBB14_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_xori:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bltui a3, 2, .LBB14_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: xori a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB14_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %d, 2
+ %xori = xor i32 %a, 11
+ %sel = select i1 %x, i32 %xori, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_shli(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_shli:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 1
+; RV32I-NEXT: bgeu a1, a3, .LBB15_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: slli a2, a0, 11
+; RV32I-NEXT: .LBB15_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_shli:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bltui a3, 2, .LBB15_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: slli a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB15_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %d, 2
+ %shli = shl i32 %a, 11
+ %sel = select i1 %x, i32 %shli, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_lshri(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_lshri:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 1
+; RV32I-NEXT: bgeu a1, a3, .LBB16_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: srli a2, a0, 11
+; RV32I-NEXT: .LBB16_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lshri:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bltui a3, 2, .LBB16_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: srli a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB16_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %d, 2
+ %lshri = lshr i32 %a, 11
+ %sel = select i1 %x, i32 %lshri, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_ashri(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_ashri:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 1
+; RV32I-NEXT: bgeu a1, a3, .LBB17_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: srai a2, a0, 11
+; RV32I-NEXT: .LBB17_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_ashri:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bltui a3, 2, .LBB17_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: srai a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB17_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %d, 2
+ %ashri = ashr i32 %a, 11
+ %sel = select i1 %x, i32 %ashri, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_andi(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_andi:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 1
+; RV32I-NEXT: bgeu a1, a3, .LBB18_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: andi a2, a0, 11
+; RV32I-NEXT: .LBB18_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_andi:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bltui a3, 2, .LBB18_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: andi a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB18_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %d, 2
+ %andi = and i32 %a, 11
+ %sel = select i1 %x, i32 %andi, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_ori(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_ori:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 1
+; RV32I-NEXT: bgeu a1, a3, .LBB19_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: ori a2, a0, 11
+; RV32I-NEXT: .LBB19_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_ori:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bltui a3, 2, .LBB19_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ori a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB19_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %d, 2
+ %ori = or i32 %a, 11
+ %sel = select i1 %x, i32 %ori, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_mul(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_mul:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: .cfi_def_cfa_offset 16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: .cfi_offset ra, -4
+; RV32I-NEXT: .cfi_offset s0, -8
+; RV32I-NEXT: .cfi_offset s1, -12
+; RV32I-NEXT: mv s1, a3
+; RV32I-NEXT: mv s0, a2
+; RV32I-NEXT: call __mulsi3
+; RV32I-NEXT: li a1, 1
+; RV32I-NEXT: bltu a1, s1, .LBB20_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: .LBB20_2: # %entry
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: .cfi_restore ra
+; RV32I-NEXT: .cfi_restore s0
+; RV32I-NEXT: .cfi_restore s1
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: .cfi_def_cfa_offset 0
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mul:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bltui a3, 2, .LBB20_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mul a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB20_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %d, 2
+ %muli = mul i32 %a, %b
+ %sel = select i1 %x, i32 %muli, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_li(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_li:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 1
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: bgeu a3, a2, .LBB21_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: lui a0, 16
+; RV32I-NEXT: addi a0, a0, 7
+; RV32I-NEXT: .LBB21_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_li:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: qc.bltui a2, 2, .LBB21_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.li a0, 65543
+; RV32I-SFB-WITH-IMM-NEXT: .LBB21_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %d, 2
+ %sel = select i1 %x, i32 65543, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_qc_e_li(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_qc_e_li:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 1
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: bgeu a3, a2, .LBB22_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: lui a0, 1025
+; RV32I-NEXT: addi a0, a0, 528
+; RV32I-NEXT: .LBB22_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_qc_e_li:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: qc.bltui a2, 2, .LBB22_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.li a0, 4198928
+; RV32I-SFB-WITH-IMM-NEXT: .LBB22_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %d, 2
+ %sel = select i1 %x, i32 4198928, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_lui(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_lui:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 1
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: bgeu a3, a2, .LBB23_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: lui a0, 16
+; RV32I-NEXT: .LBB23_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lui:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: qc.bltui a2, 2, .LBB23_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lui a0, 16
+; RV32I-SFB-WITH-IMM-NEXT: .LBB23_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %d, 2
+ %sel = select i1 %x, i32 65536, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_lb(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lb:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 1
+; RV32I-NEXT: bgeu a3, a1, .LBB24_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lb a2, 4(a0)
+; RV32I-NEXT: .LBB24_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lb:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bltui a1, 2, .LBB24_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lb a2, 4(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB24_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %a, 2
+ %addr = getelementptr i8, ptr %base, i32 4 ; compute base + 4
+ %val = load i8, ptr %addr ; load 8-bit value
+ %ext = sext i8 %val to i32 ; sign-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lbu(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lbu:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 1
+; RV32I-NEXT: bgeu a3, a1, .LBB25_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lbu a2, 4(a0)
+; RV32I-NEXT: .LBB25_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lbu:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bltui a1, 2, .LBB25_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lbu a2, 4(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB25_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %a, 2
+ %addr = getelementptr i8, ptr %base, i32 4 ; compute base + 4
+ %val = load i8, ptr %addr ; load 8-bit value
+ %ext = zext i8 %val to i32 ; zero-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lh(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lh:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 1
+; RV32I-NEXT: bgeu a3, a1, .LBB26_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lh a2, 8(a0)
+; RV32I-NEXT: .LBB26_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lh:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bltui a1, 2, .LBB26_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lh a2, 8(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB26_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %a, 2
+ %addr = getelementptr i16, ptr %base, i32 4 ; compute base + 4
+ %val = load i16, ptr %addr ; load 16-bit value
+ %ext = sext i16 %val to i32 ; sign-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lhu(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lhu:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 1
+; RV32I-NEXT: bgeu a3, a1, .LBB27_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lhu a2, 8(a0)
+; RV32I-NEXT: .LBB27_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lhu:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bltui a1, 2, .LBB27_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lhu a2, 8(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB27_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %a, 2
+ %addr = getelementptr i16, ptr %base, i32 4 ; compute base + 4
+ %val = load i16, ptr %addr ; load 16-bit value
+ %ext = zext i16 %val to i32 ; zero-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lw(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lw:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 1
+; RV32I-NEXT: bgeu a3, a1, .LBB28_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lw a2, 16(a0)
+; RV32I-NEXT: .LBB28_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lw:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bltui a1, 2, .LBB28_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lw a2, 16(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB28_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %a, 2
+ %addr = getelementptr i32, ptr %base, i32 4 ; compute base + 4
+ %val = load i32, ptr %addr ; load 32-bit value
+ %res = select i1 %x, i32 %val, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lb_qc_e(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lb_qc_e:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 1
+; RV32I-NEXT: bgeu a3, a1, .LBB29_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: add a0, a0, a1
+; RV32I-NEXT: lb a2, 1808(a0)
+; RV32I-NEXT: .LBB29_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lb_qc_e:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bltui a1, 2, .LBB29_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.lb a2, 10000(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB29_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %a, 2
+ %addr = getelementptr i8, ptr %base, i32 10000 ; compute base + 10000
+ %val = load i8, ptr %addr ; load 8-bit value
+ %ext = sext i8 %val to i32 ; sign-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lbu_qc_e(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lbu_qc_e:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 1
+; RV32I-NEXT: bgeu a3, a1, .LBB30_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: add a0, a0, a1
+; RV32I-NEXT: lbu a2, 1808(a0)
+; RV32I-NEXT: .LBB30_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lbu_qc_e:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bltui a1, 2, .LBB30_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.lbu a2, 10000(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB30_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %a, 2
+ %addr = getelementptr i8, ptr %base, i32 10000 ; compute base + 10000
+ %val = load i8, ptr %addr ; load 8-bit value
+ %ext = zext i8 %val to i32 ; zero-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lh_qc_e(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lh_qc_e:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 1
+; RV32I-NEXT: bgeu a3, a1, .LBB31_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lui a1, 5
+; RV32I-NEXT: add a0, a0, a1
+; RV32I-NEXT: lh a2, -480(a0)
+; RV32I-NEXT: .LBB31_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lh_qc_e:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bltui a1, 2, .LBB31_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.lh a2, 20000(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB31_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %a, 2
+ %addr = getelementptr i16, ptr %base, i32 10000 ; compute base + 10000
+ %val = load i16, ptr %addr ; load 16-bit value
+ %ext = sext i16 %val to i32 ; sign-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lhu_qc_e(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lhu_qc_e:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 1
+; RV32I-NEXT: bgeu a3, a1, .LBB32_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lui a1, 5
+; RV32I-NEXT: add a0, a0, a1
+; RV32I-NEXT: lhu a2, -480(a0)
+; RV32I-NEXT: .LBB32_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lhu_qc_e:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bltui a1, 2, .LBB32_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.lhu a2, 20000(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB32_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %a, 2
+ %addr = getelementptr i16, ptr %base, i32 10000 ; compute base + 10000
+ %val = load i16, ptr %addr ; load 16-bit value
+ %ext = zext i16 %val to i32 ; zero-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lw_qc_e(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lw_qc_e:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 1
+; RV32I-NEXT: bgeu a3, a1, .LBB33_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lui a1, 10
+; RV32I-NEXT: add a0, a0, a1
+; RV32I-NEXT: lw a2, -960(a0)
+; RV32I-NEXT: .LBB33_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lw_qc_e:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bltui a1, 2, .LBB33_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.lw a2, 40000(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB33_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %a, 2
+ %addr = getelementptr i32, ptr %base, i32 10000 ; compute base + 10000
+ %val = load i32, ptr %addr ; load 32-bit value
+ %res = select i1 %x, i32 %val, i32 %b
+ ret i32 %res
+}
diff --git a/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_32_ult.ll b/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_32_ult.ll
new file mode 100644
index 0000000000000..2e3b2260b353f
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_32_ult.ll
@@ -0,0 +1,898 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 | FileCheck %s --check-prefixes=RV32I
+; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 -mattr=+xqci,+short-forward-branch-ialu,+short-forward-branch-imul,+short-forward-branch-iload,+short-forward-branch-imm,+m | \
+; RUN: FileCheck %s --check-prefixes=RV32I-SFB-WITH-IMM
+
+define i32 @branch_with_immSFB_mv(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_mv:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 2
+; RV32I-NEXT: bltu a2, a3, .LBB0_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: .LBB0_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mv:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bltui a2, 2, .LBB0_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB0_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %d, 2
+ %sel = select i1 %x, i32 %a, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_mv_zerofalsev(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_mv_zerofalsev:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: sltiu a1, a2, 2
+; RV32I-NEXT: neg a1, a1
+; RV32I-NEXT: and a0, a1, a0
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mv_zerofalsev:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.ligeui a0, a2, 2, 0
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %d, 2
+ %sel = select i1 %x, i32 %a, i32 0
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_mv_zerofalsev_swapped(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_mv_zerofalsev_swapped:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: sltiu a1, a2, 2
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: and a0, a1, a0
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mv_zerofalsev_swapped:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.liltui a0, a2, 2, 0
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %d, 2
+ %sel = select i1 %x, i32 0, i32 %a
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_mv_minusOnefalsev(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_mv_minusOnefalsev:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: sltiu a1, a2, 2
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: or a0, a1, a0
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mv_minusOnefalsev:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.ligeui a0, a2, 2, -1
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %d, 2
+ %sel = select i1 %x, i32 %a, i32 -1
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_mv_minusOnefalsev_swapped(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_mv_minusOnefalsev_swapped:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: sltiu a1, a2, 2
+; RV32I-NEXT: neg a1, a1
+; RV32I-NEXT: or a0, a1, a0
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mv_minusOnefalsev_swapped:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.liltui a0, a2, 2, -1
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %d, 2
+ %sel = select i1 %x, i32 -1, i32 %a
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_add(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_add:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a4, 2
+; RV32I-NEXT: bgeu a3, a4, .LBB5_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: add a2, a0, a1
+; RV32I-NEXT: .LBB5_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_add:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bgeui a3, 2, .LBB5_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: add a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB5_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %d, 2
+ %addi = add i32 %a, %b
+ %sel = select i1 %x, i32 %addi, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_sub(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_sub:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a4, 2
+; RV32I-NEXT: bgeu a3, a4, .LBB6_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: sub a2, a0, a1
+; RV32I-NEXT: .LBB6_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_sub:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bgeui a3, 2, .LBB6_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: sub a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB6_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %d, 2
+ %subi = sub i32 %a, %b
+ %sel = select i1 %x, i32 %subi, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_shl(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_shl:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a4, 2
+; RV32I-NEXT: bgeu a3, a4, .LBB7_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: sll a2, a0, a1
+; RV32I-NEXT: .LBB7_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_shl:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bgeui a3, 2, .LBB7_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: sll a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB7_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %d, 2
+ %shli = shl i32 %a, %b
+ %sel = select i1 %x, i32 %shli, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_lshr(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_lshr:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a4, 2
+; RV32I-NEXT: bgeu a3, a4, .LBB8_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: srl a2, a0, a1
+; RV32I-NEXT: .LBB8_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lshr:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bgeui a3, 2, .LBB8_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: srl a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB8_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %d, 2
+ %lshri = lshr i32 %a, %b
+ %sel = select i1 %x, i32 %lshri, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_ashr(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_ashr:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a4, 2
+; RV32I-NEXT: bgeu a3, a4, .LBB9_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: sra a2, a0, a1
+; RV32I-NEXT: .LBB9_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_ashr:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bgeui a3, 2, .LBB9_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: sra a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB9_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %d, 2
+ %ashri = ashr i32 %a, %b
+ %sel = select i1 %x, i32 %ashri, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_xor(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_xor:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a4, 2
+; RV32I-NEXT: bgeu a3, a4, .LBB10_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: xor a2, a0, a1
+; RV32I-NEXT: .LBB10_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_xor:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bgeui a3, 2, .LBB10_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: xor a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB10_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %d, 2
+ %xori = xor i32 %a, %b
+ %sel = select i1 %x, i32 %xori, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_and(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_and:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a4, 2
+; RV32I-NEXT: bgeu a3, a4, .LBB11_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: and a2, a0, a1
+; RV32I-NEXT: .LBB11_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_and:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bgeui a3, 2, .LBB11_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: and a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB11_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %d, 2
+ %andi = and i32 %a, %b
+ %sel = select i1 %x, i32 %andi, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_or(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_or:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a4, 2
+; RV32I-NEXT: bgeu a3, a4, .LBB12_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: or a2, a0, a1
+; RV32I-NEXT: .LBB12_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_or:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bgeui a3, 2, .LBB12_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: or a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB12_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %d, 2
+ %ori = or i32 %a, %b
+ %sel = select i1 %x, i32 %ori, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_addi(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_addi:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 2
+; RV32I-NEXT: bgeu a3, a1, .LBB13_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: addi a2, a0, 11
+; RV32I-NEXT: .LBB13_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_addi:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bgeui a3, 2, .LBB13_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: addi a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB13_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %d, 2
+ %addi = add i32 %a, 11
+ %sel = select i1 %x, i32 %addi, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_xori(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_xori:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 2
+; RV32I-NEXT: bgeu a3, a1, .LBB14_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: xori a2, a0, 11
+; RV32I-NEXT: .LBB14_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_xori:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bgeui a3, 2, .LBB14_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: xori a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB14_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %d, 2
+ %xori = xor i32 %a, 11
+ %sel = select i1 %x, i32 %xori, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_shli(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_shli:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 2
+; RV32I-NEXT: bgeu a3, a1, .LBB15_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: slli a2, a0, 11
+; RV32I-NEXT: .LBB15_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_shli:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bgeui a3, 2, .LBB15_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: slli a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB15_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %d, 2
+ %shli = shl i32 %a, 11
+ %sel = select i1 %x, i32 %shli, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_lshri(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_lshri:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 2
+; RV32I-NEXT: bgeu a3, a1, .LBB16_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: srli a2, a0, 11
+; RV32I-NEXT: .LBB16_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lshri:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bgeui a3, 2, .LBB16_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: srli a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB16_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %d, 2
+ %lshri = lshr i32 %a, 11
+ %sel = select i1 %x, i32 %lshri, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_ashri(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_ashri:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 2
+; RV32I-NEXT: bgeu a3, a1, .LBB17_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: srai a2, a0, 11
+; RV32I-NEXT: .LBB17_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_ashri:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bgeui a3, 2, .LBB17_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: srai a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB17_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %d, 2
+ %ashri = ashr i32 %a, 11
+ %sel = select i1 %x, i32 %ashri, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_andi(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_andi:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 2
+; RV32I-NEXT: bgeu a3, a1, .LBB18_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: andi a2, a0, 11
+; RV32I-NEXT: .LBB18_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_andi:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bgeui a3, 2, .LBB18_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: andi a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB18_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %d, 2
+ %andi = and i32 %a, 11
+ %sel = select i1 %x, i32 %andi, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_ori(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_ori:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 2
+; RV32I-NEXT: bgeu a3, a1, .LBB19_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: ori a2, a0, 11
+; RV32I-NEXT: .LBB19_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_ori:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bgeui a3, 2, .LBB19_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ori a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB19_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %d, 2
+ %ori = or i32 %a, 11
+ %sel = select i1 %x, i32 %ori, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_mul(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_mul:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: .cfi_def_cfa_offset 16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: .cfi_offset ra, -4
+; RV32I-NEXT: .cfi_offset s0, -8
+; RV32I-NEXT: .cfi_offset s1, -12
+; RV32I-NEXT: mv s1, a3
+; RV32I-NEXT: mv s0, a2
+; RV32I-NEXT: call __mulsi3
+; RV32I-NEXT: li a1, 2
+; RV32I-NEXT: bltu s1, a1, .LBB20_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: .LBB20_2: # %entry
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: .cfi_restore ra
+; RV32I-NEXT: .cfi_restore s0
+; RV32I-NEXT: .cfi_restore s1
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: .cfi_def_cfa_offset 0
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mul:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bgeui a3, 2, .LBB20_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mul a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB20_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %d, 2
+ %muli = mul i32 %a, %b
+ %sel = select i1 %x, i32 %muli, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_li(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_li:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 2
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: bgeu a2, a3, .LBB21_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: lui a0, 16
+; RV32I-NEXT: addi a0, a0, 7
+; RV32I-NEXT: .LBB21_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_li:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: qc.bgeui a2, 2, .LBB21_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.li a0, 65543
+; RV32I-SFB-WITH-IMM-NEXT: .LBB21_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %d, 2
+ %sel = select i1 %x, i32 65543, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_qc_e_li(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_qc_e_li:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 2
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: bgeu a2, a3, .LBB22_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: lui a0, 1025
+; RV32I-NEXT: addi a0, a0, 528
+; RV32I-NEXT: .LBB22_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_qc_e_li:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: qc.bgeui a2, 2, .LBB22_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.li a0, 4198928
+; RV32I-SFB-WITH-IMM-NEXT: .LBB22_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %d, 2
+ %sel = select i1 %x, i32 4198928, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_lui(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_lui:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 2
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: bgeu a2, a3, .LBB23_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: lui a0, 16
+; RV32I-NEXT: .LBB23_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lui:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: qc.bgeui a2, 2, .LBB23_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lui a0, 16
+; RV32I-SFB-WITH-IMM-NEXT: .LBB23_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %d, 2
+ %sel = select i1 %x, i32 65536, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_lb(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lb:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 2
+; RV32I-NEXT: bgeu a1, a3, .LBB24_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lb a2, 4(a0)
+; RV32I-NEXT: .LBB24_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lb:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bgeui a1, 2, .LBB24_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lb a2, 4(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB24_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %a, 2
+ %addr = getelementptr i8, ptr %base, i32 4 ; compute base + 4
+ %val = load i8, ptr %addr ; load 8-bit value
+ %ext = sext i8 %val to i32 ; sign-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lbu(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lbu:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 2
+; RV32I-NEXT: bgeu a1, a3, .LBB25_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lbu a2, 4(a0)
+; RV32I-NEXT: .LBB25_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lbu:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bgeui a1, 2, .LBB25_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lbu a2, 4(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB25_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %a, 2
+ %addr = getelementptr i8, ptr %base, i32 4 ; compute base + 4
+ %val = load i8, ptr %addr ; load 8-bit value
+ %ext = zext i8 %val to i32 ; zero-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lh(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lh:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 2
+; RV32I-NEXT: bgeu a1, a3, .LBB26_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lh a2, 8(a0)
+; RV32I-NEXT: .LBB26_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lh:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bgeui a1, 2, .LBB26_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lh a2, 8(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB26_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %a, 2
+ %addr = getelementptr i16, ptr %base, i32 4 ; compute base + 4
+ %val = load i16, ptr %addr ; load 16-bit value
+ %ext = sext i16 %val to i32 ; sign-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lhu(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lhu:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 2
+; RV32I-NEXT: bgeu a1, a3, .LBB27_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lhu a2, 8(a0)
+; RV32I-NEXT: .LBB27_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lhu:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bgeui a1, 2, .LBB27_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lhu a2, 8(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB27_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %a, 2
+ %addr = getelementptr i16, ptr %base, i32 4 ; compute base + 4
+ %val = load i16, ptr %addr ; load 16-bit value
+ %ext = zext i16 %val to i32 ; zero-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lw(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lw:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 2
+; RV32I-NEXT: bgeu a1, a3, .LBB28_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lw a2, 16(a0)
+; RV32I-NEXT: .LBB28_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lw:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bgeui a1, 2, .LBB28_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lw a2, 16(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB28_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %a, 2
+ %addr = getelementptr i32, ptr %base, i32 4 ; compute base + 4
+ %val = load i32, ptr %addr ; load 32-bit value
+ %res = select i1 %x, i32 %val, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lb_qc_e(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lb_qc_e:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 2
+; RV32I-NEXT: bgeu a1, a3, .LBB29_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: add a0, a0, a1
+; RV32I-NEXT: lb a2, 1808(a0)
+; RV32I-NEXT: .LBB29_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lb_qc_e:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bgeui a1, 2, .LBB29_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.lb a2, 10000(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB29_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %a, 2
+ %addr = getelementptr i8, ptr %base, i32 10000 ; compute base + 10000
+ %val = load i8, ptr %addr ; load 8-bit value
+ %ext = sext i8 %val to i32 ; sign-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lbu_qc_e(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lbu_qc_e:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 2
+; RV32I-NEXT: bgeu a1, a3, .LBB30_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: add a0, a0, a1
+; RV32I-NEXT: lbu a2, 1808(a0)
+; RV32I-NEXT: .LBB30_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lbu_qc_e:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bgeui a1, 2, .LBB30_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.lbu a2, 10000(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB30_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %a, 2
+ %addr = getelementptr i8, ptr %base, i32 10000 ; compute base + 10000
+ %val = load i8, ptr %addr ; load 8-bit value
+ %ext = zext i8 %val to i32 ; zero-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lh_qc_e(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lh_qc_e:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 2
+; RV32I-NEXT: bgeu a1, a3, .LBB31_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lui a1, 5
+; RV32I-NEXT: add a0, a0, a1
+; RV32I-NEXT: lh a2, -480(a0)
+; RV32I-NEXT: .LBB31_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lh_qc_e:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bgeui a1, 2, .LBB31_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.lh a2, 20000(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB31_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %a, 2
+ %addr = getelementptr i16, ptr %base, i32 10000 ; compute base + 10000
+ %val = load i16, ptr %addr ; load 16-bit value
+ %ext = sext i16 %val to i32 ; sign-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lhu_qc_e(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lhu_qc_e:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 2
+; RV32I-NEXT: bgeu a1, a3, .LBB32_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lui a1, 5
+; RV32I-NEXT: add a0, a0, a1
+; RV32I-NEXT: lhu a2, -480(a0)
+; RV32I-NEXT: .LBB32_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lhu_qc_e:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bgeui a1, 2, .LBB32_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.lhu a2, 20000(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB32_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %a, 2
+ %addr = getelementptr i16, ptr %base, i32 10000 ; compute base + 10000
+ %val = load i16, ptr %addr ; load 16-bit value
+ %ext = zext i16 %val to i32 ; zero-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lw_qc_e(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lw_qc_e:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a3, 2
+; RV32I-NEXT: bgeu a1, a3, .LBB33_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lui a1, 10
+; RV32I-NEXT: add a0, a0, a1
+; RV32I-NEXT: lw a2, -960(a0)
+; RV32I-NEXT: .LBB33_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lw_qc_e:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.bgeui a1, 2, .LBB33_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.lw a2, 40000(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB33_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %a, 2
+ %addr = getelementptr i32, ptr %base, i32 10000 ; compute base + 10000
+ %val = load i32, ptr %addr ; load 32-bit value
+ %res = select i1 %x, i32 %val, i32 %b
+ ret i32 %res
+}
diff --git a/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_48_eq.ll b/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_48_eq.ll
new file mode 100644
index 0000000000000..859d5897a3ac3
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_48_eq.ll
@@ -0,0 +1,952 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 | FileCheck %s --check-prefixes=RV32I
+; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 -mattr=+xqci,+short-forward-branch-ialu,+short-forward-branch-imul,+short-forward-branch-iload,+short-forward-branch-imm,+m | \
+; RUN: FileCheck %s --check-prefixes=RV32I-SFB-WITH-IMM
+
+define i32 @branch_with_immSFB_mv(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_mv:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a3, a3, 1819
+; RV32I-NEXT: beq a2, a3, .LBB0_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: .LBB0_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mv:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.beqi a2, 10011, .LBB0_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB0_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %d, 10011
+ %sel = select i1 %x, i32 %a, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_mv_zerofalsev(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_mv_zerofalsev:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1819
+; RV32I-NEXT: xor a1, a2, a1
+; RV32I-NEXT: snez a1, a1
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: and a0, a1, a0
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mv_zerofalsev:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.beqi a2, 10011, .LBB1_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: li a0, 0
+; RV32I-SFB-WITH-IMM-NEXT: .LBB1_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %d, 10011
+ %sel = select i1 %x, i32 %a, i32 0
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_mv_zerofalsev_swapped(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_mv_zerofalsev_swapped:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1819
+; RV32I-NEXT: xor a1, a2, a1
+; RV32I-NEXT: seqz a1, a1
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: and a0, a1, a0
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mv_zerofalsev_swapped:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bnei a2, 10011, .LBB2_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: li a0, 0
+; RV32I-SFB-WITH-IMM-NEXT: .LBB2_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %d, 10011
+ %sel = select i1 %x, i32 0, i32 %a
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_mv_minusOnefalsev(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_mv_minusOnefalsev:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1819
+; RV32I-NEXT: xor a1, a2, a1
+; RV32I-NEXT: seqz a1, a1
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: or a0, a1, a0
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mv_minusOnefalsev:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: li a1, -1
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.beqi a2, 10011, .LBB3_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB3_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %d, 10011
+ %sel = select i1 %x, i32 %a, i32 -1
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_mv_minusOnefalsev_swapped(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_mv_minusOnefalsev_swapped:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1819
+; RV32I-NEXT: xor a1, a2, a1
+; RV32I-NEXT: snez a1, a1
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: or a0, a1, a0
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mv_minusOnefalsev_swapped:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: li a1, -1
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bnei a2, 10011, .LBB4_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB4_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %d, 10011
+ %sel = select i1 %x, i32 -1, i32 %a
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_add(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_add:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a4, 2
+; RV32I-NEXT: addi a4, a4, 1819
+; RV32I-NEXT: bne a3, a4, .LBB5_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: add a2, a0, a1
+; RV32I-NEXT: .LBB5_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_add:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bnei a3, 10011, .LBB5_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: add a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB5_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %d, 10011
+ %addi = add i32 %a, %b
+ %sel = select i1 %x, i32 %addi, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_sub(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_sub:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a4, 2
+; RV32I-NEXT: addi a4, a4, 1819
+; RV32I-NEXT: bne a3, a4, .LBB6_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: sub a2, a0, a1
+; RV32I-NEXT: .LBB6_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_sub:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bnei a3, 10011, .LBB6_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: sub a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB6_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %d, 10011
+ %subi = sub i32 %a, %b
+ %sel = select i1 %x, i32 %subi, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_shl(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_shl:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a4, 2
+; RV32I-NEXT: addi a4, a4, 1819
+; RV32I-NEXT: bne a3, a4, .LBB7_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: sll a2, a0, a1
+; RV32I-NEXT: .LBB7_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_shl:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bnei a3, 10011, .LBB7_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: sll a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB7_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %d, 10011
+ %shli = shl i32 %a, %b
+ %sel = select i1 %x, i32 %shli, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_lshr(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_lshr:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a4, 2
+; RV32I-NEXT: addi a4, a4, 1819
+; RV32I-NEXT: bne a3, a4, .LBB8_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: srl a2, a0, a1
+; RV32I-NEXT: .LBB8_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lshr:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bnei a3, 10011, .LBB8_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: srl a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB8_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %d, 10011
+ %lshri = lshr i32 %a, %b
+ %sel = select i1 %x, i32 %lshri, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_ashr(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_ashr:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a4, 2
+; RV32I-NEXT: addi a4, a4, 1819
+; RV32I-NEXT: bne a3, a4, .LBB9_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: sra a2, a0, a1
+; RV32I-NEXT: .LBB9_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_ashr:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bnei a3, 10011, .LBB9_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: sra a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB9_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %d, 10011
+ %ashri = ashr i32 %a, %b
+ %sel = select i1 %x, i32 %ashri, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_xor(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_xor:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a4, 2
+; RV32I-NEXT: addi a4, a4, 1819
+; RV32I-NEXT: bne a3, a4, .LBB10_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: xor a2, a0, a1
+; RV32I-NEXT: .LBB10_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_xor:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bnei a3, 10011, .LBB10_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: xor a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB10_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %d, 10011
+ %xori = xor i32 %a, %b
+ %sel = select i1 %x, i32 %xori, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_and(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_and:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a4, 2
+; RV32I-NEXT: addi a4, a4, 1819
+; RV32I-NEXT: bne a3, a4, .LBB11_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: and a2, a0, a1
+; RV32I-NEXT: .LBB11_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_and:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bnei a3, 10011, .LBB11_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: and a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB11_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %d, 10011
+ %andi = and i32 %a, %b
+ %sel = select i1 %x, i32 %andi, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_or(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_or:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a4, 2
+; RV32I-NEXT: addi a4, a4, 1819
+; RV32I-NEXT: bne a3, a4, .LBB12_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: or a2, a0, a1
+; RV32I-NEXT: .LBB12_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_or:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bnei a3, 10011, .LBB12_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: or a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB12_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %d, 10011
+ %ori = or i32 %a, %b
+ %sel = select i1 %x, i32 %ori, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_addi(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_addi:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1819
+; RV32I-NEXT: bne a3, a1, .LBB13_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: addi a2, a0, 11
+; RV32I-NEXT: .LBB13_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_addi:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bnei a3, 10011, .LBB13_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: addi a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB13_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %d, 10011
+ %addi = add i32 %a, 11
+ %sel = select i1 %x, i32 %addi, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_xori(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_xori:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1819
+; RV32I-NEXT: bne a3, a1, .LBB14_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: xori a2, a0, 11
+; RV32I-NEXT: .LBB14_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_xori:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bnei a3, 10011, .LBB14_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: xori a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB14_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %d, 10011
+ %xori = xor i32 %a, 11
+ %sel = select i1 %x, i32 %xori, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_shli(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_shli:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1819
+; RV32I-NEXT: bne a3, a1, .LBB15_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: slli a2, a0, 11
+; RV32I-NEXT: .LBB15_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_shli:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bnei a3, 10011, .LBB15_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: slli a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB15_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %d, 10011
+ %shli = shl i32 %a, 11
+ %sel = select i1 %x, i32 %shli, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_lshri(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_lshri:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1819
+; RV32I-NEXT: bne a3, a1, .LBB16_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: srli a2, a0, 11
+; RV32I-NEXT: .LBB16_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lshri:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bnei a3, 10011, .LBB16_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: srli a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB16_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %d, 10011
+ %lshri = lshr i32 %a, 11
+ %sel = select i1 %x, i32 %lshri, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_ashri(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_ashri:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1819
+; RV32I-NEXT: bne a3, a1, .LBB17_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: srai a2, a0, 11
+; RV32I-NEXT: .LBB17_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_ashri:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bnei a3, 10011, .LBB17_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: srai a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB17_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %d, 10011
+ %ashri = ashr i32 %a, 11
+ %sel = select i1 %x, i32 %ashri, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_andi(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_andi:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1819
+; RV32I-NEXT: bne a3, a1, .LBB18_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: andi a2, a0, 11
+; RV32I-NEXT: .LBB18_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_andi:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bnei a3, 10011, .LBB18_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: andi a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB18_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %d, 10011
+ %andi = and i32 %a, 11
+ %sel = select i1 %x, i32 %andi, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_ori(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_ori:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1819
+; RV32I-NEXT: bne a3, a1, .LBB19_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: ori a2, a0, 11
+; RV32I-NEXT: .LBB19_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_ori:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bnei a3, 10011, .LBB19_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ori a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB19_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %d, 10011
+ %ori = or i32 %a, 11
+ %sel = select i1 %x, i32 %ori, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_mul(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_mul:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: .cfi_def_cfa_offset 16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: .cfi_offset ra, -4
+; RV32I-NEXT: .cfi_offset s0, -8
+; RV32I-NEXT: .cfi_offset s1, -12
+; RV32I-NEXT: mv s1, a3
+; RV32I-NEXT: mv s0, a2
+; RV32I-NEXT: call __mulsi3
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1819
+; RV32I-NEXT: beq s1, a1, .LBB20_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: .LBB20_2: # %entry
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: .cfi_restore ra
+; RV32I-NEXT: .cfi_restore s0
+; RV32I-NEXT: .cfi_restore s1
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: .cfi_def_cfa_offset 0
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mul:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bnei a3, 10011, .LBB20_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mul a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB20_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %d, 10011
+ %muli = mul i32 %a, %b
+ %sel = select i1 %x, i32 %muli, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_li(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_li:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a0, 2
+; RV32I-NEXT: addi a3, a0, 1819
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: bne a2, a3, .LBB21_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: lui a0, 16
+; RV32I-NEXT: addi a0, a0, 7
+; RV32I-NEXT: .LBB21_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_li:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bnei a2, 10011, .LBB21_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.li a0, 65543
+; RV32I-SFB-WITH-IMM-NEXT: .LBB21_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %d, 10011
+ %sel = select i1 %x, i32 65543, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_qc_e_li(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_qc_e_li:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a0, 2
+; RV32I-NEXT: addi a3, a0, 1819
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: bne a2, a3, .LBB22_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: lui a0, 1025
+; RV32I-NEXT: addi a0, a0, 528
+; RV32I-NEXT: .LBB22_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_qc_e_li:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bnei a2, 10011, .LBB22_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.li a0, 4198928
+; RV32I-SFB-WITH-IMM-NEXT: .LBB22_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %d, 10011
+ %sel = select i1 %x, i32 4198928, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_lui(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_lui:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a0, 2
+; RV32I-NEXT: addi a3, a0, 1819
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: bne a2, a3, .LBB23_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: lui a0, 16
+; RV32I-NEXT: .LBB23_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lui:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bnei a2, 10011, .LBB23_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lui a0, 16
+; RV32I-SFB-WITH-IMM-NEXT: .LBB23_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %d, 10011
+ %sel = select i1 %x, i32 65536, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_lb(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lb:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a3, a3, 1819
+; RV32I-NEXT: bne a1, a3, .LBB24_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lb a2, 4(a0)
+; RV32I-NEXT: .LBB24_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lb:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bnei a1, 10011, .LBB24_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lb a2, 4(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB24_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %a, 10011
+ %addr = getelementptr i8, ptr %base, i32 4 ; compute base + 4
+ %val = load i8, ptr %addr ; load 8-bit value
+ %ext = sext i8 %val to i32 ; sign-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lbu(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lbu:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a3, a3, 1819
+; RV32I-NEXT: bne a1, a3, .LBB25_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lbu a2, 4(a0)
+; RV32I-NEXT: .LBB25_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lbu:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bnei a1, 10011, .LBB25_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lbu a2, 4(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB25_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %a, 10011
+ %addr = getelementptr i8, ptr %base, i32 4 ; compute base + 4
+ %val = load i8, ptr %addr ; load 8-bit value
+ %ext = zext i8 %val to i32 ; zero-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lh(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lh:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a3, a3, 1819
+; RV32I-NEXT: bne a1, a3, .LBB26_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lh a2, 8(a0)
+; RV32I-NEXT: .LBB26_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lh:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bnei a1, 10011, .LBB26_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lh a2, 8(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB26_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %a, 10011
+ %addr = getelementptr i16, ptr %base, i32 4 ; compute base + 4
+ %val = load i16, ptr %addr ; load 16-bit value
+ %ext = sext i16 %val to i32 ; sign-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lhu(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lhu:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a3, a3, 1819
+; RV32I-NEXT: bne a1, a3, .LBB27_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lhu a2, 8(a0)
+; RV32I-NEXT: .LBB27_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lhu:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bnei a1, 10011, .LBB27_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lhu a2, 8(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB27_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %a, 10011
+ %addr = getelementptr i16, ptr %base, i32 4 ; compute base + 4
+ %val = load i16, ptr %addr ; load 16-bit value
+ %ext = zext i16 %val to i32 ; zero-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lw(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lw:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a3, a3, 1819
+; RV32I-NEXT: bne a1, a3, .LBB28_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lw a2, 16(a0)
+; RV32I-NEXT: .LBB28_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lw:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bnei a1, 10011, .LBB28_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lw a2, 16(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB28_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %a, 10011
+ %addr = getelementptr i32, ptr %base, i32 4 ; compute base + 4
+ %val = load i32, ptr %addr ; load 32-bit value
+ %res = select i1 %x, i32 %val, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lb_qc_e(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lb_qc_e:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a4, a3, 1819
+; RV32I-NEXT: bne a1, a4, .LBB29_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: add a0, a0, a3
+; RV32I-NEXT: lb a2, 1808(a0)
+; RV32I-NEXT: .LBB29_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lb_qc_e:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bnei a1, 10011, .LBB29_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.lb a2, 10000(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB29_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %a, 10011
+ %addr = getelementptr i8, ptr %base, i32 10000 ; compute base + 10000
+ %val = load i8, ptr %addr ; load 8-bit value
+ %ext = sext i8 %val to i32 ; sign-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lbu_qc_e(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lbu_qc_e:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a4, a3, 1819
+; RV32I-NEXT: bne a1, a4, .LBB30_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: add a0, a0, a3
+; RV32I-NEXT: lbu a2, 1808(a0)
+; RV32I-NEXT: .LBB30_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lbu_qc_e:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bnei a1, 10011, .LBB30_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.lbu a2, 10000(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB30_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %a, 10011
+ %addr = getelementptr i8, ptr %base, i32 10000 ; compute base + 10000
+ %val = load i8, ptr %addr ; load 8-bit value
+ %ext = zext i8 %val to i32 ; zero-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lh_qc_e(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lh_qc_e:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a3, a3, 1819
+; RV32I-NEXT: bne a1, a3, .LBB31_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lui a1, 5
+; RV32I-NEXT: add a0, a0, a1
+; RV32I-NEXT: lh a2, -480(a0)
+; RV32I-NEXT: .LBB31_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lh_qc_e:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bnei a1, 10011, .LBB31_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.lh a2, 20000(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB31_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %a, 10011
+ %addr = getelementptr i16, ptr %base, i32 10000 ; compute base + 10000
+ %val = load i16, ptr %addr ; load 16-bit value
+ %ext = sext i16 %val to i32 ; sign-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lhu_qc_e(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lhu_qc_e:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a3, a3, 1819
+; RV32I-NEXT: bne a1, a3, .LBB32_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lui a1, 5
+; RV32I-NEXT: add a0, a0, a1
+; RV32I-NEXT: lhu a2, -480(a0)
+; RV32I-NEXT: .LBB32_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lhu_qc_e:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bnei a1, 10011, .LBB32_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.lhu a2, 20000(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB32_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %a, 10011
+ %addr = getelementptr i16, ptr %base, i32 10000 ; compute base + 10000
+ %val = load i16, ptr %addr ; load 16-bit value
+ %ext = zext i16 %val to i32 ; zero-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lw_qc_e(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lw_qc_e:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a3, a3, 1819
+; RV32I-NEXT: bne a1, a3, .LBB33_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lui a1, 10
+; RV32I-NEXT: add a0, a0, a1
+; RV32I-NEXT: lw a2, -960(a0)
+; RV32I-NEXT: .LBB33_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lw_qc_e:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bnei a1, 10011, .LBB33_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.lw a2, 40000(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB33_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp eq i32 %a, 10011
+ %addr = getelementptr i32, ptr %base, i32 10000 ; compute base + 10000
+ %val = load i32, ptr %addr ; load 32-bit value
+ %res = select i1 %x, i32 %val, i32 %b
+ ret i32 %res
+}
diff --git a/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_48_ne.ll b/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_48_ne.ll
new file mode 100644
index 0000000000000..e98b2a44d4a7f
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_48_ne.ll
@@ -0,0 +1,952 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 | FileCheck %s --check-prefixes=RV32I
+; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 -mattr=+xqci,+short-forward-branch-ialu,+short-forward-branch-imul,+short-forward-branch-iload,+short-forward-branch-imm,+m | \
+; RUN: FileCheck %s --check-prefixes=RV32I-SFB-WITH-IMM
+
+define i32 @branch_with_immSFB_mv(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_mv:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a3, a3, 1819
+; RV32I-NEXT: bne a2, a3, .LBB0_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: .LBB0_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mv:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bnei a2, 10011, .LBB0_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB0_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %d, 10011
+ %sel = select i1 %x, i32 %a, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_mv_zerofalsev(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_mv_zerofalsev:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1819
+; RV32I-NEXT: xor a1, a2, a1
+; RV32I-NEXT: seqz a1, a1
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: and a0, a1, a0
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mv_zerofalsev:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bnei a2, 10011, .LBB1_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: li a0, 0
+; RV32I-SFB-WITH-IMM-NEXT: .LBB1_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %d, 10011
+ %sel = select i1 %x, i32 %a, i32 0
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_mv_zerofalsev_swapped(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_mv_zerofalsev_swapped:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1819
+; RV32I-NEXT: xor a1, a2, a1
+; RV32I-NEXT: snez a1, a1
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: and a0, a1, a0
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mv_zerofalsev_swapped:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.beqi a2, 10011, .LBB2_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: li a0, 0
+; RV32I-SFB-WITH-IMM-NEXT: .LBB2_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %d, 10011
+ %sel = select i1 %x, i32 0, i32 %a
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_mv_minusOnefalsev(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_mv_minusOnefalsev:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1819
+; RV32I-NEXT: xor a1, a2, a1
+; RV32I-NEXT: snez a1, a1
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: or a0, a1, a0
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mv_minusOnefalsev:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: li a1, -1
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bnei a2, 10011, .LBB3_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB3_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %d, 10011
+ %sel = select i1 %x, i32 %a, i32 -1
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_mv_minusOnefalsev_swapped(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_mv_minusOnefalsev_swapped:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1819
+; RV32I-NEXT: xor a1, a2, a1
+; RV32I-NEXT: seqz a1, a1
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: or a0, a1, a0
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mv_minusOnefalsev_swapped:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: li a1, -1
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.beqi a2, 10011, .LBB4_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB4_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %d, 10011
+ %sel = select i1 %x, i32 -1, i32 %a
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_add(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_add:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a4, 2
+; RV32I-NEXT: addi a4, a4, 1819
+; RV32I-NEXT: beq a3, a4, .LBB5_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: add a2, a0, a1
+; RV32I-NEXT: .LBB5_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_add:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.beqi a3, 10011, .LBB5_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: add a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB5_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %d, 10011
+ %addi = add i32 %a, %b
+ %sel = select i1 %x, i32 %addi, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_sub(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_sub:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a4, 2
+; RV32I-NEXT: addi a4, a4, 1819
+; RV32I-NEXT: beq a3, a4, .LBB6_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: sub a2, a0, a1
+; RV32I-NEXT: .LBB6_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_sub:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.beqi a3, 10011, .LBB6_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: sub a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB6_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %d, 10011
+ %subi = sub i32 %a, %b
+ %sel = select i1 %x, i32 %subi, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_shl(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_shl:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a4, 2
+; RV32I-NEXT: addi a4, a4, 1819
+; RV32I-NEXT: beq a3, a4, .LBB7_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: sll a2, a0, a1
+; RV32I-NEXT: .LBB7_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_shl:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.beqi a3, 10011, .LBB7_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: sll a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB7_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %d, 10011
+ %shli = shl i32 %a, %b
+ %sel = select i1 %x, i32 %shli, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_lshr(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_lshr:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a4, 2
+; RV32I-NEXT: addi a4, a4, 1819
+; RV32I-NEXT: beq a3, a4, .LBB8_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: srl a2, a0, a1
+; RV32I-NEXT: .LBB8_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lshr:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.beqi a3, 10011, .LBB8_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: srl a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB8_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %d, 10011
+ %lshri = lshr i32 %a, %b
+ %sel = select i1 %x, i32 %lshri, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_ashr(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_ashr:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a4, 2
+; RV32I-NEXT: addi a4, a4, 1819
+; RV32I-NEXT: beq a3, a4, .LBB9_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: sra a2, a0, a1
+; RV32I-NEXT: .LBB9_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_ashr:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.beqi a3, 10011, .LBB9_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: sra a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB9_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %d, 10011
+ %ashri = ashr i32 %a, %b
+ %sel = select i1 %x, i32 %ashri, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_xor(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_xor:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a4, 2
+; RV32I-NEXT: addi a4, a4, 1819
+; RV32I-NEXT: beq a3, a4, .LBB10_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: xor a2, a0, a1
+; RV32I-NEXT: .LBB10_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_xor:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.beqi a3, 10011, .LBB10_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: xor a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB10_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %d, 10011
+ %xori = xor i32 %a, %b
+ %sel = select i1 %x, i32 %xori, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_and(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_and:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a4, 2
+; RV32I-NEXT: addi a4, a4, 1819
+; RV32I-NEXT: beq a3, a4, .LBB11_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: and a2, a0, a1
+; RV32I-NEXT: .LBB11_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_and:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.beqi a3, 10011, .LBB11_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: and a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB11_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %d, 10011
+ %andi = and i32 %a, %b
+ %sel = select i1 %x, i32 %andi, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_or(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_or:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a4, 2
+; RV32I-NEXT: addi a4, a4, 1819
+; RV32I-NEXT: beq a3, a4, .LBB12_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: or a2, a0, a1
+; RV32I-NEXT: .LBB12_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_or:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.beqi a3, 10011, .LBB12_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: or a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB12_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %d, 10011
+ %ori = or i32 %a, %b
+ %sel = select i1 %x, i32 %ori, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_addi(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_addi:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1819
+; RV32I-NEXT: beq a3, a1, .LBB13_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: addi a2, a0, 11
+; RV32I-NEXT: .LBB13_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_addi:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.beqi a3, 10011, .LBB13_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: addi a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB13_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %d, 10011
+ %addi = add i32 %a, 11
+ %sel = select i1 %x, i32 %addi, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_xori(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_xori:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1819
+; RV32I-NEXT: beq a3, a1, .LBB14_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: xori a2, a0, 11
+; RV32I-NEXT: .LBB14_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_xori:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.beqi a3, 10011, .LBB14_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: xori a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB14_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %d, 10011
+ %xori = xor i32 %a, 11
+ %sel = select i1 %x, i32 %xori, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_shli(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_shli:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1819
+; RV32I-NEXT: beq a3, a1, .LBB15_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: slli a2, a0, 11
+; RV32I-NEXT: .LBB15_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_shli:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.beqi a3, 10011, .LBB15_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: slli a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB15_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %d, 10011
+ %shli = shl i32 %a, 11
+ %sel = select i1 %x, i32 %shli, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_lshri(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_lshri:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1819
+; RV32I-NEXT: beq a3, a1, .LBB16_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: srli a2, a0, 11
+; RV32I-NEXT: .LBB16_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lshri:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.beqi a3, 10011, .LBB16_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: srli a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB16_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %d, 10011
+ %lshri = lshr i32 %a, 11
+ %sel = select i1 %x, i32 %lshri, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_ashri(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_ashri:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1819
+; RV32I-NEXT: beq a3, a1, .LBB17_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: srai a2, a0, 11
+; RV32I-NEXT: .LBB17_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_ashri:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.beqi a3, 10011, .LBB17_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: srai a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB17_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %d, 10011
+ %ashri = ashr i32 %a, 11
+ %sel = select i1 %x, i32 %ashri, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_andi(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_andi:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1819
+; RV32I-NEXT: beq a3, a1, .LBB18_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: andi a2, a0, 11
+; RV32I-NEXT: .LBB18_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_andi:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.beqi a3, 10011, .LBB18_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: andi a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB18_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %d, 10011
+ %andi = and i32 %a, 11
+ %sel = select i1 %x, i32 %andi, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_ori(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_ori:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1819
+; RV32I-NEXT: beq a3, a1, .LBB19_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: ori a2, a0, 11
+; RV32I-NEXT: .LBB19_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_ori:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.beqi a3, 10011, .LBB19_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ori a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB19_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %d, 10011
+ %ori = or i32 %a, 11
+ %sel = select i1 %x, i32 %ori, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_mul(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_mul:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: .cfi_def_cfa_offset 16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: .cfi_offset ra, -4
+; RV32I-NEXT: .cfi_offset s0, -8
+; RV32I-NEXT: .cfi_offset s1, -12
+; RV32I-NEXT: mv s1, a3
+; RV32I-NEXT: mv s0, a2
+; RV32I-NEXT: call __mulsi3
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1819
+; RV32I-NEXT: bne s1, a1, .LBB20_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: .LBB20_2: # %entry
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: .cfi_restore ra
+; RV32I-NEXT: .cfi_restore s0
+; RV32I-NEXT: .cfi_restore s1
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: .cfi_def_cfa_offset 0
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mul:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.beqi a3, 10011, .LBB20_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mul a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB20_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %d, 10011
+ %muli = mul i32 %a, %b
+ %sel = select i1 %x, i32 %muli, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_li(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_li:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a0, 2
+; RV32I-NEXT: addi a3, a0, 1819
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: beq a2, a3, .LBB21_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: lui a0, 16
+; RV32I-NEXT: addi a0, a0, 7
+; RV32I-NEXT: .LBB21_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_li:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.beqi a2, 10011, .LBB21_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.li a0, 65543
+; RV32I-SFB-WITH-IMM-NEXT: .LBB21_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %d, 10011
+ %sel = select i1 %x, i32 65543, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_qc_e_li(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_qc_e_li:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a0, 2
+; RV32I-NEXT: addi a3, a0, 1819
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: beq a2, a3, .LBB22_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: lui a0, 1025
+; RV32I-NEXT: addi a0, a0, 528
+; RV32I-NEXT: .LBB22_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_qc_e_li:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.beqi a2, 10011, .LBB22_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.li a0, 4198928
+; RV32I-SFB-WITH-IMM-NEXT: .LBB22_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %d, 10011
+ %sel = select i1 %x, i32 4198928, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_lui(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_lui:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a0, 2
+; RV32I-NEXT: addi a3, a0, 1819
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: beq a2, a3, .LBB23_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: lui a0, 16
+; RV32I-NEXT: .LBB23_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lui:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.beqi a2, 10011, .LBB23_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lui a0, 16
+; RV32I-SFB-WITH-IMM-NEXT: .LBB23_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %d, 10011
+ %sel = select i1 %x, i32 65536, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_lb(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lb:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a3, a3, 1819
+; RV32I-NEXT: beq a1, a3, .LBB24_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lb a2, 4(a0)
+; RV32I-NEXT: .LBB24_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lb:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.beqi a1, 10011, .LBB24_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lb a2, 4(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB24_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %a, 10011
+ %addr = getelementptr i8, ptr %base, i32 4 ; compute base + 4
+ %val = load i8, ptr %addr ; load 8-bit value
+ %ext = sext i8 %val to i32 ; sign-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lbu(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lbu:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a3, a3, 1819
+; RV32I-NEXT: beq a1, a3, .LBB25_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lbu a2, 4(a0)
+; RV32I-NEXT: .LBB25_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lbu:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.beqi a1, 10011, .LBB25_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lbu a2, 4(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB25_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %a, 10011
+ %addr = getelementptr i8, ptr %base, i32 4 ; compute base + 4
+ %val = load i8, ptr %addr ; load 8-bit value
+ %ext = zext i8 %val to i32 ; zero-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lh(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lh:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a3, a3, 1819
+; RV32I-NEXT: beq a1, a3, .LBB26_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lh a2, 8(a0)
+; RV32I-NEXT: .LBB26_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lh:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.beqi a1, 10011, .LBB26_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lh a2, 8(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB26_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %a, 10011
+ %addr = getelementptr i16, ptr %base, i32 4 ; compute base + 4
+ %val = load i16, ptr %addr ; load 16-bit value
+ %ext = sext i16 %val to i32 ; sign-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lhu(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lhu:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a3, a3, 1819
+; RV32I-NEXT: beq a1, a3, .LBB27_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lhu a2, 8(a0)
+; RV32I-NEXT: .LBB27_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lhu:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.beqi a1, 10011, .LBB27_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lhu a2, 8(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB27_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %a, 10011
+ %addr = getelementptr i16, ptr %base, i32 4 ; compute base + 4
+ %val = load i16, ptr %addr ; load 16-bit value
+ %ext = zext i16 %val to i32 ; zero-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lw(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lw:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a3, a3, 1819
+; RV32I-NEXT: beq a1, a3, .LBB28_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lw a2, 16(a0)
+; RV32I-NEXT: .LBB28_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lw:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.beqi a1, 10011, .LBB28_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lw a2, 16(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB28_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %a, 10011
+ %addr = getelementptr i32, ptr %base, i32 4 ; compute base + 4
+ %val = load i32, ptr %addr ; load 32-bit value
+ %res = select i1 %x, i32 %val, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lb_qc_e(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lb_qc_e:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a4, a3, 1819
+; RV32I-NEXT: beq a1, a4, .LBB29_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: add a0, a0, a3
+; RV32I-NEXT: lb a2, 1808(a0)
+; RV32I-NEXT: .LBB29_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lb_qc_e:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.beqi a1, 10011, .LBB29_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.lb a2, 10000(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB29_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %a, 10011
+ %addr = getelementptr i8, ptr %base, i32 10000 ; compute base + 10000
+ %val = load i8, ptr %addr ; load 8-bit value
+ %ext = sext i8 %val to i32 ; sign-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lbu_qc_e(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lbu_qc_e:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a4, a3, 1819
+; RV32I-NEXT: beq a1, a4, .LBB30_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: add a0, a0, a3
+; RV32I-NEXT: lbu a2, 1808(a0)
+; RV32I-NEXT: .LBB30_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lbu_qc_e:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.beqi a1, 10011, .LBB30_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.lbu a2, 10000(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB30_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %a, 10011
+ %addr = getelementptr i8, ptr %base, i32 10000 ; compute base + 10000
+ %val = load i8, ptr %addr ; load 8-bit value
+ %ext = zext i8 %val to i32 ; zero-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lh_qc_e(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lh_qc_e:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a3, a3, 1819
+; RV32I-NEXT: beq a1, a3, .LBB31_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lui a1, 5
+; RV32I-NEXT: add a0, a0, a1
+; RV32I-NEXT: lh a2, -480(a0)
+; RV32I-NEXT: .LBB31_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lh_qc_e:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.beqi a1, 10011, .LBB31_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.lh a2, 20000(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB31_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %a, 10011
+ %addr = getelementptr i16, ptr %base, i32 10000 ; compute base + 10000
+ %val = load i16, ptr %addr ; load 16-bit value
+ %ext = sext i16 %val to i32 ; sign-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lhu_qc_e(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lhu_qc_e:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a3, a3, 1819
+; RV32I-NEXT: beq a1, a3, .LBB32_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lui a1, 5
+; RV32I-NEXT: add a0, a0, a1
+; RV32I-NEXT: lhu a2, -480(a0)
+; RV32I-NEXT: .LBB32_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lhu_qc_e:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.beqi a1, 10011, .LBB32_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.lhu a2, 20000(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB32_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %a, 10011
+ %addr = getelementptr i16, ptr %base, i32 10000 ; compute base + 10000
+ %val = load i16, ptr %addr ; load 16-bit value
+ %ext = zext i16 %val to i32 ; zero-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lw_qc_e(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lw_qc_e:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a3, a3, 1819
+; RV32I-NEXT: beq a1, a3, .LBB33_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lui a1, 10
+; RV32I-NEXT: add a0, a0, a1
+; RV32I-NEXT: lw a2, -960(a0)
+; RV32I-NEXT: .LBB33_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lw_qc_e:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.beqi a1, 10011, .LBB33_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.lw a2, 40000(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB33_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ne i32 %a, 10011
+ %addr = getelementptr i32, ptr %base, i32 10000 ; compute base + 10000
+ %val = load i32, ptr %addr ; load 32-bit value
+ %res = select i1 %x, i32 %val, i32 %b
+ ret i32 %res
+}
diff --git a/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_48_sge.ll b/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_48_sge.ll
new file mode 100644
index 0000000000000..7d0d5ec80eda0
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_48_sge.ll
@@ -0,0 +1,948 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 | FileCheck %s --check-prefixes=RV32I
+; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 -mattr=+xqci,+short-forward-branch-ialu,+short-forward-branch-imul,+short-forward-branch-iload,+short-forward-branch-imm,+m | \
+; RUN: FileCheck %s --check-prefixes=RV32I-SFB-WITH-IMM
+
+define i32 @branch_with_immSFB_mv(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_mv:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a3, a3, 1818
+; RV32I-NEXT: blt a3, a2, .LBB0_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: .LBB0_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mv:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgei a2, 10011, .LBB0_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB0_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %d, 10011
+ %sel = select i1 %x, i32 %a, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_mv_zerofalsev(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_mv_zerofalsev:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1818
+; RV32I-NEXT: slt a1, a1, a2
+; RV32I-NEXT: neg a1, a1
+; RV32I-NEXT: and a0, a1, a0
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mv_zerofalsev:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgei a2, 10011, .LBB1_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: li a0, 0
+; RV32I-SFB-WITH-IMM-NEXT: .LBB1_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %d, 10011
+ %sel = select i1 %x, i32 %a, i32 0
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_mv_zerofalsev_swapped(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_mv_zerofalsev_swapped:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1818
+; RV32I-NEXT: slt a1, a1, a2
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: and a0, a1, a0
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mv_zerofalsev_swapped:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.blti a2, 10011, .LBB2_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: li a0, 0
+; RV32I-SFB-WITH-IMM-NEXT: .LBB2_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %d, 10011
+ %sel = select i1 %x, i32 0, i32 %a
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_mv_minusOnefalsev(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_mv_minusOnefalsev:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1818
+; RV32I-NEXT: slt a1, a1, a2
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: or a0, a1, a0
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mv_minusOnefalsev:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: li a1, -1
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgei a2, 10011, .LBB3_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB3_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %d, 10011
+ %sel = select i1 %x, i32 %a, i32 -1
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_mv_minusOnefalsev_swapped(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_mv_minusOnefalsev_swapped:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1818
+; RV32I-NEXT: slt a1, a1, a2
+; RV32I-NEXT: neg a1, a1
+; RV32I-NEXT: or a0, a1, a0
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mv_minusOnefalsev_swapped:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: li a1, -1
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.blti a2, 10011, .LBB4_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB4_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %d, 10011
+ %sel = select i1 %x, i32 -1, i32 %a
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_add(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_add:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a4, 2
+; RV32I-NEXT: addi a4, a4, 1818
+; RV32I-NEXT: bge a4, a3, .LBB5_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: add a2, a0, a1
+; RV32I-NEXT: .LBB5_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_add:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.blti a3, 10011, .LBB5_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: add a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB5_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %d, 10011
+ %addi = add i32 %a, %b
+ %sel = select i1 %x, i32 %addi, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_sub(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_sub:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a4, 2
+; RV32I-NEXT: addi a4, a4, 1818
+; RV32I-NEXT: bge a4, a3, .LBB6_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: sub a2, a0, a1
+; RV32I-NEXT: .LBB6_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_sub:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.blti a3, 10011, .LBB6_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: sub a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB6_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %d, 10011
+ %subi = sub i32 %a, %b
+ %sel = select i1 %x, i32 %subi, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_shl(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_shl:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a4, 2
+; RV32I-NEXT: addi a4, a4, 1818
+; RV32I-NEXT: bge a4, a3, .LBB7_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: sll a2, a0, a1
+; RV32I-NEXT: .LBB7_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_shl:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.blti a3, 10011, .LBB7_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: sll a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB7_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %d, 10011
+ %shli = shl i32 %a, %b
+ %sel = select i1 %x, i32 %shli, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_lshr(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_lshr:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a4, 2
+; RV32I-NEXT: addi a4, a4, 1818
+; RV32I-NEXT: bge a4, a3, .LBB8_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: srl a2, a0, a1
+; RV32I-NEXT: .LBB8_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lshr:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.blti a3, 10011, .LBB8_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: srl a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB8_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %d, 10011
+ %lshri = lshr i32 %a, %b
+ %sel = select i1 %x, i32 %lshri, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_ashr(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_ashr:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a4, 2
+; RV32I-NEXT: addi a4, a4, 1818
+; RV32I-NEXT: bge a4, a3, .LBB9_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: sra a2, a0, a1
+; RV32I-NEXT: .LBB9_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_ashr:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.blti a3, 10011, .LBB9_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: sra a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB9_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %d, 10011
+ %ashri = ashr i32 %a, %b
+ %sel = select i1 %x, i32 %ashri, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_xor(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_xor:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a4, 2
+; RV32I-NEXT: addi a4, a4, 1818
+; RV32I-NEXT: bge a4, a3, .LBB10_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: xor a2, a0, a1
+; RV32I-NEXT: .LBB10_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_xor:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.blti a3, 10011, .LBB10_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: xor a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB10_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %d, 10011
+ %xori = xor i32 %a, %b
+ %sel = select i1 %x, i32 %xori, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_and(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_and:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a4, 2
+; RV32I-NEXT: addi a4, a4, 1818
+; RV32I-NEXT: bge a4, a3, .LBB11_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: and a2, a0, a1
+; RV32I-NEXT: .LBB11_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_and:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.blti a3, 10011, .LBB11_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: and a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB11_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %d, 10011
+ %andi = and i32 %a, %b
+ %sel = select i1 %x, i32 %andi, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_or(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_or:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a4, 2
+; RV32I-NEXT: addi a4, a4, 1818
+; RV32I-NEXT: bge a4, a3, .LBB12_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: or a2, a0, a1
+; RV32I-NEXT: .LBB12_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_or:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.blti a3, 10011, .LBB12_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: or a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB12_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %d, 10011
+ %ori = or i32 %a, %b
+ %sel = select i1 %x, i32 %ori, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_addi(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_addi:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1818
+; RV32I-NEXT: bge a1, a3, .LBB13_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: addi a2, a0, 11
+; RV32I-NEXT: .LBB13_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_addi:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.blti a3, 10011, .LBB13_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: addi a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB13_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %d, 10011
+ %addi = add i32 %a, 11
+ %sel = select i1 %x, i32 %addi, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_xori(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_xori:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1818
+; RV32I-NEXT: bge a1, a3, .LBB14_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: xori a2, a0, 11
+; RV32I-NEXT: .LBB14_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_xori:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.blti a3, 10011, .LBB14_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: xori a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB14_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %d, 10011
+ %xori = xor i32 %a, 11
+ %sel = select i1 %x, i32 %xori, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_shli(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_shli:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1818
+; RV32I-NEXT: bge a1, a3, .LBB15_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: slli a2, a0, 11
+; RV32I-NEXT: .LBB15_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_shli:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.blti a3, 10011, .LBB15_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: slli a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB15_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %d, 10011
+ %shli = shl i32 %a, 11
+ %sel = select i1 %x, i32 %shli, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_lshri(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_lshri:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1818
+; RV32I-NEXT: bge a1, a3, .LBB16_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: srli a2, a0, 11
+; RV32I-NEXT: .LBB16_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lshri:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.blti a3, 10011, .LBB16_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: srli a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB16_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %d, 10011
+ %lshri = lshr i32 %a, 11
+ %sel = select i1 %x, i32 %lshri, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_ashri(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_ashri:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1818
+; RV32I-NEXT: bge a1, a3, .LBB17_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: srai a2, a0, 11
+; RV32I-NEXT: .LBB17_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_ashri:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.blti a3, 10011, .LBB17_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: srai a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB17_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %d, 10011
+ %ashri = ashr i32 %a, 11
+ %sel = select i1 %x, i32 %ashri, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_andi(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_andi:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1818
+; RV32I-NEXT: bge a1, a3, .LBB18_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: andi a2, a0, 11
+; RV32I-NEXT: .LBB18_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_andi:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.blti a3, 10011, .LBB18_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: andi a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB18_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %d, 10011
+ %andi = and i32 %a, 11
+ %sel = select i1 %x, i32 %andi, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_ori(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_ori:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1818
+; RV32I-NEXT: bge a1, a3, .LBB19_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: ori a2, a0, 11
+; RV32I-NEXT: .LBB19_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_ori:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.blti a3, 10011, .LBB19_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ori a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB19_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %d, 10011
+ %ori = or i32 %a, 11
+ %sel = select i1 %x, i32 %ori, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_mul(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_mul:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: .cfi_def_cfa_offset 16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: .cfi_offset ra, -4
+; RV32I-NEXT: .cfi_offset s0, -8
+; RV32I-NEXT: .cfi_offset s1, -12
+; RV32I-NEXT: mv s1, a3
+; RV32I-NEXT: mv s0, a2
+; RV32I-NEXT: call __mulsi3
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1818
+; RV32I-NEXT: blt a1, s1, .LBB20_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: .LBB20_2: # %entry
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: .cfi_restore ra
+; RV32I-NEXT: .cfi_restore s0
+; RV32I-NEXT: .cfi_restore s1
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: .cfi_def_cfa_offset 0
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mul:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.blti a3, 10011, .LBB20_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mul a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB20_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %d, 10011
+ %muli = mul i32 %a, %b
+ %sel = select i1 %x, i32 %muli, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_li(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_li:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a0, 2
+; RV32I-NEXT: addi a3, a0, 1818
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: bge a3, a2, .LBB21_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: lui a0, 16
+; RV32I-NEXT: addi a0, a0, 7
+; RV32I-NEXT: .LBB21_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_li:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.blti a2, 10011, .LBB21_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.li a0, 65543
+; RV32I-SFB-WITH-IMM-NEXT: .LBB21_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %d, 10011
+ %sel = select i1 %x, i32 65543, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_qc_e_li(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_qc_e_li:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a0, 2
+; RV32I-NEXT: addi a3, a0, 1818
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: bge a3, a2, .LBB22_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: lui a0, 1025
+; RV32I-NEXT: addi a0, a0, 528
+; RV32I-NEXT: .LBB22_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_qc_e_li:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.blti a2, 10011, .LBB22_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.li a0, 4198928
+; RV32I-SFB-WITH-IMM-NEXT: .LBB22_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %d, 10011
+ %sel = select i1 %x, i32 4198928, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_lui(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_lui:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a0, 2
+; RV32I-NEXT: addi a3, a0, 1818
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: bge a3, a2, .LBB23_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: lui a0, 16
+; RV32I-NEXT: .LBB23_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lui:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.blti a2, 10011, .LBB23_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lui a0, 16
+; RV32I-SFB-WITH-IMM-NEXT: .LBB23_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %d, 10011
+ %sel = select i1 %x, i32 65536, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_lb(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lb:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a3, a3, 1818
+; RV32I-NEXT: bge a3, a1, .LBB24_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lb a2, 4(a0)
+; RV32I-NEXT: .LBB24_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lb:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.blti a1, 10011, .LBB24_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lb a2, 4(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB24_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %a, 10011
+ %addr = getelementptr i8, ptr %base, i32 4 ; compute base + 4
+ %val = load i8, ptr %addr ; load 8-bit value
+ %ext = sext i8 %val to i32 ; sign-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lbu(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lbu:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a3, a3, 1818
+; RV32I-NEXT: bge a3, a1, .LBB25_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lbu a2, 4(a0)
+; RV32I-NEXT: .LBB25_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lbu:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.blti a1, 10011, .LBB25_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lbu a2, 4(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB25_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %a, 10011
+ %addr = getelementptr i8, ptr %base, i32 4 ; compute base + 4
+ %val = load i8, ptr %addr ; load 8-bit value
+ %ext = zext i8 %val to i32 ; zero-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lh(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lh:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a3, a3, 1818
+; RV32I-NEXT: bge a3, a1, .LBB26_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lh a2, 8(a0)
+; RV32I-NEXT: .LBB26_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lh:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.blti a1, 10011, .LBB26_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lh a2, 8(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB26_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %a, 10011
+ %addr = getelementptr i16, ptr %base, i32 4 ; compute base + 4
+ %val = load i16, ptr %addr ; load 16-bit value
+ %ext = sext i16 %val to i32 ; sign-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lhu(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lhu:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a3, a3, 1818
+; RV32I-NEXT: bge a3, a1, .LBB27_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lhu a2, 8(a0)
+; RV32I-NEXT: .LBB27_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lhu:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.blti a1, 10011, .LBB27_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lhu a2, 8(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB27_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %a, 10011
+ %addr = getelementptr i16, ptr %base, i32 4 ; compute base + 4
+ %val = load i16, ptr %addr ; load 16-bit value
+ %ext = zext i16 %val to i32 ; zero-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lw(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lw:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a3, a3, 1818
+; RV32I-NEXT: bge a3, a1, .LBB28_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lw a2, 16(a0)
+; RV32I-NEXT: .LBB28_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lw:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.blti a1, 10011, .LBB28_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lw a2, 16(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB28_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %a, 10011
+ %addr = getelementptr i32, ptr %base, i32 4 ; compute base + 4
+ %val = load i32, ptr %addr ; load 32-bit value
+ %res = select i1 %x, i32 %val, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lb_qc_e(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lb_qc_e:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a4, a3, 1818
+; RV32I-NEXT: bge a4, a1, .LBB29_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: add a0, a0, a3
+; RV32I-NEXT: lb a2, 1808(a0)
+; RV32I-NEXT: .LBB29_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lb_qc_e:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.blti a1, 10011, .LBB29_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.lb a2, 10000(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB29_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %a, 10011
+ %addr = getelementptr i8, ptr %base, i32 10000 ; compute base + 10000
+ %val = load i8, ptr %addr ; load 8-bit value
+ %ext = sext i8 %val to i32 ; sign-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lbu_qc_e(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lbu_qc_e:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a4, a3, 1818
+; RV32I-NEXT: bge a4, a1, .LBB30_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: add a0, a0, a3
+; RV32I-NEXT: lbu a2, 1808(a0)
+; RV32I-NEXT: .LBB30_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lbu_qc_e:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.blti a1, 10011, .LBB30_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.lbu a2, 10000(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB30_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %a, 10011
+ %addr = getelementptr i8, ptr %base, i32 10000 ; compute base + 10000
+ %val = load i8, ptr %addr ; load 8-bit value
+ %ext = zext i8 %val to i32 ; zero-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lh_qc_e(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lh_qc_e:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a3, a3, 1818
+; RV32I-NEXT: bge a3, a1, .LBB31_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lui a1, 5
+; RV32I-NEXT: add a0, a0, a1
+; RV32I-NEXT: lh a2, -480(a0)
+; RV32I-NEXT: .LBB31_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lh_qc_e:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.blti a1, 10011, .LBB31_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.lh a2, 20000(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB31_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %a, 10011
+ %addr = getelementptr i16, ptr %base, i32 10000 ; compute base + 10000
+ %val = load i16, ptr %addr ; load 16-bit value
+ %ext = sext i16 %val to i32 ; sign-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lhu_qc_e(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lhu_qc_e:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a3, a3, 1818
+; RV32I-NEXT: bge a3, a1, .LBB32_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lui a1, 5
+; RV32I-NEXT: add a0, a0, a1
+; RV32I-NEXT: lhu a2, -480(a0)
+; RV32I-NEXT: .LBB32_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lhu_qc_e:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.blti a1, 10011, .LBB32_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.lhu a2, 20000(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB32_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %a, 10011
+ %addr = getelementptr i16, ptr %base, i32 10000 ; compute base + 10000
+ %val = load i16, ptr %addr ; load 16-bit value
+ %ext = zext i16 %val to i32 ; zero-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lw_qc_e(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lw_qc_e:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a3, a3, 1818
+; RV32I-NEXT: bge a3, a1, .LBB33_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lui a1, 10
+; RV32I-NEXT: add a0, a0, a1
+; RV32I-NEXT: lw a2, -960(a0)
+; RV32I-NEXT: .LBB33_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lw_qc_e:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.blti a1, 10011, .LBB33_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.lw a2, 40000(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB33_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp sge i32 %a, 10011
+ %addr = getelementptr i32, ptr %base, i32 10000 ; compute base + 10000
+ %val = load i32, ptr %addr ; load 32-bit value
+ %res = select i1 %x, i32 %val, i32 %b
+ ret i32 %res
+}
diff --git a/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_48_slt.ll b/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_48_slt.ll
new file mode 100644
index 0000000000000..f1ba557e59f93
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_48_slt.ll
@@ -0,0 +1,948 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 | FileCheck %s --check-prefixes=RV32I
+; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 -mattr=+xqci,+short-forward-branch-ialu,+short-forward-branch-imul,+short-forward-branch-iload,+short-forward-branch-imm,+m | \
+; RUN: FileCheck %s --check-prefixes=RV32I-SFB-WITH-IMM
+
+define i32 @branch_with_immSFB_mv(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_mv:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a3, a3, 1819
+; RV32I-NEXT: blt a2, a3, .LBB0_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: .LBB0_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mv:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.blti a2, 10011, .LBB0_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB0_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %d, 10011
+ %sel = select i1 %x, i32 %a, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_mv_zerofalsev(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_mv_zerofalsev:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1819
+; RV32I-NEXT: slt a1, a2, a1
+; RV32I-NEXT: neg a1, a1
+; RV32I-NEXT: and a0, a1, a0
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mv_zerofalsev:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.blti a2, 10011, .LBB1_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: li a0, 0
+; RV32I-SFB-WITH-IMM-NEXT: .LBB1_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %d, 10011
+ %sel = select i1 %x, i32 %a, i32 0
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_mv_zerofalsev_swapped(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_mv_zerofalsev_swapped:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1819
+; RV32I-NEXT: slt a1, a2, a1
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: and a0, a1, a0
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mv_zerofalsev_swapped:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgei a2, 10011, .LBB2_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: li a0, 0
+; RV32I-SFB-WITH-IMM-NEXT: .LBB2_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %d, 10011
+ %sel = select i1 %x, i32 0, i32 %a
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_mv_minusOnefalsev(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_mv_minusOnefalsev:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1819
+; RV32I-NEXT: slt a1, a2, a1
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: or a0, a1, a0
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mv_minusOnefalsev:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: li a1, -1
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.blti a2, 10011, .LBB3_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB3_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %d, 10011
+ %sel = select i1 %x, i32 %a, i32 -1
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_mv_minusOnefalsev_swapped(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_mv_minusOnefalsev_swapped:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1819
+; RV32I-NEXT: slt a1, a2, a1
+; RV32I-NEXT: neg a1, a1
+; RV32I-NEXT: or a0, a1, a0
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mv_minusOnefalsev_swapped:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: li a1, -1
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgei a2, 10011, .LBB4_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB4_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %d, 10011
+ %sel = select i1 %x, i32 -1, i32 %a
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_add(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_add:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a4, 2
+; RV32I-NEXT: addi a4, a4, 1819
+; RV32I-NEXT: bge a3, a4, .LBB5_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: add a2, a0, a1
+; RV32I-NEXT: .LBB5_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_add:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgei a3, 10011, .LBB5_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: add a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB5_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %d, 10011
+ %addi = add i32 %a, %b
+ %sel = select i1 %x, i32 %addi, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_sub(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_sub:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a4, 2
+; RV32I-NEXT: addi a4, a4, 1819
+; RV32I-NEXT: bge a3, a4, .LBB6_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: sub a2, a0, a1
+; RV32I-NEXT: .LBB6_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_sub:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgei a3, 10011, .LBB6_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: sub a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB6_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %d, 10011
+ %subi = sub i32 %a, %b
+ %sel = select i1 %x, i32 %subi, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_shl(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_shl:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a4, 2
+; RV32I-NEXT: addi a4, a4, 1819
+; RV32I-NEXT: bge a3, a4, .LBB7_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: sll a2, a0, a1
+; RV32I-NEXT: .LBB7_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_shl:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgei a3, 10011, .LBB7_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: sll a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB7_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %d, 10011
+ %shli = shl i32 %a, %b
+ %sel = select i1 %x, i32 %shli, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_lshr(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_lshr:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a4, 2
+; RV32I-NEXT: addi a4, a4, 1819
+; RV32I-NEXT: bge a3, a4, .LBB8_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: srl a2, a0, a1
+; RV32I-NEXT: .LBB8_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lshr:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgei a3, 10011, .LBB8_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: srl a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB8_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %d, 10011
+ %lshri = lshr i32 %a, %b
+ %sel = select i1 %x, i32 %lshri, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_ashr(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_ashr:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a4, 2
+; RV32I-NEXT: addi a4, a4, 1819
+; RV32I-NEXT: bge a3, a4, .LBB9_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: sra a2, a0, a1
+; RV32I-NEXT: .LBB9_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_ashr:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgei a3, 10011, .LBB9_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: sra a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB9_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %d, 10011
+ %ashri = ashr i32 %a, %b
+ %sel = select i1 %x, i32 %ashri, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_xor(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_xor:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a4, 2
+; RV32I-NEXT: addi a4, a4, 1819
+; RV32I-NEXT: bge a3, a4, .LBB10_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: xor a2, a0, a1
+; RV32I-NEXT: .LBB10_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_xor:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgei a3, 10011, .LBB10_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: xor a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB10_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %d, 10011
+ %xori = xor i32 %a, %b
+ %sel = select i1 %x, i32 %xori, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_and(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_and:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a4, 2
+; RV32I-NEXT: addi a4, a4, 1819
+; RV32I-NEXT: bge a3, a4, .LBB11_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: and a2, a0, a1
+; RV32I-NEXT: .LBB11_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_and:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgei a3, 10011, .LBB11_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: and a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB11_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %d, 10011
+ %andi = and i32 %a, %b
+ %sel = select i1 %x, i32 %andi, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_or(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_or:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a4, 2
+; RV32I-NEXT: addi a4, a4, 1819
+; RV32I-NEXT: bge a3, a4, .LBB12_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: or a2, a0, a1
+; RV32I-NEXT: .LBB12_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_or:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgei a3, 10011, .LBB12_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: or a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB12_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %d, 10011
+ %ori = or i32 %a, %b
+ %sel = select i1 %x, i32 %ori, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_addi(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_addi:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1819
+; RV32I-NEXT: bge a3, a1, .LBB13_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: addi a2, a0, 11
+; RV32I-NEXT: .LBB13_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_addi:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgei a3, 10011, .LBB13_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: addi a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB13_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %d, 10011
+ %addi = add i32 %a, 11
+ %sel = select i1 %x, i32 %addi, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_xori(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_xori:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1819
+; RV32I-NEXT: bge a3, a1, .LBB14_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: xori a2, a0, 11
+; RV32I-NEXT: .LBB14_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_xori:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgei a3, 10011, .LBB14_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: xori a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB14_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %d, 10011
+ %xori = xor i32 %a, 11
+ %sel = select i1 %x, i32 %xori, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_shli(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_shli:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1819
+; RV32I-NEXT: bge a3, a1, .LBB15_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: slli a2, a0, 11
+; RV32I-NEXT: .LBB15_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_shli:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgei a3, 10011, .LBB15_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: slli a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB15_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %d, 10011
+ %shli = shl i32 %a, 11
+ %sel = select i1 %x, i32 %shli, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_lshri(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_lshri:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1819
+; RV32I-NEXT: bge a3, a1, .LBB16_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: srli a2, a0, 11
+; RV32I-NEXT: .LBB16_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lshri:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgei a3, 10011, .LBB16_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: srli a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB16_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %d, 10011
+ %lshri = lshr i32 %a, 11
+ %sel = select i1 %x, i32 %lshri, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_ashri(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_ashri:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1819
+; RV32I-NEXT: bge a3, a1, .LBB17_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: srai a2, a0, 11
+; RV32I-NEXT: .LBB17_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_ashri:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgei a3, 10011, .LBB17_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: srai a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB17_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %d, 10011
+ %ashri = ashr i32 %a, 11
+ %sel = select i1 %x, i32 %ashri, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_andi(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_andi:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1819
+; RV32I-NEXT: bge a3, a1, .LBB18_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: andi a2, a0, 11
+; RV32I-NEXT: .LBB18_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_andi:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgei a3, 10011, .LBB18_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: andi a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB18_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %d, 10011
+ %andi = and i32 %a, 11
+ %sel = select i1 %x, i32 %andi, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_ori(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_ori:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1819
+; RV32I-NEXT: bge a3, a1, .LBB19_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: ori a2, a0, 11
+; RV32I-NEXT: .LBB19_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_ori:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgei a3, 10011, .LBB19_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ori a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB19_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %d, 10011
+ %ori = or i32 %a, 11
+ %sel = select i1 %x, i32 %ori, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_mul(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_mul:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: .cfi_def_cfa_offset 16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: .cfi_offset ra, -4
+; RV32I-NEXT: .cfi_offset s0, -8
+; RV32I-NEXT: .cfi_offset s1, -12
+; RV32I-NEXT: mv s1, a3
+; RV32I-NEXT: mv s0, a2
+; RV32I-NEXT: call __mulsi3
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1819
+; RV32I-NEXT: blt s1, a1, .LBB20_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: .LBB20_2: # %entry
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: .cfi_restore ra
+; RV32I-NEXT: .cfi_restore s0
+; RV32I-NEXT: .cfi_restore s1
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: .cfi_def_cfa_offset 0
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mul:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgei a3, 10011, .LBB20_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mul a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB20_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %d, 10011
+ %muli = mul i32 %a, %b
+ %sel = select i1 %x, i32 %muli, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_li(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_li:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a0, 2
+; RV32I-NEXT: addi a3, a0, 1819
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: bge a2, a3, .LBB21_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: lui a0, 16
+; RV32I-NEXT: addi a0, a0, 7
+; RV32I-NEXT: .LBB21_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_li:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgei a2, 10011, .LBB21_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.li a0, 65543
+; RV32I-SFB-WITH-IMM-NEXT: .LBB21_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %d, 10011
+ %sel = select i1 %x, i32 65543, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_qc_e_li(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_qc_e_li:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a0, 2
+; RV32I-NEXT: addi a3, a0, 1819
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: bge a2, a3, .LBB22_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: lui a0, 1025
+; RV32I-NEXT: addi a0, a0, 528
+; RV32I-NEXT: .LBB22_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_qc_e_li:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgei a2, 10011, .LBB22_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.li a0, 4198928
+; RV32I-SFB-WITH-IMM-NEXT: .LBB22_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %d, 10011
+ %sel = select i1 %x, i32 4198928, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_lui(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_lui:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a0, 2
+; RV32I-NEXT: addi a3, a0, 1819
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: bge a2, a3, .LBB23_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: lui a0, 16
+; RV32I-NEXT: .LBB23_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lui:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgei a2, 10011, .LBB23_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lui a0, 16
+; RV32I-SFB-WITH-IMM-NEXT: .LBB23_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %d, 10011
+ %sel = select i1 %x, i32 65536, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_lb(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lb:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a3, a3, 1819
+; RV32I-NEXT: bge a1, a3, .LBB24_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lb a2, 4(a0)
+; RV32I-NEXT: .LBB24_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lb:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgei a1, 10011, .LBB24_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lb a2, 4(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB24_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %a, 10011
+ %addr = getelementptr i8, ptr %base, i32 4 ; compute base + 4
+ %val = load i8, ptr %addr ; load 8-bit value
+ %ext = sext i8 %val to i32 ; sign-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lbu(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lbu:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a3, a3, 1819
+; RV32I-NEXT: bge a1, a3, .LBB25_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lbu a2, 4(a0)
+; RV32I-NEXT: .LBB25_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lbu:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgei a1, 10011, .LBB25_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lbu a2, 4(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB25_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %a, 10011
+ %addr = getelementptr i8, ptr %base, i32 4 ; compute base + 4
+ %val = load i8, ptr %addr ; load 8-bit value
+ %ext = zext i8 %val to i32 ; zero-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lh(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lh:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a3, a3, 1819
+; RV32I-NEXT: bge a1, a3, .LBB26_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lh a2, 8(a0)
+; RV32I-NEXT: .LBB26_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lh:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgei a1, 10011, .LBB26_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lh a2, 8(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB26_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %a, 10011
+ %addr = getelementptr i16, ptr %base, i32 4 ; compute base + 4
+ %val = load i16, ptr %addr ; load 16-bit value
+ %ext = sext i16 %val to i32 ; sign-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lhu(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lhu:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a3, a3, 1819
+; RV32I-NEXT: bge a1, a3, .LBB27_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lhu a2, 8(a0)
+; RV32I-NEXT: .LBB27_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lhu:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgei a1, 10011, .LBB27_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lhu a2, 8(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB27_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %a, 10011
+ %addr = getelementptr i16, ptr %base, i32 4 ; compute base + 4
+ %val = load i16, ptr %addr ; load 16-bit value
+ %ext = zext i16 %val to i32 ; zero-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lw(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lw:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a3, a3, 1819
+; RV32I-NEXT: bge a1, a3, .LBB28_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lw a2, 16(a0)
+; RV32I-NEXT: .LBB28_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lw:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgei a1, 10011, .LBB28_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lw a2, 16(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB28_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %a, 10011
+ %addr = getelementptr i32, ptr %base, i32 4 ; compute base + 4
+ %val = load i32, ptr %addr ; load 32-bit value
+ %res = select i1 %x, i32 %val, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lb_qc_e(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lb_qc_e:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a4, a3, 1819
+; RV32I-NEXT: bge a1, a4, .LBB29_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: add a0, a0, a3
+; RV32I-NEXT: lb a2, 1808(a0)
+; RV32I-NEXT: .LBB29_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lb_qc_e:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgei a1, 10011, .LBB29_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.lb a2, 10000(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB29_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %a, 10011
+ %addr = getelementptr i8, ptr %base, i32 10000 ; compute base + 10000
+ %val = load i8, ptr %addr ; load 8-bit value
+ %ext = sext i8 %val to i32 ; sign-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lbu_qc_e(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lbu_qc_e:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a4, a3, 1819
+; RV32I-NEXT: bge a1, a4, .LBB30_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: add a0, a0, a3
+; RV32I-NEXT: lbu a2, 1808(a0)
+; RV32I-NEXT: .LBB30_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lbu_qc_e:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgei a1, 10011, .LBB30_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.lbu a2, 10000(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB30_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %a, 10011
+ %addr = getelementptr i8, ptr %base, i32 10000 ; compute base + 10000
+ %val = load i8, ptr %addr ; load 8-bit value
+ %ext = zext i8 %val to i32 ; zero-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lh_qc_e(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lh_qc_e:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a3, a3, 1819
+; RV32I-NEXT: bge a1, a3, .LBB31_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lui a1, 5
+; RV32I-NEXT: add a0, a0, a1
+; RV32I-NEXT: lh a2, -480(a0)
+; RV32I-NEXT: .LBB31_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lh_qc_e:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgei a1, 10011, .LBB31_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.lh a2, 20000(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB31_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %a, 10011
+ %addr = getelementptr i16, ptr %base, i32 10000 ; compute base + 10000
+ %val = load i16, ptr %addr ; load 16-bit value
+ %ext = sext i16 %val to i32 ; sign-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lhu_qc_e(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lhu_qc_e:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a3, a3, 1819
+; RV32I-NEXT: bge a1, a3, .LBB32_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lui a1, 5
+; RV32I-NEXT: add a0, a0, a1
+; RV32I-NEXT: lhu a2, -480(a0)
+; RV32I-NEXT: .LBB32_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lhu_qc_e:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgei a1, 10011, .LBB32_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.lhu a2, 20000(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB32_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %a, 10011
+ %addr = getelementptr i16, ptr %base, i32 10000 ; compute base + 10000
+ %val = load i16, ptr %addr ; load 16-bit value
+ %ext = zext i16 %val to i32 ; zero-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lw_qc_e(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lw_qc_e:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a3, a3, 1819
+; RV32I-NEXT: bge a1, a3, .LBB33_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lui a1, 10
+; RV32I-NEXT: add a0, a0, a1
+; RV32I-NEXT: lw a2, -960(a0)
+; RV32I-NEXT: .LBB33_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lw_qc_e:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgei a1, 10011, .LBB33_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.lw a2, 40000(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB33_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp slt i32 %a, 10011
+ %addr = getelementptr i32, ptr %base, i32 10000 ; compute base + 10000
+ %val = load i32, ptr %addr ; load 32-bit value
+ %res = select i1 %x, i32 %val, i32 %b
+ ret i32 %res
+}
diff --git a/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_48_uge.ll b/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_48_uge.ll
new file mode 100644
index 0000000000000..37baf90890edf
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_48_uge.ll
@@ -0,0 +1,948 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 | FileCheck %s --check-prefixes=RV32I
+; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 -mattr=+xqci,+short-forward-branch-ialu,+short-forward-branch-imul,+short-forward-branch-iload,+short-forward-branch-imm,+m | \
+; RUN: FileCheck %s --check-prefixes=RV32I-SFB-WITH-IMM
+
+define i32 @branch_with_immSFB_mv(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_mv:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a3, a3, 1818
+; RV32I-NEXT: bltu a3, a2, .LBB0_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: .LBB0_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mv:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgeui a2, 10011, .LBB0_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB0_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %d, 10011
+ %sel = select i1 %x, i32 %a, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_mv_zerofalsev(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_mv_zerofalsev:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1818
+; RV32I-NEXT: sltu a1, a1, a2
+; RV32I-NEXT: neg a1, a1
+; RV32I-NEXT: and a0, a1, a0
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mv_zerofalsev:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgeui a2, 10011, .LBB1_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: li a0, 0
+; RV32I-SFB-WITH-IMM-NEXT: .LBB1_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %d, 10011
+ %sel = select i1 %x, i32 %a, i32 0
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_mv_zerofalsev_swapped(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_mv_zerofalsev_swapped:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1818
+; RV32I-NEXT: sltu a1, a1, a2
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: and a0, a1, a0
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mv_zerofalsev_swapped:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bltui a2, 10011, .LBB2_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: li a0, 0
+; RV32I-SFB-WITH-IMM-NEXT: .LBB2_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %d, 10011
+ %sel = select i1 %x, i32 0, i32 %a
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_mv_minusOnefalsev(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_mv_minusOnefalsev:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1818
+; RV32I-NEXT: sltu a1, a1, a2
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: or a0, a1, a0
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mv_minusOnefalsev:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: li a1, -1
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgeui a2, 10011, .LBB3_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB3_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %d, 10011
+ %sel = select i1 %x, i32 %a, i32 -1
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_mv_minusOnefalsev_swapped(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_mv_minusOnefalsev_swapped:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1818
+; RV32I-NEXT: sltu a1, a1, a2
+; RV32I-NEXT: neg a1, a1
+; RV32I-NEXT: or a0, a1, a0
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mv_minusOnefalsev_swapped:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: li a1, -1
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bltui a2, 10011, .LBB4_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB4_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %d, 10011
+ %sel = select i1 %x, i32 -1, i32 %a
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_add(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_add:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a4, 2
+; RV32I-NEXT: addi a4, a4, 1818
+; RV32I-NEXT: bgeu a4, a3, .LBB5_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: add a2, a0, a1
+; RV32I-NEXT: .LBB5_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_add:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bltui a3, 10011, .LBB5_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: add a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB5_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %d, 10011
+ %addi = add i32 %a, %b
+ %sel = select i1 %x, i32 %addi, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_sub(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_sub:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a4, 2
+; RV32I-NEXT: addi a4, a4, 1818
+; RV32I-NEXT: bgeu a4, a3, .LBB6_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: sub a2, a0, a1
+; RV32I-NEXT: .LBB6_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_sub:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bltui a3, 10011, .LBB6_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: sub a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB6_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %d, 10011
+ %subi = sub i32 %a, %b
+ %sel = select i1 %x, i32 %subi, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_shl(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_shl:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a4, 2
+; RV32I-NEXT: addi a4, a4, 1818
+; RV32I-NEXT: bgeu a4, a3, .LBB7_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: sll a2, a0, a1
+; RV32I-NEXT: .LBB7_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_shl:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bltui a3, 10011, .LBB7_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: sll a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB7_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %d, 10011
+ %shli = shl i32 %a, %b
+ %sel = select i1 %x, i32 %shli, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_lshr(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_lshr:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a4, 2
+; RV32I-NEXT: addi a4, a4, 1818
+; RV32I-NEXT: bgeu a4, a3, .LBB8_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: srl a2, a0, a1
+; RV32I-NEXT: .LBB8_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lshr:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bltui a3, 10011, .LBB8_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: srl a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB8_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %d, 10011
+ %lshri = lshr i32 %a, %b
+ %sel = select i1 %x, i32 %lshri, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_ashr(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_ashr:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a4, 2
+; RV32I-NEXT: addi a4, a4, 1818
+; RV32I-NEXT: bgeu a4, a3, .LBB9_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: sra a2, a0, a1
+; RV32I-NEXT: .LBB9_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_ashr:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bltui a3, 10011, .LBB9_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: sra a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB9_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %d, 10011
+ %ashri = ashr i32 %a, %b
+ %sel = select i1 %x, i32 %ashri, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_xor(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_xor:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a4, 2
+; RV32I-NEXT: addi a4, a4, 1818
+; RV32I-NEXT: bgeu a4, a3, .LBB10_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: xor a2, a0, a1
+; RV32I-NEXT: .LBB10_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_xor:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bltui a3, 10011, .LBB10_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: xor a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB10_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %d, 10011
+ %xori = xor i32 %a, %b
+ %sel = select i1 %x, i32 %xori, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_and(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_and:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a4, 2
+; RV32I-NEXT: addi a4, a4, 1818
+; RV32I-NEXT: bgeu a4, a3, .LBB11_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: and a2, a0, a1
+; RV32I-NEXT: .LBB11_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_and:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bltui a3, 10011, .LBB11_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: and a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB11_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %d, 10011
+ %andi = and i32 %a, %b
+ %sel = select i1 %x, i32 %andi, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_or(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_or:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a4, 2
+; RV32I-NEXT: addi a4, a4, 1818
+; RV32I-NEXT: bgeu a4, a3, .LBB12_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: or a2, a0, a1
+; RV32I-NEXT: .LBB12_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_or:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bltui a3, 10011, .LBB12_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: or a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB12_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %d, 10011
+ %ori = or i32 %a, %b
+ %sel = select i1 %x, i32 %ori, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_addi(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_addi:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1818
+; RV32I-NEXT: bgeu a1, a3, .LBB13_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: addi a2, a0, 11
+; RV32I-NEXT: .LBB13_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_addi:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bltui a3, 10011, .LBB13_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: addi a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB13_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %d, 10011
+ %addi = add i32 %a, 11
+ %sel = select i1 %x, i32 %addi, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_xori(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_xori:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1818
+; RV32I-NEXT: bgeu a1, a3, .LBB14_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: xori a2, a0, 11
+; RV32I-NEXT: .LBB14_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_xori:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bltui a3, 10011, .LBB14_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: xori a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB14_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %d, 10011
+ %xori = xor i32 %a, 11
+ %sel = select i1 %x, i32 %xori, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_shli(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_shli:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1818
+; RV32I-NEXT: bgeu a1, a3, .LBB15_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: slli a2, a0, 11
+; RV32I-NEXT: .LBB15_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_shli:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bltui a3, 10011, .LBB15_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: slli a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB15_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %d, 10011
+ %shli = shl i32 %a, 11
+ %sel = select i1 %x, i32 %shli, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_lshri(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_lshri:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1818
+; RV32I-NEXT: bgeu a1, a3, .LBB16_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: srli a2, a0, 11
+; RV32I-NEXT: .LBB16_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lshri:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bltui a3, 10011, .LBB16_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: srli a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB16_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %d, 10011
+ %lshri = lshr i32 %a, 11
+ %sel = select i1 %x, i32 %lshri, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_ashri(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_ashri:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1818
+; RV32I-NEXT: bgeu a1, a3, .LBB17_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: srai a2, a0, 11
+; RV32I-NEXT: .LBB17_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_ashri:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bltui a3, 10011, .LBB17_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: srai a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB17_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %d, 10011
+ %ashri = ashr i32 %a, 11
+ %sel = select i1 %x, i32 %ashri, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_andi(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_andi:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1818
+; RV32I-NEXT: bgeu a1, a3, .LBB18_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: andi a2, a0, 11
+; RV32I-NEXT: .LBB18_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_andi:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bltui a3, 10011, .LBB18_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: andi a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB18_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %d, 10011
+ %andi = and i32 %a, 11
+ %sel = select i1 %x, i32 %andi, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_ori(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_ori:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1818
+; RV32I-NEXT: bgeu a1, a3, .LBB19_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: ori a2, a0, 11
+; RV32I-NEXT: .LBB19_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_ori:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bltui a3, 10011, .LBB19_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ori a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB19_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %d, 10011
+ %ori = or i32 %a, 11
+ %sel = select i1 %x, i32 %ori, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_mul(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_mul:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: .cfi_def_cfa_offset 16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: .cfi_offset ra, -4
+; RV32I-NEXT: .cfi_offset s0, -8
+; RV32I-NEXT: .cfi_offset s1, -12
+; RV32I-NEXT: mv s1, a3
+; RV32I-NEXT: mv s0, a2
+; RV32I-NEXT: call __mulsi3
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1818
+; RV32I-NEXT: bltu a1, s1, .LBB20_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: .LBB20_2: # %entry
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: .cfi_restore ra
+; RV32I-NEXT: .cfi_restore s0
+; RV32I-NEXT: .cfi_restore s1
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: .cfi_def_cfa_offset 0
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mul:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bltui a3, 10011, .LBB20_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mul a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB20_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %d, 10011
+ %muli = mul i32 %a, %b
+ %sel = select i1 %x, i32 %muli, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_li(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_li:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a0, 2
+; RV32I-NEXT: addi a3, a0, 1818
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: bgeu a3, a2, .LBB21_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: lui a0, 16
+; RV32I-NEXT: addi a0, a0, 7
+; RV32I-NEXT: .LBB21_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_li:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bltui a2, 10011, .LBB21_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.li a0, 65543
+; RV32I-SFB-WITH-IMM-NEXT: .LBB21_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %d, 10011
+ %sel = select i1 %x, i32 65543, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_qc_e_li(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_qc_e_li:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a0, 2
+; RV32I-NEXT: addi a3, a0, 1818
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: bgeu a3, a2, .LBB22_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: lui a0, 1025
+; RV32I-NEXT: addi a0, a0, 528
+; RV32I-NEXT: .LBB22_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_qc_e_li:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bltui a2, 10011, .LBB22_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.li a0, 4198928
+; RV32I-SFB-WITH-IMM-NEXT: .LBB22_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %d, 10011
+ %sel = select i1 %x, i32 4198928, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_lui(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_lui:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a0, 2
+; RV32I-NEXT: addi a3, a0, 1818
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: bgeu a3, a2, .LBB23_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: lui a0, 16
+; RV32I-NEXT: .LBB23_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lui:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bltui a2, 10011, .LBB23_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lui a0, 16
+; RV32I-SFB-WITH-IMM-NEXT: .LBB23_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %d, 10011
+ %sel = select i1 %x, i32 65536, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_lb(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lb:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a3, a3, 1818
+; RV32I-NEXT: bgeu a3, a1, .LBB24_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lb a2, 4(a0)
+; RV32I-NEXT: .LBB24_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lb:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bltui a1, 10011, .LBB24_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lb a2, 4(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB24_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %a, 10011
+ %addr = getelementptr i8, ptr %base, i32 4 ; compute base + 4
+ %val = load i8, ptr %addr ; load 8-bit value
+ %ext = sext i8 %val to i32 ; sign-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lbu(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lbu:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a3, a3, 1818
+; RV32I-NEXT: bgeu a3, a1, .LBB25_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lbu a2, 4(a0)
+; RV32I-NEXT: .LBB25_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lbu:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bltui a1, 10011, .LBB25_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lbu a2, 4(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB25_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %a, 10011
+ %addr = getelementptr i8, ptr %base, i32 4 ; compute base + 4
+ %val = load i8, ptr %addr ; load 8-bit value
+ %ext = zext i8 %val to i32 ; zero-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lh(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lh:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a3, a3, 1818
+; RV32I-NEXT: bgeu a3, a1, .LBB26_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lh a2, 8(a0)
+; RV32I-NEXT: .LBB26_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lh:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bltui a1, 10011, .LBB26_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lh a2, 8(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB26_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %a, 10011
+ %addr = getelementptr i16, ptr %base, i32 4 ; compute base + 4
+ %val = load i16, ptr %addr ; load 16-bit value
+ %ext = sext i16 %val to i32 ; sign-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lhu(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lhu:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a3, a3, 1818
+; RV32I-NEXT: bgeu a3, a1, .LBB27_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lhu a2, 8(a0)
+; RV32I-NEXT: .LBB27_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lhu:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bltui a1, 10011, .LBB27_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lhu a2, 8(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB27_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %a, 10011
+ %addr = getelementptr i16, ptr %base, i32 4 ; compute base + 4
+ %val = load i16, ptr %addr ; load 16-bit value
+ %ext = zext i16 %val to i32 ; zero-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lw(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lw:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a3, a3, 1818
+; RV32I-NEXT: bgeu a3, a1, .LBB28_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lw a2, 16(a0)
+; RV32I-NEXT: .LBB28_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lw:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bltui a1, 10011, .LBB28_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lw a2, 16(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB28_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %a, 10011
+ %addr = getelementptr i32, ptr %base, i32 4 ; compute base + 4
+ %val = load i32, ptr %addr ; load 32-bit value
+ %res = select i1 %x, i32 %val, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lb_qc_e(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lb_qc_e:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a4, a3, 1818
+; RV32I-NEXT: bgeu a4, a1, .LBB29_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: add a0, a0, a3
+; RV32I-NEXT: lb a2, 1808(a0)
+; RV32I-NEXT: .LBB29_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lb_qc_e:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bltui a1, 10011, .LBB29_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.lb a2, 10000(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB29_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %a, 10011
+ %addr = getelementptr i8, ptr %base, i32 10000 ; compute base + 10000
+ %val = load i8, ptr %addr ; load 8-bit value
+ %ext = sext i8 %val to i32 ; sign-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lbu_qc_e(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lbu_qc_e:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a4, a3, 1818
+; RV32I-NEXT: bgeu a4, a1, .LBB30_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: add a0, a0, a3
+; RV32I-NEXT: lbu a2, 1808(a0)
+; RV32I-NEXT: .LBB30_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lbu_qc_e:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bltui a1, 10011, .LBB30_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.lbu a2, 10000(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB30_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %a, 10011
+ %addr = getelementptr i8, ptr %base, i32 10000 ; compute base + 10000
+ %val = load i8, ptr %addr ; load 8-bit value
+ %ext = zext i8 %val to i32 ; zero-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lh_qc_e(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lh_qc_e:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a3, a3, 1818
+; RV32I-NEXT: bgeu a3, a1, .LBB31_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lui a1, 5
+; RV32I-NEXT: add a0, a0, a1
+; RV32I-NEXT: lh a2, -480(a0)
+; RV32I-NEXT: .LBB31_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lh_qc_e:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bltui a1, 10011, .LBB31_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.lh a2, 20000(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB31_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %a, 10011
+ %addr = getelementptr i16, ptr %base, i32 10000 ; compute base + 10000
+ %val = load i16, ptr %addr ; load 16-bit value
+ %ext = sext i16 %val to i32 ; sign-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lhu_qc_e(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lhu_qc_e:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a3, a3, 1818
+; RV32I-NEXT: bgeu a3, a1, .LBB32_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lui a1, 5
+; RV32I-NEXT: add a0, a0, a1
+; RV32I-NEXT: lhu a2, -480(a0)
+; RV32I-NEXT: .LBB32_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lhu_qc_e:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bltui a1, 10011, .LBB32_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.lhu a2, 20000(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB32_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %a, 10011
+ %addr = getelementptr i16, ptr %base, i32 10000 ; compute base + 10000
+ %val = load i16, ptr %addr ; load 16-bit value
+ %ext = zext i16 %val to i32 ; zero-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lw_qc_e(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lw_qc_e:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a3, a3, 1818
+; RV32I-NEXT: bgeu a3, a1, .LBB33_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lui a1, 10
+; RV32I-NEXT: add a0, a0, a1
+; RV32I-NEXT: lw a2, -960(a0)
+; RV32I-NEXT: .LBB33_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lw_qc_e:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bltui a1, 10011, .LBB33_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.lw a2, 40000(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB33_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp uge i32 %a, 10011
+ %addr = getelementptr i32, ptr %base, i32 10000 ; compute base + 10000
+ %val = load i32, ptr %addr ; load 32-bit value
+ %res = select i1 %x, i32 %val, i32 %b
+ ret i32 %res
+}
diff --git a/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_48_ult.ll b/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_48_ult.ll
new file mode 100644
index 0000000000000..12ffa568fdb6c
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_48_ult.ll
@@ -0,0 +1,948 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 | FileCheck %s --check-prefixes=RV32I
+; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 -mattr=+xqci,+short-forward-branch-ialu,+short-forward-branch-imul,+short-forward-branch-iload,+short-forward-branch-imm,+m | \
+; RUN: FileCheck %s --check-prefixes=RV32I-SFB-WITH-IMM
+
+define i32 @branch_with_immSFB_mv(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_mv:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a3, a3, 1819
+; RV32I-NEXT: bltu a2, a3, .LBB0_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: .LBB0_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mv:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bltui a2, 10011, .LBB0_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB0_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %d, 10011
+ %sel = select i1 %x, i32 %a, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_mv_zerofalsev(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_mv_zerofalsev:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1819
+; RV32I-NEXT: sltu a1, a2, a1
+; RV32I-NEXT: neg a1, a1
+; RV32I-NEXT: and a0, a1, a0
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mv_zerofalsev:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bltui a2, 10011, .LBB1_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: li a0, 0
+; RV32I-SFB-WITH-IMM-NEXT: .LBB1_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %d, 10011
+ %sel = select i1 %x, i32 %a, i32 0
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_mv_zerofalsev_swapped(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_mv_zerofalsev_swapped:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1819
+; RV32I-NEXT: sltu a1, a2, a1
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: and a0, a1, a0
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mv_zerofalsev_swapped:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgeui a2, 10011, .LBB2_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: li a0, 0
+; RV32I-SFB-WITH-IMM-NEXT: .LBB2_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %d, 10011
+ %sel = select i1 %x, i32 0, i32 %a
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_mv_minusOnefalsev(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_mv_minusOnefalsev:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1819
+; RV32I-NEXT: sltu a1, a2, a1
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: or a0, a1, a0
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mv_minusOnefalsev:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: li a1, -1
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bltui a2, 10011, .LBB3_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB3_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %d, 10011
+ %sel = select i1 %x, i32 %a, i32 -1
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_mv_minusOnefalsev_swapped(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_mv_minusOnefalsev_swapped:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1819
+; RV32I-NEXT: sltu a1, a2, a1
+; RV32I-NEXT: neg a1, a1
+; RV32I-NEXT: or a0, a1, a0
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mv_minusOnefalsev_swapped:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: li a1, -1
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgeui a2, 10011, .LBB4_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB4_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %d, 10011
+ %sel = select i1 %x, i32 -1, i32 %a
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_add(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_add:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a4, 2
+; RV32I-NEXT: addi a4, a4, 1819
+; RV32I-NEXT: bgeu a3, a4, .LBB5_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: add a2, a0, a1
+; RV32I-NEXT: .LBB5_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_add:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgeui a3, 10011, .LBB5_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: add a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB5_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %d, 10011
+ %addi = add i32 %a, %b
+ %sel = select i1 %x, i32 %addi, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_sub(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_sub:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a4, 2
+; RV32I-NEXT: addi a4, a4, 1819
+; RV32I-NEXT: bgeu a3, a4, .LBB6_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: sub a2, a0, a1
+; RV32I-NEXT: .LBB6_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_sub:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgeui a3, 10011, .LBB6_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: sub a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB6_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %d, 10011
+ %subi = sub i32 %a, %b
+ %sel = select i1 %x, i32 %subi, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_shl(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_shl:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a4, 2
+; RV32I-NEXT: addi a4, a4, 1819
+; RV32I-NEXT: bgeu a3, a4, .LBB7_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: sll a2, a0, a1
+; RV32I-NEXT: .LBB7_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_shl:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgeui a3, 10011, .LBB7_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: sll a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB7_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %d, 10011
+ %shli = shl i32 %a, %b
+ %sel = select i1 %x, i32 %shli, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_lshr(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_lshr:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a4, 2
+; RV32I-NEXT: addi a4, a4, 1819
+; RV32I-NEXT: bgeu a3, a4, .LBB8_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: srl a2, a0, a1
+; RV32I-NEXT: .LBB8_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lshr:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgeui a3, 10011, .LBB8_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: srl a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB8_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %d, 10011
+ %lshri = lshr i32 %a, %b
+ %sel = select i1 %x, i32 %lshri, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_ashr(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_ashr:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a4, 2
+; RV32I-NEXT: addi a4, a4, 1819
+; RV32I-NEXT: bgeu a3, a4, .LBB9_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: sra a2, a0, a1
+; RV32I-NEXT: .LBB9_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_ashr:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgeui a3, 10011, .LBB9_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: sra a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB9_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %d, 10011
+ %ashri = ashr i32 %a, %b
+ %sel = select i1 %x, i32 %ashri, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_xor(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_xor:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a4, 2
+; RV32I-NEXT: addi a4, a4, 1819
+; RV32I-NEXT: bgeu a3, a4, .LBB10_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: xor a2, a0, a1
+; RV32I-NEXT: .LBB10_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_xor:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgeui a3, 10011, .LBB10_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: xor a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB10_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %d, 10011
+ %xori = xor i32 %a, %b
+ %sel = select i1 %x, i32 %xori, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_and(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_and:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a4, 2
+; RV32I-NEXT: addi a4, a4, 1819
+; RV32I-NEXT: bgeu a3, a4, .LBB11_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: and a2, a0, a1
+; RV32I-NEXT: .LBB11_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_and:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgeui a3, 10011, .LBB11_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: and a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB11_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %d, 10011
+ %andi = and i32 %a, %b
+ %sel = select i1 %x, i32 %andi, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_or(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_or:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a4, 2
+; RV32I-NEXT: addi a4, a4, 1819
+; RV32I-NEXT: bgeu a3, a4, .LBB12_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: or a2, a0, a1
+; RV32I-NEXT: .LBB12_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_or:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgeui a3, 10011, .LBB12_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: or a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB12_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %d, 10011
+ %ori = or i32 %a, %b
+ %sel = select i1 %x, i32 %ori, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_addi(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_addi:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1819
+; RV32I-NEXT: bgeu a3, a1, .LBB13_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: addi a2, a0, 11
+; RV32I-NEXT: .LBB13_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_addi:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgeui a3, 10011, .LBB13_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: addi a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB13_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %d, 10011
+ %addi = add i32 %a, 11
+ %sel = select i1 %x, i32 %addi, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_xori(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_xori:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1819
+; RV32I-NEXT: bgeu a3, a1, .LBB14_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: xori a2, a0, 11
+; RV32I-NEXT: .LBB14_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_xori:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgeui a3, 10011, .LBB14_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: xori a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB14_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %d, 10011
+ %xori = xor i32 %a, 11
+ %sel = select i1 %x, i32 %xori, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_shli(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_shli:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1819
+; RV32I-NEXT: bgeu a3, a1, .LBB15_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: slli a2, a0, 11
+; RV32I-NEXT: .LBB15_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_shli:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgeui a3, 10011, .LBB15_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: slli a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB15_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %d, 10011
+ %shli = shl i32 %a, 11
+ %sel = select i1 %x, i32 %shli, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_lshri(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_lshri:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1819
+; RV32I-NEXT: bgeu a3, a1, .LBB16_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: srli a2, a0, 11
+; RV32I-NEXT: .LBB16_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lshri:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgeui a3, 10011, .LBB16_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: srli a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB16_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %d, 10011
+ %lshri = lshr i32 %a, 11
+ %sel = select i1 %x, i32 %lshri, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_ashri(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_ashri:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1819
+; RV32I-NEXT: bgeu a3, a1, .LBB17_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: srai a2, a0, 11
+; RV32I-NEXT: .LBB17_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_ashri:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgeui a3, 10011, .LBB17_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: srai a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB17_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %d, 10011
+ %ashri = ashr i32 %a, 11
+ %sel = select i1 %x, i32 %ashri, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_andi(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_andi:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1819
+; RV32I-NEXT: bgeu a3, a1, .LBB18_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: andi a2, a0, 11
+; RV32I-NEXT: .LBB18_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_andi:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgeui a3, 10011, .LBB18_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: andi a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB18_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %d, 10011
+ %andi = and i32 %a, 11
+ %sel = select i1 %x, i32 %andi, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_ori(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_ori:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1819
+; RV32I-NEXT: bgeu a3, a1, .LBB19_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: ori a2, a0, 11
+; RV32I-NEXT: .LBB19_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_ori:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgeui a3, 10011, .LBB19_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ori a2, a0, 11
+; RV32I-SFB-WITH-IMM-NEXT: .LBB19_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %d, 10011
+ %ori = or i32 %a, 11
+ %sel = select i1 %x, i32 %ori, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_mul(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; RV32I-LABEL: branch_with_immSFB_mul:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: .cfi_def_cfa_offset 16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: .cfi_offset ra, -4
+; RV32I-NEXT: .cfi_offset s0, -8
+; RV32I-NEXT: .cfi_offset s1, -12
+; RV32I-NEXT: mv s1, a3
+; RV32I-NEXT: mv s0, a2
+; RV32I-NEXT: call __mulsi3
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, 1819
+; RV32I-NEXT: bltu s1, a1, .LBB20_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: .LBB20_2: # %entry
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: .cfi_restore ra
+; RV32I-NEXT: .cfi_restore s0
+; RV32I-NEXT: .cfi_restore s1
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: .cfi_def_cfa_offset 0
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_mul:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgeui a3, 10011, .LBB20_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mul a2, a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: .LBB20_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %d, 10011
+ %muli = mul i32 %a, %b
+ %sel = select i1 %x, i32 %muli, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_li(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_li:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a0, 2
+; RV32I-NEXT: addi a3, a0, 1819
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: bgeu a2, a3, .LBB21_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: lui a0, 16
+; RV32I-NEXT: addi a0, a0, 7
+; RV32I-NEXT: .LBB21_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_li:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgeui a2, 10011, .LBB21_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.li a0, 65543
+; RV32I-SFB-WITH-IMM-NEXT: .LBB21_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %d, 10011
+ %sel = select i1 %x, i32 65543, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_qc_e_li(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_qc_e_li:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a0, 2
+; RV32I-NEXT: addi a3, a0, 1819
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: bgeu a2, a3, .LBB22_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: lui a0, 1025
+; RV32I-NEXT: addi a0, a0, 528
+; RV32I-NEXT: .LBB22_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_qc_e_li:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgeui a2, 10011, .LBB22_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.li a0, 4198928
+; RV32I-SFB-WITH-IMM-NEXT: .LBB22_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %d, 10011
+ %sel = select i1 %x, i32 4198928, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_lui(i32 %a, i32 %c, i32 %d) {
+; RV32I-LABEL: branch_with_immSFB_lui:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a0, 2
+; RV32I-NEXT: addi a3, a0, 1819
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: bgeu a2, a3, .LBB23_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: lui a0, 16
+; RV32I-NEXT: .LBB23_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lui:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a1
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgeui a2, 10011, .LBB23_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lui a0, 16
+; RV32I-SFB-WITH-IMM-NEXT: .LBB23_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %d, 10011
+ %sel = select i1 %x, i32 65536, i32 %c
+ ret i32 %sel
+}
+
+define i32 @branch_with_immSFB_lb(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lb:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a3, a3, 1819
+; RV32I-NEXT: bgeu a1, a3, .LBB24_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lb a2, 4(a0)
+; RV32I-NEXT: .LBB24_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lb:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgeui a1, 10011, .LBB24_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lb a2, 4(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB24_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %a, 10011
+ %addr = getelementptr i8, ptr %base, i32 4 ; compute base + 4
+ %val = load i8, ptr %addr ; load 8-bit value
+ %ext = sext i8 %val to i32 ; sign-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lbu(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lbu:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a3, a3, 1819
+; RV32I-NEXT: bgeu a1, a3, .LBB25_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lbu a2, 4(a0)
+; RV32I-NEXT: .LBB25_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lbu:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgeui a1, 10011, .LBB25_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lbu a2, 4(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB25_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %a, 10011
+ %addr = getelementptr i8, ptr %base, i32 4 ; compute base + 4
+ %val = load i8, ptr %addr ; load 8-bit value
+ %ext = zext i8 %val to i32 ; zero-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lh(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lh:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a3, a3, 1819
+; RV32I-NEXT: bgeu a1, a3, .LBB26_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lh a2, 8(a0)
+; RV32I-NEXT: .LBB26_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lh:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgeui a1, 10011, .LBB26_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lh a2, 8(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB26_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %a, 10011
+ %addr = getelementptr i16, ptr %base, i32 4 ; compute base + 4
+ %val = load i16, ptr %addr ; load 16-bit value
+ %ext = sext i16 %val to i32 ; sign-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lhu(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lhu:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a3, a3, 1819
+; RV32I-NEXT: bgeu a1, a3, .LBB27_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lhu a2, 8(a0)
+; RV32I-NEXT: .LBB27_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lhu:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgeui a1, 10011, .LBB27_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lhu a2, 8(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB27_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %a, 10011
+ %addr = getelementptr i16, ptr %base, i32 4 ; compute base + 4
+ %val = load i16, ptr %addr ; load 16-bit value
+ %ext = zext i16 %val to i32 ; zero-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lw(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lw:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a3, a3, 1819
+; RV32I-NEXT: bgeu a1, a3, .LBB28_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lw a2, 16(a0)
+; RV32I-NEXT: .LBB28_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lw:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgeui a1, 10011, .LBB28_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: lw a2, 16(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB28_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %a, 10011
+ %addr = getelementptr i32, ptr %base, i32 4 ; compute base + 4
+ %val = load i32, ptr %addr ; load 32-bit value
+ %res = select i1 %x, i32 %val, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lb_qc_e(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lb_qc_e:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a4, a3, 1819
+; RV32I-NEXT: bgeu a1, a4, .LBB29_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: add a0, a0, a3
+; RV32I-NEXT: lb a2, 1808(a0)
+; RV32I-NEXT: .LBB29_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lb_qc_e:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgeui a1, 10011, .LBB29_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.lb a2, 10000(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB29_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %a, 10011
+ %addr = getelementptr i8, ptr %base, i32 10000 ; compute base + 10000
+ %val = load i8, ptr %addr ; load 8-bit value
+ %ext = sext i8 %val to i32 ; sign-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lbu_qc_e(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lbu_qc_e:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a4, a3, 1819
+; RV32I-NEXT: bgeu a1, a4, .LBB30_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: add a0, a0, a3
+; RV32I-NEXT: lbu a2, 1808(a0)
+; RV32I-NEXT: .LBB30_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lbu_qc_e:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgeui a1, 10011, .LBB30_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.lbu a2, 10000(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB30_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %a, 10011
+ %addr = getelementptr i8, ptr %base, i32 10000 ; compute base + 10000
+ %val = load i8, ptr %addr ; load 8-bit value
+ %ext = zext i8 %val to i32 ; zero-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lh_qc_e(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lh_qc_e:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a3, a3, 1819
+; RV32I-NEXT: bgeu a1, a3, .LBB31_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lui a1, 5
+; RV32I-NEXT: add a0, a0, a1
+; RV32I-NEXT: lh a2, -480(a0)
+; RV32I-NEXT: .LBB31_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lh_qc_e:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgeui a1, 10011, .LBB31_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.lh a2, 20000(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB31_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %a, 10011
+ %addr = getelementptr i16, ptr %base, i32 10000 ; compute base + 10000
+ %val = load i16, ptr %addr ; load 16-bit value
+ %ext = sext i16 %val to i32 ; sign-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lhu_qc_e(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lhu_qc_e:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a3, a3, 1819
+; RV32I-NEXT: bgeu a1, a3, .LBB32_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lui a1, 5
+; RV32I-NEXT: add a0, a0, a1
+; RV32I-NEXT: lhu a2, -480(a0)
+; RV32I-NEXT: .LBB32_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lhu_qc_e:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgeui a1, 10011, .LBB32_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.lhu a2, 20000(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB32_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %a, 10011
+ %addr = getelementptr i16, ptr %base, i32 10000 ; compute base + 10000
+ %val = load i16, ptr %addr ; load 16-bit value
+ %ext = zext i16 %val to i32 ; zero-extend to 32 bits
+ %res = select i1 %x, i32 %ext, i32 %b
+ ret i32 %res
+}
+
+define i32 @branch_with_immSFB_lw_qc_e(ptr %base, i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: branch_with_immSFB_lw_qc_e:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a3, 2
+; RV32I-NEXT: addi a3, a3, 1819
+; RV32I-NEXT: bgeu a1, a3, .LBB33_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: lui a1, 10
+; RV32I-NEXT: add a0, a0, a1
+; RV32I-NEXT: lw a2, -960(a0)
+; RV32I-NEXT: .LBB33_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32I-SFB-WITH-IMM-LABEL: branch_with_immSFB_lw_qc_e:
+; RV32I-SFB-WITH-IMM: # %bb.0: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.bgeui a1, 10011, .LBB33_2
+; RV32I-SFB-WITH-IMM-NEXT: # %bb.1: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: qc.e.lw a2, 40000(a0)
+; RV32I-SFB-WITH-IMM-NEXT: .LBB33_2: # %entry
+; RV32I-SFB-WITH-IMM-NEXT: mv a0, a2
+; RV32I-SFB-WITH-IMM-NEXT: ret
+entry:
+ %x = icmp ult i32 %a, 10011
+ %addr = getelementptr i32, ptr %base, i32 10000 ; compute base + 10000
+ %val = load i32, ptr %addr ; load 32-bit value
+ %res = select i1 %x, i32 %val, i32 %b
+ ret i32 %res
+}
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