[llvm] 02fb667 - AMDGPU/GlobalISel: RegBankLegalize rules for FFBH/FFBL (#186017)
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Fri Mar 13 11:00:12 PDT 2026
Author: vangthao95
Date: 2026-03-13T11:00:07-07:00
New Revision: 02fb667c6deba72a1bfeb3be80dcb5b245dd4df6
URL: https://github.com/llvm/llvm-project/commit/02fb667c6deba72a1bfeb3be80dcb5b245dd4df6
DIFF: https://github.com/llvm/llvm-project/commit/02fb667c6deba72a1bfeb3be80dcb5b245dd4df6.diff
LOG: AMDGPU/GlobalISel: RegBankLegalize rules for FFBH/FFBL (#186017)
Added:
Modified:
llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbh-u32.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbl-b32.mir
llvm/test/CodeGen/AMDGPU/ctlz.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
index 4fe1442f27864..40d343dd81812 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
@@ -1101,6 +1101,27 @@ bool RegBankLegalizeHelper::lower(MachineInstr &MI,
}
case ApplyINTRIN_IMAGE:
return applyRegisterBanksINTRIN_IMAGE(MI);
+ case SplitFFB64To32: {
+ // (ffbh hi:lo) -> umin(ffbh(hi), uaddsat(ffbh(lo), 32))
+ // (ffbl hi:lo) -> umin(ffbl(lo), uaddsat(ffbl(hi), 32))
+ auto Unmerge = B.buildUnmerge({VgprRB, S32}, MI.getOperand(1).getReg());
+ unsigned Opc = MI.getOpcode();
+ auto Lo = B.buildInstr(Opc, {{VgprRB, S32}}, {Unmerge.getReg(0)});
+ auto Hi = B.buildInstr(Opc, {{VgprRB, S32}}, {Unmerge.getReg(1)});
+
+ // FFBH counts from MSB, FFBL counts from LSB. The secondary half adds 32 to
+ // account for the primary half's width.
+ bool IsFFBH = Opc == AMDGPU::G_AMDGPU_FFBH_U32;
+ auto Primary = IsFFBH ? Hi : Lo;
+ auto Secondary = IsFFBH ? Lo : Hi;
+ auto Adjusted =
+ B.buildInstr(AMDGPU::G_UADDSAT, {{VgprRB, S32}},
+ {Secondary, B.buildConstant({VgprRB, S32}, 32)});
+ B.buildUMin(MI.getOperand(0).getReg(), Primary, Adjusted);
+
+ MI.eraseFromParent();
+ return true;
+ }
}
if (!WFI.SgprWaterfallOperandRegs.empty()) {
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index 0c7c823b78752..58ffa69cece4b 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -1184,6 +1184,12 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
.Uni(S64, {{Sgpr64}, {Sgpr64}})
.Div(S64, {{Vgpr64}, {Vgpr64}});
+ addRulesForGOpcs({G_AMDGPU_FFBH_U32, G_AMDGPU_FFBL_B32})
+ .Any({{UniS32, S32}, {{Sgpr32}, {Sgpr32}}})
+ .Any({{DivS32, S32}, {{Vgpr32}, {Vgpr32}}})
+ .Any({{UniS32, S64}, {{Sgpr32}, {Sgpr64}}})
+ .Any({{DivS32, S64}, {{Vgpr32}, {Vgpr64}, SplitFFB64To32}});
+
addRulesForGOpcs({G_FENCE}).Any({{{}}, {{}, {}}});
addRulesForGOpcs({G_READSTEADYCOUNTER, G_READCYCLECOUNTER}, Standard)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
index c5634c53270af..738c29c895223 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
@@ -274,7 +274,8 @@ enum LoweringMethodID {
AextToS32InIncomingBlockGPHI,
VerifyAllSgprGPHI,
VerifyAllSgprOrVgprGPHI,
- ApplyINTRIN_IMAGE
+ ApplyINTRIN_IMAGE,
+ SplitFFB64To32
};
enum FastRulesTypes {
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbh-u32.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbh-u32.mir
index fa5df0f69bb18..57f32580d44a3 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbh-u32.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbh-u32.mir
@@ -1,6 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
-# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s
---
name: ffbh_u32_s
@@ -34,3 +33,42 @@ body: |
%0:_(s32) = COPY $vgpr0
%1:_(s32) = G_AMDGPU_FFBH_U32 %0
...
+
+---
+name: ffbh_u32_s64_s
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1
+
+ ; CHECK-LABEL: name: ffbh_u32_s64_s
+ ; CHECK: liveins: $sgpr0_sgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
+ ; CHECK-NEXT: [[AMDGPU_FFBH_U32_:%[0-9]+]]:sgpr(s32) = G_AMDGPU_FFBH_U32 [[COPY]](s64)
+ %0:_(s64) = COPY $sgpr0_sgpr1
+ %1:_(s32) = G_AMDGPU_FFBH_U32 %0
+...
+
+---
+name: ffbh_u32_s64_v
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: ffbh_u32_s64_v
+ ; CHECK: liveins: $vgpr0_vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY]](s64)
+ ; CHECK-NEXT: [[AMDGPU_FFBH_U32_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_FFBH_U32 [[UV]](s32)
+ ; CHECK-NEXT: [[AMDGPU_FFBH_U32_1:%[0-9]+]]:vgpr(s32) = G_AMDGPU_FFBH_U32 [[UV1]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 32
+ ; CHECK-NEXT: [[UADDSAT:%[0-9]+]]:vgpr(s32) = G_UADDSAT [[AMDGPU_FFBH_U32_]], [[C]]
+ ; CHECK-NEXT: [[UMIN:%[0-9]+]]:vgpr(s32) = G_UMIN [[AMDGPU_FFBH_U32_1]], [[UADDSAT]]
+ %0:_(s64) = COPY $vgpr0_vgpr1
+ %1:_(s32) = G_AMDGPU_FFBH_U32 %0
+...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbl-b32.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbl-b32.mir
index 23fc3de6490af..fe7210cf1654a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbl-b32.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbl-b32.mir
@@ -1,6 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
-# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s
---
name: ffbl_b32_s
@@ -34,3 +33,42 @@ body: |
%0:_(s32) = COPY $vgpr0
%1:_(s32) = G_AMDGPU_FFBL_B32 %0
...
+
+---
+name: ffbl_b32_s64_s
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1
+
+ ; CHECK-LABEL: name: ffbl_b32_s64_s
+ ; CHECK: liveins: $sgpr0_sgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
+ ; CHECK-NEXT: [[AMDGPU_FFBL_B32_:%[0-9]+]]:sgpr(s32) = G_AMDGPU_FFBL_B32 [[COPY]](s64)
+ %0:_(s64) = COPY $sgpr0_sgpr1
+ %1:_(s32) = G_AMDGPU_FFBL_B32 %0
+...
+
+---
+name: ffbl_b32_s64_v
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: ffbl_b32_s64_v
+ ; CHECK: liveins: $vgpr0_vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY]](s64)
+ ; CHECK-NEXT: [[AMDGPU_FFBL_B32_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_FFBL_B32 [[UV]](s32)
+ ; CHECK-NEXT: [[AMDGPU_FFBL_B32_1:%[0-9]+]]:vgpr(s32) = G_AMDGPU_FFBL_B32 [[UV1]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 32
+ ; CHECK-NEXT: [[UADDSAT:%[0-9]+]]:vgpr(s32) = G_UADDSAT [[AMDGPU_FFBL_B32_1]], [[C]]
+ ; CHECK-NEXT: [[UMIN:%[0-9]+]]:vgpr(s32) = G_UMIN [[AMDGPU_FFBL_B32_]], [[UADDSAT]]
+ %0:_(s64) = COPY $vgpr0_vgpr1
+ %1:_(s32) = G_AMDGPU_FFBL_B32 %0
+...
diff --git a/llvm/test/CodeGen/AMDGPU/ctlz.ll b/llvm/test/CodeGen/AMDGPU/ctlz.ll
index 8b7cf17cffe2b..2813a030d737b 100644
--- a/llvm/test/CodeGen/AMDGPU/ctlz.ll
+++ b/llvm/test/CodeGen/AMDGPU/ctlz.ll
@@ -3,7 +3,7 @@
; RUN: llc < %s -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global | FileCheck %s -enable-var-scope --check-prefix=VI
; RUN: llc < %s -mtriple=r600 -mcpu=cypress | FileCheck %s -enable-var-scope --check-prefix=EG
; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1010 | FileCheck %s -enable-var-scope --check-prefix=GFX10
-; RUN: llc < %s -global-isel -mtriple=amdgcn -mcpu=gfx1010 | FileCheck %s -enable-var-scope --check-prefix=GFX10-GISEL
+; RUN: llc < %s -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1010 | FileCheck %s -enable-var-scope --check-prefix=GFX10-GISEL
; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 | FileCheck %s -enable-var-scope --check-prefixes=GFX11,GFX11-TRUE16
; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 | FileCheck %s -enable-var-scope --check-prefixes=GFX11,GFX11-FAKE16
@@ -566,9 +566,11 @@ define amdgpu_kernel void @v_ctlz_i8(ptr addrspace(1) noalias %out, ptr addrspac
; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-GISEL-NEXT: global_load_ubyte v1, v0, s[2:3]
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0)
-; GFX10-GISEL-NEXT: v_ffbh_u32_e32 v1, v1
-; GFX10-GISEL-NEXT: v_min_u32_e32 v1, 32, v1
-; GFX10-GISEL-NEXT: v_add_nc_u32_e32 v1, 0xffffffe8, v1
+; GFX10-GISEL-NEXT: v_readfirstlane_b32 s2, v1
+; GFX10-GISEL-NEXT: s_flbit_i32_b32 s2, s2
+; GFX10-GISEL-NEXT: s_min_u32 s2, s2, 32
+; GFX10-GISEL-NEXT: s_sub_i32 s2, s2, 24
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, s2
; GFX10-GISEL-NEXT: global_store_byte v0, v1, s[0:1]
; GFX10-GISEL-NEXT: s_endpgm
;
@@ -2169,11 +2171,14 @@ define amdgpu_kernel void @v_ctlz_i8_sel_eq_neg1(ptr addrspace(1) noalias %out,
; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-GISEL-NEXT: global_load_ushort v1, v0, s[2:3]
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0)
-; GFX10-GISEL-NEXT: v_ffbh_u32_sdwa v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-; GFX10-GISEL-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1
-; GFX10-GISEL-NEXT: v_min_u32_e32 v2, 32, v2
-; GFX10-GISEL-NEXT: v_add_nc_u16 v2, v2, -16
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, v2, 0xffff, vcc_lo
+; GFX10-GISEL-NEXT: v_readfirstlane_b32 s2, v1
+; GFX10-GISEL-NEXT: s_and_b32 s2, s2, 0xffff
+; GFX10-GISEL-NEXT: s_flbit_i32_b32 s3, s2
+; GFX10-GISEL-NEXT: s_min_u32 s3, s3, 32
+; GFX10-GISEL-NEXT: s_add_i32 s3, s3, 0xfff0
+; GFX10-GISEL-NEXT: s_cmp_eq_u32 s2, 0
+; GFX10-GISEL-NEXT: s_cselect_b32 s2, 0xffff, s3
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, s2
; GFX10-GISEL-NEXT: global_store_short v0, v1, s[0:1]
; GFX10-GISEL-NEXT: s_endpgm
;
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