[llvm] [NFC][LLVM] Fix indentation issue in AArch64ExpandPseudo::expandMI (PR #186375)

[via llvm-commits]

github-actions[bot] wrote:

<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


:warning: C/C++ code formatter, clang-format found issues in your code. :warning:

<details>
<summary>
You can test this locally with the following command:
</summary>

``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp -- llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp --diff_from_common_commit
``````````

:warning:
The reproduction instructions above might return results for more than one PR
in a stack if you are using a stacked PR workflow. You can limit the results by
changing `origin/main` to the base branch/commit you want to compare against.
:warning:

</details>

<details>
<summary>
View the diff from clang-format here.
</summary>

``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp b/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
index b8e48353b..71dd86cd9 100644
--- a/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
@@ -1844,21 +1844,21 @@ bool AArch64ExpandPseudo::expandMI(MachineBasicBlock &MBB,
                                 AArch64::ZPR2StridedRegClass, AArch64::LD1D_2Z,
                                 AArch64::LD1D_2Z_STRIDED);
   case AArch64::LDNT1B_2Z_PSEUDO:
-    return expandMultiVecPseudo(
-        MBB, MBBI, AArch64::ZPR2RegClass, AArch64::ZPR2StridedRegClass,
-        AArch64::LDNT1B_2Z, AArch64::LDNT1B_2Z_STRIDED);
+    return expandMultiVecPseudo(MBB, MBBI, AArch64::ZPR2RegClass,
+                                AArch64::ZPR2StridedRegClass,
+                                AArch64::LDNT1B_2Z, AArch64::LDNT1B_2Z_STRIDED);
   case AArch64::LDNT1H_2Z_PSEUDO:
-    return expandMultiVecPseudo(
-        MBB, MBBI, AArch64::ZPR2RegClass, AArch64::ZPR2StridedRegClass,
-        AArch64::LDNT1H_2Z, AArch64::LDNT1H_2Z_STRIDED);
+    return expandMultiVecPseudo(MBB, MBBI, AArch64::ZPR2RegClass,
+                                AArch64::ZPR2StridedRegClass,
+                                AArch64::LDNT1H_2Z, AArch64::LDNT1H_2Z_STRIDED);
   case AArch64::LDNT1W_2Z_PSEUDO:
-    return expandMultiVecPseudo(
-        MBB, MBBI, AArch64::ZPR2RegClass, AArch64::ZPR2StridedRegClass,
-        AArch64::LDNT1W_2Z, AArch64::LDNT1W_2Z_STRIDED);
+    return expandMultiVecPseudo(MBB, MBBI, AArch64::ZPR2RegClass,
+                                AArch64::ZPR2StridedRegClass,
+                                AArch64::LDNT1W_2Z, AArch64::LDNT1W_2Z_STRIDED);
   case AArch64::LDNT1D_2Z_PSEUDO:
-    return expandMultiVecPseudo(
-        MBB, MBBI, AArch64::ZPR2RegClass, AArch64::ZPR2StridedRegClass,
-        AArch64::LDNT1D_2Z, AArch64::LDNT1D_2Z_STRIDED);
+    return expandMultiVecPseudo(MBB, MBBI, AArch64::ZPR2RegClass,
+                                AArch64::ZPR2StridedRegClass,
+                                AArch64::LDNT1D_2Z, AArch64::LDNT1D_2Z_STRIDED);
   case AArch64::LD1B_4Z_IMM_PSEUDO:
     return expandMultiVecPseudo(
         MBB, MBBI, AArch64::ZPR4RegClass, AArch64::ZPR4StridedRegClass,
@@ -1908,21 +1908,21 @@ bool AArch64ExpandPseudo::expandMI(MachineBasicBlock &MBB,
                                 AArch64::ZPR4StridedRegClass, AArch64::LD1D_4Z,
                                 AArch64::LD1D_4Z_STRIDED);
   case AArch64::LDNT1B_4Z_PSEUDO:
-    return expandMultiVecPseudo(
-        MBB, MBBI, AArch64::ZPR4RegClass, AArch64::ZPR4StridedRegClass,
-        AArch64::LDNT1B_4Z, AArch64::LDNT1B_4Z_STRIDED);
+    return expandMultiVecPseudo(MBB, MBBI, AArch64::ZPR4RegClass,
+                                AArch64::ZPR4StridedRegClass,
+                                AArch64::LDNT1B_4Z, AArch64::LDNT1B_4Z_STRIDED);
   case AArch64::LDNT1H_4Z_PSEUDO:
-    return expandMultiVecPseudo(
-        MBB, MBBI, AArch64::ZPR4RegClass, AArch64::ZPR4StridedRegClass,
-        AArch64::LDNT1H_4Z, AArch64::LDNT1H_4Z_STRIDED);
+    return expandMultiVecPseudo(MBB, MBBI, AArch64::ZPR4RegClass,
+                                AArch64::ZPR4StridedRegClass,
+                                AArch64::LDNT1H_4Z, AArch64::LDNT1H_4Z_STRIDED);
   case AArch64::LDNT1W_4Z_PSEUDO:
-    return expandMultiVecPseudo(
-        MBB, MBBI, AArch64::ZPR4RegClass, AArch64::ZPR4StridedRegClass,
-        AArch64::LDNT1W_4Z, AArch64::LDNT1W_4Z_STRIDED);
+    return expandMultiVecPseudo(MBB, MBBI, AArch64::ZPR4RegClass,
+                                AArch64::ZPR4StridedRegClass,
+                                AArch64::LDNT1W_4Z, AArch64::LDNT1W_4Z_STRIDED);
   case AArch64::LDNT1D_4Z_PSEUDO:
-    return expandMultiVecPseudo(
-        MBB, MBBI, AArch64::ZPR4RegClass, AArch64::ZPR4StridedRegClass,
-        AArch64::LDNT1D_4Z, AArch64::LDNT1D_4Z_STRIDED);
+    return expandMultiVecPseudo(MBB, MBBI, AArch64::ZPR4RegClass,
+                                AArch64::ZPR4StridedRegClass,
+                                AArch64::LDNT1D_4Z, AArch64::LDNT1D_4Z_STRIDED);
   case AArch64::FORM_TRANSPOSED_REG_TUPLE_X2_PSEUDO:
     return expandFormTuplePseudo(MBB, MBBI, NextMBBI, 2);
   case AArch64::FORM_TRANSPOSED_REG_TUPLE_X4_PSEUDO:

``````````

</details>


https://github.com/llvm/llvm-project/pull/186375