[llvm] [AMDGPU] Use AMDGPULaneMaskUtils in SILowerI1Copies (PR #186170)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 12 10:19:04 PDT 2026
https://github.com/idubinov updated https://github.com/llvm/llvm-project/pull/186170
>From 571346d099579ddea839e3981c028f3dd3842c9a Mon Sep 17 00:00:00 2001
From: idubinov <igor.dubinov at amd.com>
Date: Thu, 12 Mar 2026 11:29:13 -0500
Subject: [PATCH 1/2] Use AMDGPULaneMaskUtils in SILowerI1Copies
---
.../AMDGPUGlobalISelDivergenceLowering.cpp | 8 ++--
llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp | 46 ++++++-------------
llvm/lib/Target/AMDGPU/SILowerI1Copies.h | 12 ++---
3 files changed, 21 insertions(+), 45 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUGlobalISelDivergenceLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUGlobalISelDivergenceLowering.cpp
index b72bfaa3e7d10..bd882f421c83a 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUGlobalISelDivergenceLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUGlobalISelDivergenceLowering.cpp
@@ -177,9 +177,9 @@ void DivergenceLoweringHelper::buildMergeLaneMasks(
Register CurMaskedReg = createLaneMaskReg(MRI, LaneMaskRegAttrs);
B.setInsertPt(MBB, I);
- B.buildInstr(AndN2Op, {PrevMaskedReg}, {PrevRegCopy, ExecReg});
- B.buildInstr(AndOp, {CurMaskedReg}, {ExecReg, CurRegCopy});
- B.buildInstr(OrOp, {DstReg}, {PrevMaskedReg, CurMaskedReg});
+ B.buildInstr(LMC.AndN2Opc, {PrevMaskedReg}, {PrevRegCopy, LMC.ExecReg});
+ B.buildInstr(LMC.AndOpc, {CurMaskedReg}, {LMC.ExecReg, CurRegCopy});
+ B.buildInstr(LMC.OrOpc, {DstReg}, {PrevMaskedReg, CurMaskedReg});
}
// GlobalISel has to constrain S1 incoming taken as-is with lane mask register
@@ -222,7 +222,7 @@ bool DivergenceLoweringHelper::lowerTemporalDivergence() {
Register VgprReg = MRI->createGenericVirtualRegister(MRI->getType(Reg));
B.buildInstr(AMDGPU::COPY, {VgprReg}, {Reg})
- .addUse(ExecReg, RegState::Implicit);
+ .addUse(LMC.ExecReg, RegState::Implicit);
replaceUsesOfRegInInstWith(Reg, UseInst, VgprReg);
TDCache[Reg] = VgprReg;
diff --git a/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp b/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
index 0b8c71a4a2453..54916c2b18db7 100644
--- a/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
+++ b/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
@@ -442,30 +442,12 @@ bool Vreg1LoweringHelper::lowerCopiesFromI1() {
PhiLoweringHelper::PhiLoweringHelper(MachineFunction *MF,
MachineDominatorTree *DT,
MachinePostDominatorTree *PDT)
- : MF(MF), DT(DT), PDT(PDT) {
+ : MF(MF), DT(DT), PDT(PDT),
+ LMC(AMDGPU::LaneMaskConstants::get(MF->getSubtarget<GCNSubtarget>())) {
MRI = &MF->getRegInfo();
ST = &MF->getSubtarget<GCNSubtarget>();
TII = ST->getInstrInfo();
- IsWave32 = ST->isWave32();
-
- if (IsWave32) {
- ExecReg = AMDGPU::EXEC_LO;
- MovOp = AMDGPU::S_MOV_B32;
- AndOp = AMDGPU::S_AND_B32;
- OrOp = AMDGPU::S_OR_B32;
- XorOp = AMDGPU::S_XOR_B32;
- AndN2Op = AMDGPU::S_ANDN2_B32;
- OrN2Op = AMDGPU::S_ORN2_B32;
- } else {
- ExecReg = AMDGPU::EXEC;
- MovOp = AMDGPU::S_MOV_B64;
- AndOp = AMDGPU::S_AND_B64;
- OrOp = AMDGPU::S_OR_B64;
- XorOp = AMDGPU::S_XOR_B64;
- AndN2Op = AMDGPU::S_ANDN2_B64;
- OrN2Op = AMDGPU::S_ORN2_B64;
- }
}
bool PhiLoweringHelper::lowerPhis() {
@@ -677,7 +659,7 @@ bool PhiLoweringHelper::isConstantLaneMask(Register Reg, bool &Val) const {
return false;
}
- if (MI->getOpcode() != MovOp)
+ if (MI->getOpcode() != LMC.MovOpc)
return false;
if (!MI->getOperand(1).isImm())
@@ -795,10 +777,10 @@ void Vreg1LoweringHelper::buildMergeLaneMasks(MachineBasicBlock &MBB,
if (PrevVal == CurVal) {
BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg).addReg(CurReg);
} else if (CurVal) {
- BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg).addReg(ExecReg);
+ BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg).addReg(LMC.ExecReg);
} else {
- BuildMI(MBB, I, DL, TII->get(XorOp), DstReg)
- .addReg(ExecReg)
+ BuildMI(MBB, I, DL, TII->get(LMC.XorOpc), DstReg)
+ .addReg(LMC.ExecReg)
.addImm(-1);
}
return;
@@ -811,9 +793,9 @@ void Vreg1LoweringHelper::buildMergeLaneMasks(MachineBasicBlock &MBB,
PrevMaskedReg = PrevReg;
} else {
PrevMaskedReg = createLaneMaskReg(MRI, LaneMaskRegAttrs);
- BuildMI(MBB, I, DL, TII->get(AndN2Op), PrevMaskedReg)
+ BuildMI(MBB, I, DL, TII->get(LMC.AndN2Opc), PrevMaskedReg)
.addReg(PrevReg)
- .addReg(ExecReg);
+ .addReg(LMC.ExecReg);
}
}
if (!CurConstant) {
@@ -822,9 +804,9 @@ void Vreg1LoweringHelper::buildMergeLaneMasks(MachineBasicBlock &MBB,
CurMaskedReg = CurReg;
} else {
CurMaskedReg = createLaneMaskReg(MRI, LaneMaskRegAttrs);
- BuildMI(MBB, I, DL, TII->get(AndOp), CurMaskedReg)
+ BuildMI(MBB, I, DL, TII->get(LMC.AndOpc), CurMaskedReg)
.addReg(CurReg)
- .addReg(ExecReg);
+ .addReg(LMC.ExecReg);
}
}
@@ -835,13 +817,13 @@ void Vreg1LoweringHelper::buildMergeLaneMasks(MachineBasicBlock &MBB,
BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg)
.addReg(PrevMaskedReg);
} else if (PrevConstant && PrevVal) {
- BuildMI(MBB, I, DL, TII->get(OrN2Op), DstReg)
+ BuildMI(MBB, I, DL, TII->get(LMC.OrN2Opc), DstReg)
.addReg(CurMaskedReg)
- .addReg(ExecReg);
+ .addReg(LMC.ExecReg);
} else {
- BuildMI(MBB, I, DL, TII->get(OrOp), DstReg)
+ BuildMI(MBB, I, DL, TII->get(LMC.OrOpc), DstReg)
.addReg(PrevMaskedReg)
- .addReg(CurMaskedReg ? CurMaskedReg : ExecReg);
+ .addReg(CurMaskedReg ? CurMaskedReg : LMC.ExecReg);
}
}
diff --git a/llvm/lib/Target/AMDGPU/SILowerI1Copies.h b/llvm/lib/Target/AMDGPU/SILowerI1Copies.h
index fd90328c2b926..f1d028df3afb6 100644
--- a/llvm/lib/Target/AMDGPU/SILowerI1Copies.h
+++ b/llvm/lib/Target/AMDGPU/SILowerI1Copies.h
@@ -12,6 +12,7 @@
//
//===----------------------------------------------------------------------===//
+#include "AMDGPULaneMaskUtils.h"
#include "GCNSubtarget.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachinePostDominators.h"
@@ -20,7 +21,7 @@
namespace llvm {
-/// Incoming for lane maks phi as machine instruction, incoming register \p Reg
+/// Incoming for lane mask phi as machine instruction, incoming register \p Reg
/// and incoming block \p Block are taken from machine instruction.
/// \p UpdatedReg (if valid) is \p Reg lane mask merged with another lane mask.
struct Incoming {
@@ -50,19 +51,12 @@ class PhiLoweringHelper {
const GCNSubtarget *ST = nullptr;
const SIInstrInfo *TII = nullptr;
MachineRegisterInfo::VRegAttrs LaneMaskRegAttrs;
+ const AMDGPU::LaneMaskConstants &LMC;
#ifndef NDEBUG
DenseSet<Register> PhiRegisters;
#endif
- Register ExecReg;
- unsigned MovOp;
- unsigned AndOp;
- unsigned OrOp;
- unsigned XorOp;
- unsigned AndN2Op;
- unsigned OrN2Op;
-
public:
bool lowerPhis();
bool isConstantLaneMask(Register Reg, bool &Val) const;
>From b4ef4c08930b05c9459746412d60761eb5eb9b0e Mon Sep 17 00:00:00 2001
From: idubinov <igor.dubinov at amd.com>
Date: Thu, 12 Mar 2026 12:18:39 -0500
Subject: [PATCH 2/2] address review
---
.../AMDGPUGlobalISelDivergenceLowering.cpp | 8 ++---
llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp | 29 +++++++++----------
llvm/lib/Target/AMDGPU/SILowerI1Copies.h | 2 +-
3 files changed, 19 insertions(+), 20 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUGlobalISelDivergenceLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUGlobalISelDivergenceLowering.cpp
index bd882f421c83a..714958c79f609 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUGlobalISelDivergenceLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUGlobalISelDivergenceLowering.cpp
@@ -177,9 +177,9 @@ void DivergenceLoweringHelper::buildMergeLaneMasks(
Register CurMaskedReg = createLaneMaskReg(MRI, LaneMaskRegAttrs);
B.setInsertPt(MBB, I);
- B.buildInstr(LMC.AndN2Opc, {PrevMaskedReg}, {PrevRegCopy, LMC.ExecReg});
- B.buildInstr(LMC.AndOpc, {CurMaskedReg}, {LMC.ExecReg, CurRegCopy});
- B.buildInstr(LMC.OrOpc, {DstReg}, {PrevMaskedReg, CurMaskedReg});
+ B.buildInstr(LMC->AndN2Opc, {PrevMaskedReg}, {PrevRegCopy, LMC->ExecReg});
+ B.buildInstr(LMC->AndOpc, {CurMaskedReg}, {LMC->ExecReg, CurRegCopy});
+ B.buildInstr(LMC->OrOpc, {DstReg}, {PrevMaskedReg, CurMaskedReg});
}
// GlobalISel has to constrain S1 incoming taken as-is with lane mask register
@@ -222,7 +222,7 @@ bool DivergenceLoweringHelper::lowerTemporalDivergence() {
Register VgprReg = MRI->createGenericVirtualRegister(MRI->getType(Reg));
B.buildInstr(AMDGPU::COPY, {VgprReg}, {Reg})
- .addUse(LMC.ExecReg, RegState::Implicit);
+ .addUse(LMC->ExecReg, RegState::Implicit);
replaceUsesOfRegInInstWith(Reg, UseInst, VgprReg);
TDCache[Reg] = VgprReg;
diff --git a/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp b/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
index 54916c2b18db7..ee8465697cb54 100644
--- a/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
+++ b/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
@@ -442,11 +442,10 @@ bool Vreg1LoweringHelper::lowerCopiesFromI1() {
PhiLoweringHelper::PhiLoweringHelper(MachineFunction *MF,
MachineDominatorTree *DT,
MachinePostDominatorTree *PDT)
- : MF(MF), DT(DT), PDT(PDT),
- LMC(AMDGPU::LaneMaskConstants::get(MF->getSubtarget<GCNSubtarget>())) {
+ : MF(MF), DT(DT), PDT(PDT), ST(&MF->getSubtarget<GCNSubtarget>()),
+ LMC(&AMDGPU::LaneMaskConstants::get(*ST)) {
MRI = &MF->getRegInfo();
- ST = &MF->getSubtarget<GCNSubtarget>();
TII = ST->getInstrInfo();
}
@@ -659,7 +658,7 @@ bool PhiLoweringHelper::isConstantLaneMask(Register Reg, bool &Val) const {
return false;
}
- if (MI->getOpcode() != LMC.MovOpc)
+ if (MI->getOpcode() != LMC->MovOpc)
return false;
if (!MI->getOperand(1).isImm())
@@ -777,10 +776,10 @@ void Vreg1LoweringHelper::buildMergeLaneMasks(MachineBasicBlock &MBB,
if (PrevVal == CurVal) {
BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg).addReg(CurReg);
} else if (CurVal) {
- BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg).addReg(LMC.ExecReg);
+ BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg).addReg(LMC->ExecReg);
} else {
- BuildMI(MBB, I, DL, TII->get(LMC.XorOpc), DstReg)
- .addReg(LMC.ExecReg)
+ BuildMI(MBB, I, DL, TII->get(LMC->XorOpc), DstReg)
+ .addReg(LMC->ExecReg)
.addImm(-1);
}
return;
@@ -793,9 +792,9 @@ void Vreg1LoweringHelper::buildMergeLaneMasks(MachineBasicBlock &MBB,
PrevMaskedReg = PrevReg;
} else {
PrevMaskedReg = createLaneMaskReg(MRI, LaneMaskRegAttrs);
- BuildMI(MBB, I, DL, TII->get(LMC.AndN2Opc), PrevMaskedReg)
+ BuildMI(MBB, I, DL, TII->get(LMC->AndN2Opc), PrevMaskedReg)
.addReg(PrevReg)
- .addReg(LMC.ExecReg);
+ .addReg(LMC->ExecReg);
}
}
if (!CurConstant) {
@@ -804,9 +803,9 @@ void Vreg1LoweringHelper::buildMergeLaneMasks(MachineBasicBlock &MBB,
CurMaskedReg = CurReg;
} else {
CurMaskedReg = createLaneMaskReg(MRI, LaneMaskRegAttrs);
- BuildMI(MBB, I, DL, TII->get(LMC.AndOpc), CurMaskedReg)
+ BuildMI(MBB, I, DL, TII->get(LMC->AndOpc), CurMaskedReg)
.addReg(CurReg)
- .addReg(LMC.ExecReg);
+ .addReg(LMC->ExecReg);
}
}
@@ -817,13 +816,13 @@ void Vreg1LoweringHelper::buildMergeLaneMasks(MachineBasicBlock &MBB,
BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg)
.addReg(PrevMaskedReg);
} else if (PrevConstant && PrevVal) {
- BuildMI(MBB, I, DL, TII->get(LMC.OrN2Opc), DstReg)
+ BuildMI(MBB, I, DL, TII->get(LMC->OrN2Opc), DstReg)
.addReg(CurMaskedReg)
- .addReg(LMC.ExecReg);
+ .addReg(LMC->ExecReg);
} else {
- BuildMI(MBB, I, DL, TII->get(LMC.OrOpc), DstReg)
+ BuildMI(MBB, I, DL, TII->get(LMC->OrOpc), DstReg)
.addReg(PrevMaskedReg)
- .addReg(CurMaskedReg ? CurMaskedReg : LMC.ExecReg);
+ .addReg(CurMaskedReg ? CurMaskedReg : LMC->ExecReg);
}
}
diff --git a/llvm/lib/Target/AMDGPU/SILowerI1Copies.h b/llvm/lib/Target/AMDGPU/SILowerI1Copies.h
index f1d028df3afb6..8eb587cc025d6 100644
--- a/llvm/lib/Target/AMDGPU/SILowerI1Copies.h
+++ b/llvm/lib/Target/AMDGPU/SILowerI1Copies.h
@@ -51,7 +51,7 @@ class PhiLoweringHelper {
const GCNSubtarget *ST = nullptr;
const SIInstrInfo *TII = nullptr;
MachineRegisterInfo::VRegAttrs LaneMaskRegAttrs;
- const AMDGPU::LaneMaskConstants &LMC;
+ const AMDGPU::LaneMaskConstants *LMC = nullptr;
#ifndef NDEBUG
DenseSet<Register> PhiRegisters;
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