[llvm] 641ab6e - [CodeGen] check artificial subregister before propagate copy (#185751)

[via llvm-commits]

Author: Brox Chen
Date: 2026-03-12T11:16:36-04:00
New Revision: 641ab6ef83e90b7d9c434e4fc0769b81eba17650

URL: https://github.com/llvm/llvm-project/commit/641ab6ef83e90b7d9c434e4fc0769b81eba17650
DIFF: https://github.com/llvm/llvm-project/commit/641ab6ef83e90b7d9c434e4fc0769b81eba17650.diff

LOG: [CodeGen] check artificial subregister before propagate copy (#185751)

In machine copy propagation pass, do not propagate the subregister copy
if the subreg is artificial

Added: 
    llvm/test/CodeGen/AMDGPU/machine-cp-propagation.mir

Modified: 
    llvm/lib/CodeGen/MachineCopyPropagation.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/MachineCopyPropagation.cpp b/llvm/lib/CodeGen/MachineCopyPropagation.cpp
index 2a344b40c30c1..58ff6f77830b3 100644
--- a/llvm/lib/CodeGen/MachineCopyPropagation.cpp
+++ b/llvm/lib/CodeGen/MachineCopyPropagation.cpp
@@ -819,7 +819,7 @@ void MachineCopyPropagation::forwardUses(MachineInstr &MI) {
       assert(SubRegIdx &&
              "MI source is not a sub-register of Copy destination");
       ForwardedReg = TRI->getSubReg(CopySrcReg, SubRegIdx);
-      if (!ForwardedReg) {
+      if (!ForwardedReg || TRI->isArtificial(ForwardedReg)) {
         LLVM_DEBUG(dbgs() << "MCP: Copy source does not have sub-register "
                           << TRI->getSubRegIndexName(SubRegIdx) << '\n');
         continue;

diff  --git a/llvm/test/CodeGen/AMDGPU/machine-cp-propagation.mir b/llvm/test/CodeGen/AMDGPU/machine-cp-propagation.mir
new file mode 100644
index 0000000000000..e7a63446535a5
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/machine-cp-propagation.mir
@@ -0,0 +1,36 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 -run-pass=machine-cp -o - %s | FileCheck -check-prefixes=CHECK %s
+
+# vgpr2_hi16 should not fold into sgpr4_hi16
+---
+name:            test_machine_copy
+alignment:       1
+tracksRegLiveness: true
+machineFunctionInfo:
+  isEntryFunction: true
+body:             |
+  bb.0:
+  liveins: $vgpr0, $sgpr4_sgpr5
+    ; CHECK-LABEL: name: test_machine_copy
+    ; CHECK: liveins: $vgpr0, $sgpr4_sgpr5
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = S_LOAD_DWORDX4_IMM renamable $sgpr4_sgpr5, 0, 0
+    ; CHECK-NEXT: $vgpr0 = V_AND_B32_e64 1023, killed $vgpr0, implicit $exec
+    ; CHECK-NEXT: $vgpr0 = nuw nsw V_LSHLREV_B32_e64 2, killed $vgpr0, implicit $exec
+    ; CHECK-NEXT: $sgpr4 = S_LOAD_DWORD_IMM killed renamable $sgpr4_sgpr5, 16, 0
+    ; CHECK-NEXT: $vgpr1 = GLOBAL_LOAD_DWORD_SADDR renamable $sgpr2_sgpr3, renamable $vgpr0, 0, 0, implicit $exec
+    ; CHECK-NEXT: $vgpr2 = COPY killed renamable $sgpr4
+    ; CHECK-NEXT: $vgpr1_lo16 = COPY killed renamable $vgpr2_hi16
+    ; CHECK-NEXT: GLOBAL_STORE_DWORD_SADDR killed renamable $vgpr0, killed renamable $vgpr1, killed renamable $sgpr0_sgpr1, 0, 0, implicit $exec
+    ; CHECK-NEXT: S_ENDPGM 0
+  $sgpr0_sgpr1_sgpr2_sgpr3 = S_LOAD_DWORDX4_IMM renamable $sgpr4_sgpr5, 0, 0
+  $vgpr0 = V_AND_B32_e64 1023, killed $vgpr0, implicit $exec
+  $vgpr0 = nuw nsw V_LSHLREV_B32_e64 2, killed $vgpr0, implicit $exec
+  $sgpr4 = S_LOAD_DWORD_IMM killed renamable $sgpr4_sgpr5, 16, 0
+  $vgpr1 = GLOBAL_LOAD_DWORD_SADDR renamable $sgpr2_sgpr3, renamable $vgpr0, 0, 0, implicit $exec
+  $vgpr2 = COPY killed renamable $sgpr4
+  $vgpr1_lo16 = COPY killed renamable $vgpr2_hi16
+  GLOBAL_STORE_DWORD_SADDR killed renamable $vgpr0, killed renamable $vgpr1, killed renamable $sgpr0_sgpr1, 0, 0, implicit $exec
+  S_ENDPGM 0
+...
+