[llvm] [AArch64][llvm] Gate some `tlbip` insns with either +tlbid or +d128 (PR #178913)

[Jonathan Thackray via llvm-commits]

================
@@ -4264,12 +4264,24 @@ bool AArch64AsmParser::parseSyspAlias(StringRef Name, SMLoc NameLoc,
     const AArch64TLBIP::TLBIP *TLBIP = AArch64TLBIP::lookupTLBIPByName(Op);
     if (!TLBIP)
       return TokError("invalid operand for TLBIP instruction");
-    if (!getSTI().hasFeature(AArch64::FeatureD128) &&
-        !getSTI().hasFeature(AArch64::FeatureAll))
-      return TokError("instruction requires: d128");
+
     if (!TLBIP->haveFeatures(getSTI().getFeatureBits())) {
+      FeatureBitset Active = getSTI().getFeatureBits();
+      FeatureBitset Missing = TLBIP->getRequiredFeatures() & ~Active;
+
+      bool NeedD128OrTLBID =
+          TLBIP->allowTLBID() &&
+          !(Active[AArch64::FeatureD128] || Active[AArch64::FeatureTLBID]);
+
       std::string Str("instruction requires: ");
-      setRequiredFeatureString(TLBIP->getRequiredFeatures(), Str);
+      if (Missing.any())
+        setRequiredFeatureString(Missing, Str);
+
+      if (NeedD128OrTLBID) {
+        if (Missing.any())
+          Str += ", ";
+        Str += "tlbid or d128";
+      }
----------------
jthackray wrote:

Ah, I know what's happened. It's because until 5 months ago, we had a combined table for tlbi and tlbip, which I fixed in:
```
commit 2690bb6db
Author: Jonathan Thackray <jonathan.thackray at arm.com>
Date:   5 months ago

    [AArch64][llvm] Reject assembler for invalid TLBIP instructions (#162090)
```
and obviously didn't realise this at that point.

https://github.com/llvm/llvm-project/pull/178913