[llvm] [NFC][SPIRV] New test for untested SPIRVInstructionSelector case (PR #186069)
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Thu Mar 12 07:00:55 PDT 2026
https://github.com/ambergorzynski updated https://github.com/llvm/llvm-project/pull/186069
>From 00d9d883de870a354ef9da6e78a0a49b2370b338 Mon Sep 17 00:00:00 2001
From: agorzyns <amber.gorzynski at amd.com>
Date: Thu, 12 Mar 2026 03:50:20 -0500
Subject: [PATCH 1/5] [NFC][SPIRV] Add abort to demonstrate test
---
llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index 3e50e4a0e8c80..1d3ecbee08e48 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -2450,8 +2450,10 @@ static unsigned getPtrCmpOpcode(unsigned Pred) {
static unsigned getBoolCmpOpcode(unsigned PredNum) {
auto Pred = static_cast<CmpInst::Predicate>(PredNum);
switch (Pred) {
- case CmpInst::ICMP_EQ:
+ case CmpInst::ICMP_EQ: {
+ abort();
return SPIRV::OpLogicalEqual;
+ }
case CmpInst::ICMP_NE:
return SPIRV::OpLogicalNotEqual;
default:
>From 124097c941b9a729fae85bf3167de413d6350516 Mon Sep 17 00:00:00 2001
From: agorzyns <amber.gorzynski at amd.com>
Date: Thu, 12 Mar 2026 03:51:08 -0500
Subject: [PATCH 2/5] [NFC][SPIRV] Add test for untested
SPIRVInstructionSelector LogicalEq case
---
llvm/test/CodeGen/SPIRV/instructions/icmp.ll | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/llvm/test/CodeGen/SPIRV/instructions/icmp.ll b/llvm/test/CodeGen/SPIRV/instructions/icmp.ll
index 0d8778af9e5b0..13e4fd2d3d5f2 100644
--- a/llvm/test/CodeGen/SPIRV/instructions/icmp.ll
+++ b/llvm/test/CodeGen/SPIRV/instructions/icmp.ll
@@ -23,6 +23,7 @@
; CHECK-DAG: OpName [[v3UGE:%.*]] "test_v3_uge"
; CHECK-DAG: OpName [[v3SGE:%.*]] "test_v3_sge"
; CHECK-DAG: OpName [[v16NE:%.*]] "test_v16_ne"
+; CHECK-DAG: OpName [[v16EQ:%.*]] "test_v16_eq"
; CHECK: [[EQ]] = OpFunction
; CHECK-NEXT: [[A:%.*]] = OpFunctionParameter
@@ -274,3 +275,14 @@ define spir_func <16 x i1> @test_v16_ne() {
%A = icmp ne <16 x i1> zeroinitializer, zeroinitializer
ret <16 x i1> %A
}
+
+; CHECK: [[v16EQ]] = OpFunction
+; CHECK-NEXT: OpLabel
+; CHECK-NEXT: [[R:%.*]] = OpLogicalEqual {{%.+}} {{%.*}} {{%.*}}
+; CHECK-NEXT: OpReturnValue [[R]]
+; CHECK-NEXT: OpFunctionEnd
+define spir_func <16 x i1> @test_v16_eq() {
+entry:
+ %A = icmp eq <16 x i1> zeroinitializer, zeroinitializer
+ ret <16 x i1> %A
+}
>From f0623843cd06ea7238256dc83acecca9a2f23a9f Mon Sep 17 00:00:00 2001
From: agorzyns <amber.gorzynski at amd.com>
Date: Thu, 12 Mar 2026 06:10:58 -0500
Subject: [PATCH 3/5] [NFC][SPIRV] Remove abort
---
llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index 1d3ecbee08e48..8fb4e8f4a1b69 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -2450,10 +2450,8 @@ static unsigned getPtrCmpOpcode(unsigned Pred) {
static unsigned getBoolCmpOpcode(unsigned PredNum) {
auto Pred = static_cast<CmpInst::Predicate>(PredNum);
switch (Pred) {
- case CmpInst::ICMP_EQ: {
- abort();
+ case CmpInst::ICMP_EQ:
return SPIRV::OpLogicalEqual;
- }
case CmpInst::ICMP_NE:
return SPIRV::OpLogicalNotEqual;
default:
>From f9db5f552474b92634df25238d49bb43767d0d98 Mon Sep 17 00:00:00 2001
From: agorzyns <amber.gorzynski at amd.com>
Date: Thu, 12 Mar 2026 07:00:29 -0500
Subject: [PATCH 4/5] [NFC][SPIRV] Fix format
---
llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index 8fb4e8f4a1b69..3e50e4a0e8c80 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -2450,7 +2450,7 @@ static unsigned getPtrCmpOpcode(unsigned Pred) {
static unsigned getBoolCmpOpcode(unsigned PredNum) {
auto Pred = static_cast<CmpInst::Predicate>(PredNum);
switch (Pred) {
- case CmpInst::ICMP_EQ:
+ case CmpInst::ICMP_EQ:
return SPIRV::OpLogicalEqual;
case CmpInst::ICMP_NE:
return SPIRV::OpLogicalNotEqual;
>From 843d6e5a39abdc9b83e5d6c75e8ae3518fcb3ab8 Mon Sep 17 00:00:00 2001
From: agorzyns <amber.gorzynski at amd.com>
Date: Thu, 12 Mar 2026 08:58:19 -0500
Subject: [PATCH 5/5] [review] Rename test cases
---
llvm/test/CodeGen/SPIRV/instructions/icmp.ll | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/llvm/test/CodeGen/SPIRV/instructions/icmp.ll b/llvm/test/CodeGen/SPIRV/instructions/icmp.ll
index 13e4fd2d3d5f2..ccf0608753f2e 100644
--- a/llvm/test/CodeGen/SPIRV/instructions/icmp.ll
+++ b/llvm/test/CodeGen/SPIRV/instructions/icmp.ll
@@ -22,8 +22,9 @@
; CHECK-DAG: OpName [[v3SGT:%.*]] "test_v3_sgt"
; CHECK-DAG: OpName [[v3UGE:%.*]] "test_v3_uge"
; CHECK-DAG: OpName [[v3SGE:%.*]] "test_v3_sge"
-; CHECK-DAG: OpName [[v16NE:%.*]] "test_v16_ne"
-; CHECK-DAG: OpName [[v16EQ:%.*]] "test_v16_eq"
+
+; CHECK-DAG: OpName [[v16NE:%.*]] "test_boolean_v16_ne"
+; CHECK-DAG: OpName [[v16EQ:%.*]] "test_boolean_v16_eq"
; CHECK: [[EQ]] = OpFunction
; CHECK-NEXT: [[A:%.*]] = OpFunctionParameter
@@ -271,7 +272,7 @@ define <3 x i1> @test_v3_sge(<3 x i32> %a, <3 x i32> %b) {
; CHECK-NEXT: OpReturnValue [[R]]
; CHECK-NEXT: OpFunctionEnd
-define spir_func <16 x i1> @test_v16_ne() {
+define spir_func <16 x i1> @test_boolean_v16_ne() {
%A = icmp ne <16 x i1> zeroinitializer, zeroinitializer
ret <16 x i1> %A
}
@@ -281,7 +282,7 @@ define spir_func <16 x i1> @test_v16_ne() {
; CHECK-NEXT: [[R:%.*]] = OpLogicalEqual {{%.+}} {{%.*}} {{%.*}}
; CHECK-NEXT: OpReturnValue [[R]]
; CHECK-NEXT: OpFunctionEnd
-define spir_func <16 x i1> @test_v16_eq() {
+define spir_func <16 x i1> @test_boolean_v16_eq() {
entry:
%A = icmp eq <16 x i1> zeroinitializer, zeroinitializer
ret <16 x i1> %A
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