[lldb] [llvm] [AArch64][llvm] Tighten SYSP parsing; don't disassemble invalid encodings (PR #182410)

[Jonathan Thackray via llvm-commits]

================
@@ -11384,11 +11384,14 @@ let Predicates = [HasRCPC3, HasNEON] in {
 //===----------------------------------------------------------------------===//
 // 128-bit System Instructions (FEAT_SYSINSTR128)
 //===----------------------------------------------------------------------===//
-def SYSPxt  : SystemPXtI<0, "sysp">;
+def SYSPxt  : SystemPXtI<0, "sysp"> {
----------------
jthackray wrote:

https://armv8.arm.com/v8-A/A_profile_FAT/isa64/ISA_A64_xml_A_profile_FAT-2025-09_ASL0/sysp.xml says:
```
if Rt<0> == '1' && Rt != '11111' then [EndOfDecode]
```
i.e. bit 0 must be 1. This is already tested in `llvm/test/MC/AArch64/armv9a-sysp.s` where it has:
```
sysp #0, c2, c0, #0, x2, x3
// CHECK-INST: sysp #0, c2, c0, #0, x2, x3
// CHECK-ENCODING: encoding: [0x02,0x20,0x48,0xd5]

sysp #0, c2, c0, #0, x4, x5
// CHECK-INST: sysp #0, c2, c0, #0, x4, x5
// CHECK-ENCODING: encoding: [0x04,0x20,0x48,0xd5]

sysp #0, c2, c0, #0, x6, x7
// CHECK-INST: sysp #0, c2, c0, #0, x6, x7
// CHECK-ENCODING: encoding: [0x06,0x20,0x48,0xd5]
```
etc.

https://github.com/llvm/llvm-project/pull/182410