[lldb] [llvm] [AArch64][llvm] Tighten SYSP parsing; don't disassemble invalid encodings (PR #182410)

[via llvm-commits]

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@@ -1387,21 +1387,28 @@ DecodeXSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
       Inst, AArch64::XSeqPairsClassRegClassID, RegNo, Addr, Decoder);
 }
 
-static DecodeStatus DecodeSyspXzrInstruction(MCInst &Inst, uint32_t insn,
-                                             uint64_t Addr,
-                                             const MCDisassembler *Decoder) {
+static DecodeStatus DecodeSyspInstruction(MCInst &Inst, uint32_t insn,
+                                          uint64_t Addr,
+                                          const MCDisassembler *Decoder) {
   unsigned op1 = fieldFromInstruction(insn, 16, 3);
   unsigned CRn = fieldFromInstruction(insn, 12, 4);
   unsigned CRm = fieldFromInstruction(insn, 8, 4);
   unsigned op2 = fieldFromInstruction(insn, 5, 3);
   unsigned Rt = fieldFromInstruction(insn, 0, 5);
-  if (Rt != 0b11111)
+
+  if (op1 > 6 || (CRn != 8 && CRn != 9) || CRm > 7 || op2 > 7)
+    return Fail;
+
+  // SYSP register pairs follow the same encoding constraints as XSeqPairsClass:
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Lukacma wrote:

They don't unfortunately :(

https://github.com/llvm/llvm-project/pull/182410