[llvm] [WebAssembly] Fold sign-extending shifts into signed loads in FastISel (PR #185906)

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git-clang-format --diff origin/main HEAD --extensions cpp -- llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp --diff_from_common_commit
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``````````diff
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp
index 2446c5ed5..fe80eb1d2 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp
@@ -1370,7 +1370,8 @@ static unsigned getFoldedLoadOpcode(MachineInstr *MI, MachineRegisterInfo &MRI,
   }
 }
 
-/// Matches a sign-extension pattern (shl + shr_s) to fold it into a signed load.
+/// Matches a sign-extension pattern (shl + shr_s) to fold it into a signed
+/// load.
 ///
 /// FastISel assumes that 'sext' from i8 or i16 will first be lowered to a
 /// 32-bit zero-extending load (i32.load8_u / i32.load16_u) followed by 32-bit

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https://github.com/llvm/llvm-project/pull/185906