[llvm] [RISCV] Add register group overlap checks to the assembler for vector indexed segment load (PR #184963)

[Luke Lau via llvm-commits]

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@@ -3874,10 +3944,16 @@ bool RISCVAsmParser::validateInstruction(MCInst &Inst,
     assert(VS2Idx >= 0 && "No vs2 operand?");
     unsigned CheckEncoding =
         RI->getEncodingValue(Inst.getOperand(VS2Idx).getReg());
+    unsigned NF = getNFforLXSEG(Opcode);
     for (unsigned i = 0; i < Lmul; i++) {
-      if ((DestEncoding + i) == CheckEncoding)
-        return Error(Loc, "the destination vector register group cannot overlap"
-                          " the source vector register group");
+      if (NF == 1 && (DestEncoding + i) == CheckEncoding)
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lukel97 wrote:

Why do we need to limit this to NF==1? I think lmul will always be 1 for the segmented instructions

https://github.com/llvm/llvm-project/pull/184963