[llvm] [RISCV] Disable use of scalable vectors for VLEN=32 (PR #185553)

[Craig Topper via llvm-commits]

topperc wrote:

> > > > > LGTM. Does the fixed vector codegen work ok with zvl32b? Fixed vectors get legalized to scalable vectors, I'm not sure if that will generate more uses of vscale.
> > > > 
> > > > 
> > > > The loop vectorizer doesn’t introduce `vscale` for fixed-width vectors, so we don’t expect codegen to generate any additional `vscale` uses during lowering.
> > > 
> > > 
> > > I mean as in new uses of vscale in the RISC-V backend. I think some legalizations of permutation ops e.g. vector_reverse need to read vscale/vlen etc.
> > 
> > 
> > Wouldn't we be legalizing a fixed vector vector_vector reverse? That shouldn't use vscale, it should use the fixed size since only the lower elements should be reversed.
> 
> Looks like reverse of fixed i1 vectors does use vscale. At least according to the `reverse_v32i1` test from fixed-vectors-shuffle-reverse.ll

Oh useRVVForFixedLengthVectors() returns false for Zve32x with VLEN=32.

```
bool RISCVSubtarget::useRVVForFixedLengthVectors() const {                       
  return hasVInstructions() &&                                                   
         getMinRVVVectorSizeInBits() >= RISCV::RVVBitsPerBlock;                  
}                                                                                
```

https://github.com/llvm/llvm-project/pull/185553