[llvm] [MIR] Support symbolic inline asm operands (PR #185893)
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Wed Mar 11 07:53:02 PDT 2026
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Ivan Kosarev (kosarev)
<details>
<summary>Changes</summary>
Support parsing and printing inline assembly operands in MIR using the symbolic form instead of numeric register class IDs, thus removing the need to update tests when the numbers change.
The numeric form remains supported.
---
Full diff: https://github.com/llvm/llvm-project/pull/185893.diff
3 Files Affected:
- (modified) llvm/lib/CodeGen/MIRParser/MIParser.cpp (+109)
- (modified) llvm/lib/CodeGen/MIRPrinter.cpp (+25)
- (modified) llvm/test/CodeGen/AMDGPU/dst-sel-hazard.mir (+16-16)
``````````diff
diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
index c1ad33bf5efb7..5a589f86b6cf9 100644
--- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
@@ -46,6 +46,7 @@
#include "llvm/IR/DebugInfoMetadata.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/Function.h"
+#include "llvm/IR/InlineAsm.h"
#include "llvm/IR/InstrTypes.h"
#include "llvm/IR/Instructions.h"
#include "llvm/IR/Intrinsics.h"
@@ -460,6 +461,7 @@ class MIParser {
std::optional<unsigned> &TiedDefIdx,
bool IsDef = false);
bool parseImmediateOperand(MachineOperand &Dest);
+ bool parseInlineAsmOperand(MachineOperand &Dest);
bool parseIRConstant(StringRef::iterator Loc, StringRef StringValue,
const Constant *&C);
bool parseIRConstant(StringRef::iterator Loc, const Constant *&C);
@@ -1901,6 +1903,100 @@ bool MIParser::parseImmediateOperand(MachineOperand &Dest) {
return false;
}
+bool MIParser::parseInlineAsmOperand(MachineOperand &Dest) {
+ if (Token.is(MIToken::IntegerLiteral))
+ return parseImmediateOperand(Dest);
+
+ // Parse symbolic form: kind[:constraint].
+ if (Token.isNot(MIToken::Identifier))
+ return error("expected inline asm operand kind or integer literal");
+
+ StringRef KindStr = Token.stringValue();
+ constexpr auto InvalidKind = static_cast<InlineAsm::Kind>(0);
+ InlineAsm::Kind K =
+ StringSwitch<InlineAsm::Kind>(KindStr)
+ .Case("regdef", InlineAsm::Kind::RegDef)
+ .Case("reguse", InlineAsm::Kind::RegUse)
+ .Case("regdef-ec", InlineAsm::Kind::RegDefEarlyClobber)
+ .Case("clobber", InlineAsm::Kind::Clobber)
+ .Case("imm", InlineAsm::Kind::Imm)
+ .Case("mem", InlineAsm::Kind::Mem)
+ .Default(InvalidKind);
+
+ if (K == InvalidKind)
+ return error("unknown inline asm operand kind '" + KindStr + "'");
+
+ lex();
+
+ // Create the flag with default of 1 operand.
+ InlineAsm::Flag F(K, 1);
+
+ // Parse optional constraint after ':'.
+ if (Token.isNot(MIToken::colon)) {
+ Dest = MachineOperand::CreateImm(F);
+ return false;
+ }
+
+ lex();
+
+ if (Token.isNot(MIToken::Identifier))
+ return error("expected register class or memory constraint name after ':'");
+
+ StringRef ConstraintStr = Token.stringValue();
+
+ if (K == InlineAsm::Kind::Mem) {
+ InlineAsm::ConstraintCode CC =
+ StringSwitch<InlineAsm::ConstraintCode>(ConstraintStr)
+ .Case("es", InlineAsm::ConstraintCode::es)
+ .Case("i", InlineAsm::ConstraintCode::i)
+ .Case("k", InlineAsm::ConstraintCode::k)
+ .Case("m", InlineAsm::ConstraintCode::m)
+ .Case("o", InlineAsm::ConstraintCode::o)
+ .Case("v", InlineAsm::ConstraintCode::v)
+ .Case("A", InlineAsm::ConstraintCode::A)
+ .Case("Q", InlineAsm::ConstraintCode::Q)
+ .Case("R", InlineAsm::ConstraintCode::R)
+ .Case("S", InlineAsm::ConstraintCode::S)
+ .Case("T", InlineAsm::ConstraintCode::T)
+ .Case("Um", InlineAsm::ConstraintCode::Um)
+ .Case("Un", InlineAsm::ConstraintCode::Un)
+ .Case("Uq", InlineAsm::ConstraintCode::Uq)
+ .Case("Us", InlineAsm::ConstraintCode::Us)
+ .Case("Ut", InlineAsm::ConstraintCode::Ut)
+ .Case("Uv", InlineAsm::ConstraintCode::Uv)
+ .Case("Uy", InlineAsm::ConstraintCode::Uy)
+ .Case("X", InlineAsm::ConstraintCode::X)
+ .Case("Z", InlineAsm::ConstraintCode::Z)
+ .Case("ZB", InlineAsm::ConstraintCode::ZB)
+ .Case("ZC", InlineAsm::ConstraintCode::ZC)
+ .Case("Zy", InlineAsm::ConstraintCode::Zy)
+ .Case("p", InlineAsm::ConstraintCode::p)
+ .Case("ZQ", InlineAsm::ConstraintCode::ZQ)
+ .Case("ZR", InlineAsm::ConstraintCode::ZR)
+ .Case("ZS", InlineAsm::ConstraintCode::ZS)
+ .Case("ZT", InlineAsm::ConstraintCode::ZT)
+ .Default(InlineAsm::ConstraintCode::Unknown);
+
+ if (CC == InlineAsm::ConstraintCode::Unknown)
+ return error("unknown memory constraint '" + ConstraintStr + "'");
+
+ F.setMemConstraint(CC);
+ } else if (K == InlineAsm::Kind::RegDef || K == InlineAsm::Kind::RegUse ||
+ K == InlineAsm::Kind::RegDefEarlyClobber) {
+ const TargetRegisterClass *RC =
+ PFS.Target.getRegClass(ConstraintStr.lower());
+ if (!RC)
+ return error("unknown register class '" + ConstraintStr + "'");
+
+ F.setRegClass(RC->getID());
+ }
+
+ lex();
+
+ Dest = MachineOperand::CreateImm(F);
+ return false;
+}
+
bool MIParser::parseTargetImmMnemonic(const unsigned OpCode,
const unsigned OpIdx,
MachineOperand &Dest,
@@ -2980,6 +3076,17 @@ bool MIParser::parseLiveoutRegisterMaskOperand(MachineOperand &Dest) {
bool MIParser::parseMachineOperand(const unsigned OpCode, const unsigned OpIdx,
MachineOperand &Dest,
std::optional<unsigned> &TiedDefIdx) {
+ bool IsInlineAsmOperand = (OpCode == TargetOpcode::INLINEASM ||
+ OpCode == TargetOpcode::INLINEASM_BR) &&
+ OpIdx >= InlineAsm::MIOp_FirstOperand;
+
+ if (IsInlineAsmOperand && Token.is(MIToken::Identifier)) {
+ StringRef Id = Token.stringValue();
+ if (Id == "regdef" || Id == "reguse" || Id == "regdef-ec" ||
+ Id == "clobber" || Id == "imm" || Id == "mem")
+ return parseInlineAsmOperand(Dest);
+ }
+
switch (Token.kind()) {
case MIToken::kw_implicit:
case MIToken::kw_implicit_define:
@@ -2997,6 +3104,8 @@ bool MIParser::parseMachineOperand(const unsigned OpCode, const unsigned OpIdx,
case MIToken::NamedVirtualRegister:
return parseRegisterOperand(Dest, TiedDefIdx);
case MIToken::IntegerLiteral:
+ if (IsInlineAsmOperand)
+ return parseInlineAsmOperand(Dest);
return parseImmediateOperand(Dest);
case MIToken::kw_half:
case MIToken::kw_bfloat:
diff --git a/llvm/lib/CodeGen/MIRPrinter.cpp b/llvm/lib/CodeGen/MIRPrinter.cpp
index 7cba47c38b8fc..ea1cd09fd0518 100644
--- a/llvm/lib/CodeGen/MIRPrinter.cpp
+++ b/llvm/lib/CodeGen/MIRPrinter.cpp
@@ -42,6 +42,7 @@
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/IRPrintingPasses.h"
+#include "llvm/IR/InlineAsm.h"
#include "llvm/IR/Instructions.h"
#include "llvm/IR/Module.h"
#include "llvm/IR/ModuleSlotTracker.h"
@@ -73,6 +74,11 @@ static cl::opt<bool> SimplifyMIR(
static cl::opt<bool> PrintLocations("mir-debug-loc", cl::Hidden, cl::init(true),
cl::desc("Print MIR debug-locations"));
+static cl::opt<bool>
+ PrintSymbolicInlineAsmOps("print-symbolic-inline-asm-ops", cl::Hidden,
+ cl::init(false),
+ cl::desc("Print inline asm operands as names"));
+
namespace {
/// This structure describes how to print out stack object references.
@@ -967,6 +973,25 @@ static void printMIOperand(raw_ostream &OS, MFPrintState &State,
MachineOperand::printSubRegIdx(OS, Op.getImm(), TRI);
break;
}
+ if (PrintSymbolicInlineAsmOps && MI.isInlineAsm()) {
+ int FlagIdx = MI.findInlineAsmFlagIdx(OpIdx);
+ if (FlagIdx >= 0 && (unsigned)FlagIdx == OpIdx) {
+ InlineAsm::Flag F(Op.getImm());
+ OS << F.getKindName();
+
+ unsigned RCID;
+ if ((F.isRegDefKind() || F.isRegUseKind() ||
+ F.isRegDefEarlyClobberKind()) &&
+ F.hasRegClassConstraint(RCID))
+ OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID));
+
+ if (F.isMemKind()) {
+ InlineAsm::ConstraintCode MCID = F.getMemoryConstraintID();
+ OS << ":" << InlineAsm::getMemConstraintName(MCID);
+ }
+ break;
+ }
+ }
[[fallthrough]];
case MachineOperand::MO_Register:
case MachineOperand::MO_CImmediate:
diff --git a/llvm/test/CodeGen/AMDGPU/dst-sel-hazard.mir b/llvm/test/CodeGen/AMDGPU/dst-sel-hazard.mir
index 70d1d4f1e7b3c..77029d109a6be 100644
--- a/llvm/test/CodeGen/AMDGPU/dst-sel-hazard.mir
+++ b/llvm/test/CodeGen/AMDGPU/dst-sel-hazard.mir
@@ -1,9 +1,9 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-# RUN: llc -mtriple=amdgcn -mcpu=gfx942 -run-pass post-RA-hazard-rec -o - %s | FileCheck -check-prefix=HAZARD %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx9-4-generic -run-pass post-RA-hazard-rec -o - %s | FileCheck -check-prefix=HAZARD %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx90a -run-pass post-RA-hazard-rec -o - %s | FileCheck -check-prefix=NOHAZARD %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx942 -run-pass post-RA-hazard-rec -print-symbolic-inline-asm-ops -o - %s | FileCheck -check-prefix=HAZARD %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx9-4-generic -run-pass post-RA-hazard-rec -print-symbolic-inline-asm-ops -o - %s | FileCheck -check-prefix=HAZARD %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx90a -run-pass post-RA-hazard-rec -print-symbolic-inline-asm-ops -o - %s | FileCheck -check-prefix=NOHAZARD %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx90a -passes post-RA-hazard-rec -o - %s | FileCheck -check-prefix=NOHAZARD %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx90a -passes post-RA-hazard-rec -print-symbolic-inline-asm-ops -o - %s | FileCheck -check-prefix=NOHAZARD %s
---
name: sdwa_opsel_hazard
@@ -370,7 +370,7 @@ body: |
; HAZARD-LABEL: name: inline_sdwa_hazard
; HAZARD: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $exec, $mode
; HAZARD-NEXT: {{ $}}
- ; HAZARD-NEXT: INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, 1179658 /* regdef:VGPR_32 */, def $vgpr0, 1179657 /* reguse:VGPR_32 */, $vgpr1
+ ; HAZARD-NEXT: INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, regdef:VGPR_32, def $vgpr0, reguse:VGPR_32, $vgpr1
; HAZARD-NEXT: S_NOP 0
; HAZARD-NEXT: renamable $vgpr0 = V_ADD_U16_sdwa 0, $vgpr1, 0, $vgpr2, 0, 1, 0, 3, 3, implicit $exec, implicit killed $vgpr0(tied-def 0)
; HAZARD-NEXT: S_ENDPGM 0
@@ -378,10 +378,10 @@ body: |
; NOHAZARD-LABEL: name: inline_sdwa_hazard
; NOHAZARD: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $exec, $mode
; NOHAZARD-NEXT: {{ $}}
- ; NOHAZARD-NEXT: INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, 1179658 /* regdef:VGPR_32 */, def $vgpr0, 1179657 /* reguse:VGPR_32 */, $vgpr1
+ ; NOHAZARD-NEXT: INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, regdef:VGPR_32, def $vgpr0, reguse:VGPR_32, $vgpr1
; NOHAZARD-NEXT: renamable $vgpr0 = V_ADD_U16_sdwa 0, $vgpr1, 0, $vgpr2, 0, 1, 0, 3, 3, implicit $exec, implicit killed $vgpr0(tied-def 0)
; NOHAZARD-NEXT: S_ENDPGM 0
- INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, 1179658 /* regdef:VGPR_32 */, def $vgpr0, 1179657 /* reguse:VGPR_32 */, $vgpr1
+ INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, regdef:VGPR_32, def $vgpr0, reguse:VGPR_32, $vgpr1
renamable $vgpr0 = V_ADD_U16_sdwa 0, $vgpr1, 0, $vgpr2, 0, 1, 0, 3, 3, implicit $exec, implicit killed $vgpr0(tied-def 0)
S_ENDPGM 0
...
@@ -397,17 +397,17 @@ body: |
; HAZARD-NEXT: {{ $}}
; HAZARD-NEXT: renamable $vgpr0 = V_ADD_U16_sdwa 0, $vgpr1, 0, $vgpr2, 0, 1, 0, 3, 3, implicit $exec, implicit killed $vgpr0(tied-def 0)
; HAZARD-NEXT: S_NOP 0
- ; HAZARD-NEXT: INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, 1179658 /* regdef:VGPR_32 */, def $vgpr0, 1179657 /* reguse:VGPR_32 */, $vgpr1
+ ; HAZARD-NEXT: INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, regdef:VGPR_32, def $vgpr0, reguse:VGPR_32, $vgpr1
; HAZARD-NEXT: S_ENDPGM 0
;
; NOHAZARD-LABEL: name: sdwa_inline_hazard
; NOHAZARD: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $exec, $mode
; NOHAZARD-NEXT: {{ $}}
; NOHAZARD-NEXT: renamable $vgpr0 = V_ADD_U16_sdwa 0, $vgpr1, 0, $vgpr2, 0, 1, 0, 3, 3, implicit $exec, implicit killed $vgpr0(tied-def 0)
- ; NOHAZARD-NEXT: INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, 1179658 /* regdef:VGPR_32 */, def $vgpr0, 1179657 /* reguse:VGPR_32 */, $vgpr1
+ ; NOHAZARD-NEXT: INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, regdef:VGPR_32, def $vgpr0, reguse:VGPR_32, $vgpr1
; NOHAZARD-NEXT: S_ENDPGM 0
renamable $vgpr0 = V_ADD_U16_sdwa 0, $vgpr1, 0, $vgpr2, 0, 1, 0, 3, 3, implicit $exec, implicit killed $vgpr0(tied-def 0)
- INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, 1179658 /* regdef:VGPR_32 */, def $vgpr0, 1179657 /* reguse:VGPR_32 */, $vgpr1
+ INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, regdef:VGPR_32, def $vgpr0, reguse:VGPR_32, $vgpr1
S_ENDPGM 0
...
@@ -421,19 +421,19 @@ body: |
; HAZARD-LABEL: name: inline_inline_hazard
; HAZARD: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $exec, $mode
; HAZARD-NEXT: {{ $}}
- ; HAZARD-NEXT: INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, 1179658 /* regdef:VGPR_32 */, def $vgpr0, 1179657 /* reguse:VGPR_32 */, $vgpr1
+ ; HAZARD-NEXT: INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, regdef:VGPR_32, def $vgpr0, reguse:VGPR_32, $vgpr1
; HAZARD-NEXT: S_NOP 0
- ; HAZARD-NEXT: INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, 1179658 /* regdef:VGPR_32 */, def $vgpr0, 1179657 /* reguse:VGPR_32 */, $vgpr1
+ ; HAZARD-NEXT: INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, regdef:VGPR_32, def $vgpr0, reguse:VGPR_32, $vgpr1
; HAZARD-NEXT: S_ENDPGM 0
;
; NOHAZARD-LABEL: name: inline_inline_hazard
; NOHAZARD: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $exec, $mode
; NOHAZARD-NEXT: {{ $}}
- ; NOHAZARD-NEXT: INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, 1179658 /* regdef:VGPR_32 */, def $vgpr0, 1179657 /* reguse:VGPR_32 */, $vgpr1
- ; NOHAZARD-NEXT: INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, 1179658 /* regdef:VGPR_32 */, def $vgpr0, 1179657 /* reguse:VGPR_32 */, $vgpr1
+ ; NOHAZARD-NEXT: INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, regdef:VGPR_32, def $vgpr0, reguse:VGPR_32, $vgpr1
+ ; NOHAZARD-NEXT: INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, regdef:VGPR_32, def $vgpr0, reguse:VGPR_32, $vgpr1
; NOHAZARD-NEXT: S_ENDPGM 0
- INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, 1179658 /* regdef:VGPR_32 */, def $vgpr0, 1179657 /* reguse:VGPR_32 */, $vgpr1
- INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, 1179658 /* regdef:VGPR_32 */, def $vgpr0, 1179657 /* reguse:VGPR_32 */, $vgpr1
+ INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, regdef:VGPR_32, def $vgpr0, reguse:VGPR_32, $vgpr1
+ INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, regdef:VGPR_32, def $vgpr0, reguse:VGPR_32, $vgpr1
S_ENDPGM 0
...
``````````
</details>
https://github.com/llvm/llvm-project/pull/185893
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