[llvm] 737c19d - [ARM] Use FPRegs for fastcc calling convention detection. (#184593)

[via llvm-commits]

Author: David Green
Date: 2026-03-11T13:52:56Z
New Revision: 737c19dc1b748f02be8e7c1913c9f7604b2bde85

URL: https://github.com/llvm/llvm-project/commit/737c19dc1b748f02be8e7c1913c9f7604b2bde85
DIFF: https://github.com/llvm/llvm-project/commit/737c19dc1b748f02be8e7c1913c9f7604b2bde85.diff

LOG: [ARM] Use FPRegs for fastcc calling convention detection. (#184593)

This was using VFP2, but nowadays should use hasFPRegs to detect the
effective calling convention.

Fixes #109922.

Added: 
    llvm/test/CodeGen/Thumb2/mve-fastcc.ll

Modified: 
    llvm/lib/Target/ARM/ARMFastISel.cpp
    llvm/lib/Target/ARM/ARMISelLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/ARM/ARMFastISel.cpp b/llvm/lib/Target/ARM/ARMFastISel.cpp
index c24421ce6b658..9070873640afb 100644
--- a/llvm/lib/Target/ARM/ARMFastISel.cpp
+++ b/llvm/lib/Target/ARM/ARMFastISel.cpp
@@ -1897,7 +1897,7 @@ CCAssignFn *ARMFastISel::CCAssignFnForCall(CallingConv::ID CC,
   default:
     report_fatal_error("Unsupported calling convention");
   case CallingConv::Fast:
-    if (Subtarget->hasVFP2Base() && !isVarArg) {
+    if (Subtarget->hasFPRegs() && !isVarArg) {
       if (!TM.isAAPCS_ABI())
         return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
       // For AAPCS ABI targets, just use VFP variant of the calling convention.

diff  --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index d4f01d0c5879f..0d39c4cb2f581 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -1714,10 +1714,10 @@ ARMTargetLowering::getEffectiveCallingConv(CallingConv::ID CC,
   case CallingConv::Fast:
   case CallingConv::CXX_FAST_TLS:
     if (!getTM().isAAPCS_ABI()) {
-      if (Subtarget->hasVFP2Base() && !Subtarget->isThumb1Only() && !isVarArg)
+      if (Subtarget->hasFPRegs() && !Subtarget->isThumb1Only() && !isVarArg)
         return CallingConv::Fast;
       return CallingConv::ARM_APCS;
-    } else if (Subtarget->hasVFP2Base() && !Subtarget->isThumb1Only() &&
+    } else if (Subtarget->hasFPRegs() && !Subtarget->isThumb1Only() &&
                !isVarArg)
       return CallingConv::ARM_AAPCS_VFP;
     else

diff  --git a/llvm/test/CodeGen/Thumb2/mve-fastcc.ll b/llvm/test/CodeGen/Thumb2/mve-fastcc.ll
new file mode 100644
index 0000000000000..fe5ae29954346
--- /dev/null
+++ b/llvm/test/CodeGen/Thumb2/mve-fastcc.ll
@@ -0,0 +1,42 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabihf -mattr=+mve -fast-isel -verify-machineinstrs %s -o - | FileCheck %s
+; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabihf -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s
+
+%struct.S51 = type { <16 x i8>, <16 x i8> }
+
+define fastcc <4 x i32> @fastcc_zero() {
+; CHECK-LABEL: fastcc_zero:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmov.i32 q0, #0x0
+; CHECK-NEXT:    bx lr
+entry:
+  ret <4 x i32> zeroinitializer
+}
+
+define fastcc <4 x i32> @fastcc_retsecond(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: fastcc_retsecond:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmov q0, q1
+; CHECK-NEXT:    bx lr
+entry:
+  ret <4 x i32> %b
+}
+
+define internal %struct.S51 @F33() {
+; CHECK-LABEL: F33:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmov.i32 q0, #0x0
+; CHECK-NEXT:    vmov.i32 q1, #0x0
+; CHECK-NEXT:    bx lr
+entry:
+  ret %struct.S51 zeroinitializer
+}
+
+define internal fastcc void @F32() {
+; CHECK-LABEL: F32:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    b F33
+entry:
+  %call = tail call %struct.S51 @F33()
+  ret void
+}