[llvm] [TableGen] Fix MUL case in DAG default operands test (PR #185847)

[Jay Foad via llvm-commits]

https://github.com/jayfoad created https://github.com/llvm/llvm-project/pull/185847

None

>From 1a69fa4e156df84e5f222fd558fc9adbce9aed95 Mon Sep 17 00:00:00 2001
From: Jay Foad <jay.foad at amd.com>
Date: Wed, 11 Mar 2026 09:55:49 +0000
Subject: [PATCH] [TableGen] Fix MUL case in DAG default operands test

---
 llvm/test/TableGen/DAGDefaultOps.td | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/llvm/test/TableGen/DAGDefaultOps.td b/llvm/test/TableGen/DAGDefaultOps.td
index 78cc58fcf9790..8c7e3de58b734 100644
--- a/llvm/test/TableGen/DAGDefaultOps.td
+++ b/llvm/test/TableGen/DAGDefaultOps.td
@@ -3,6 +3,7 @@
 // RUN: FileCheck --check-prefix=ADDINT %s < %t
 // RUN: FileCheck --check-prefix=SUB %s < %t
 // RUN: FileCheck --check-prefix=MULINT %s < %t
+// RUN: FileCheck --check-prefix=MUL %s < %t
 
 include "llvm/Target/Target.td"
 
@@ -102,7 +103,7 @@ def MulIRRPat : Pat<(mul i32:$x, i32:$y), (MulIRR Reg:$x, Reg:$y)>;
 // MULINT-NEXT: OPC_MorphNodeTo1Chain, TARGET_VAL(::MulRRI)
 
 // MUL: SwitchOpcode{{.*}}TARGET_VAL(ISD::MUL)
-// MUL-NEXT: OPC_EmitIntegerI32, 0
 // MUL-NEXT: OPC_RecordChild0
 // MUL-NEXT: OPC_RecordChild1
-// MUL-NEXT: OPC_MorphNodeTo1Chain, TARGET_VAL(::MulRRI)
+// MUL-NEXT: OPC_EmitIntegerI32, 0
+// MUL-NEXT: OPC_MorphNodeTo1None, TARGET_VAL(::MulIRR)