[llvm] [AMDGPU] Multi dword spilling for unaligned tuples (PR #183701)

[via llvm-commits]

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@@ -1732,10 +1746,31 @@ void SIRegisterInfo::buildSpillLoadStore(
 
   for (unsigned i = 0, e = NumSubRegs + NumRemSubRegs, RegOffset = 0; i != e;
        ++i, RegOffset += EltSize) {
-    if (i == NumSubRegs) {
-      EltSize = RemSize;
+    unsigned SavedEltSize = EltSize;
+    if (i == 0 && IsRegMisaligned) {
+      // For misaligned register tuples, spill only the first sub-reg in the
+      // first iteration.
+      EltSize = 4u;
       LoadStoreOp = getFlatScratchSpillOpcode(TII, LoadStoreOp, EltSize);
     }
+    if (i == 1 && IsRegMisaligned) {
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easyonaadit wrote:

Yupp got it.

https://github.com/llvm/llvm-project/pull/183701