[llvm] [NewPM] Port AArch64CollectLOHPass (PR #185789)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-aarch64

Author: Anshul Nigham (nigham)

<details>
<summary>Changes</summary>



---
Full diff: https://github.com/llvm/llvm-project/pull/185789.diff


4 Files Affected:

- (modified) llvm/lib/Target/AArch64/AArch64.h (+7-1) 
- (modified) llvm/lib/Target/AArch64/AArch64CollectLOH.cpp (+30-11) 
- (modified) llvm/lib/Target/AArch64/AArch64PassRegistry.def (+1) 
- (modified) llvm/lib/Target/AArch64/AArch64TargetMachine.cpp (+1-1) 


``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64.h b/llvm/lib/Target/AArch64/AArch64.h
index ca9a78114158e..aa8ba0600fed5 100644
--- a/llvm/lib/Target/AArch64/AArch64.h
+++ b/llvm/lib/Target/AArch64/AArch64.h
@@ -87,7 +87,7 @@ void initializeAArch64AsmPrinterPass(PassRegistry &);
 void initializeAArch64PointerAuthPass(PassRegistry&);
 void initializeAArch64BranchTargetsLegacyPass(PassRegistry &);
 void initializeAArch64CFIFixupPass(PassRegistry&);
-void initializeAArch64CollectLOHPass(PassRegistry &);
+void initializeAArch64CollectLOHLegacyPass(PassRegistry &);
 void initializeAArch64CompressJumpTablesPass(PassRegistry&);
 void initializeAArch64CondBrTuningPass(PassRegistry &);
 void initializeAArch64ConditionOptimizerPass(PassRegistry&);
@@ -149,6 +149,12 @@ class AArch64AdvSIMDScalarPass
                         MachineFunctionAnalysisManager &MFAM);
 };
 
+class AArch64CollectLOHPass : public PassInfoMixin<AArch64CollectLOHPass> {
+public:
+  PreservedAnalyses run(MachineFunction &MF,
+                        MachineFunctionAnalysisManager &MFAM);
+};
+
 } // end namespace llvm
 
 #endif
diff --git a/llvm/lib/Target/AArch64/AArch64CollectLOH.cpp b/llvm/lib/Target/AArch64/AArch64CollectLOH.cpp
index 069147a1b669b..fe77e3e49013d 100644
--- a/llvm/lib/Target/AArch64/AArch64CollectLOH.cpp
+++ b/llvm/lib/Target/AArch64/AArch64CollectLOH.cpp
@@ -84,7 +84,8 @@
 // This LOH aims at getting rid of redundant ADRP instructions.
 //
 // The overall design for emitting the LOHs is:
-// 1. AArch64CollectLOH (this pass) records the LOHs in the AArch64FunctionInfo.
+// 1. AArch64CollectLOHLegacy (this pass) records the LOHs in the
+// AArch64FunctionInfo.
 // 2. AArch64AsmPrinter reads the LOHs from AArch64FunctionInfo and it:
 //     1. Associates them a label.
 //     2. Emits them in a MCStreamer (EmitLOHDirective).
@@ -125,11 +126,21 @@ STATISTIC(NumADRSimpleCandidate, "Number of simplifiable ADRP + ADD");
 
 namespace {
 
-struct AArch64CollectLOH : public MachineFunctionPass {
+struct AArch64CollectLOHImpl {
+  bool run(MachineFunction &MF);
+};
+
+struct AArch64CollectLOHLegacy : public MachineFunctionPass {
   static char ID;
-  AArch64CollectLOH() : MachineFunctionPass(ID) {}
+  AArch64CollectLOHLegacy() : MachineFunctionPass(ID) {
+    initializeAArch64CollectLOHLegacyPass(*PassRegistry::getPassRegistry());
+  }
 
-  bool runOnMachineFunction(MachineFunction &MF) override;
+  bool runOnMachineFunction(MachineFunction &MF) override {
+    if (skipFunction(MF.getFunction()))
+      return false;
+    return AArch64CollectLOHImpl().run(MF);
+  }
 
   MachineFunctionProperties getRequiredProperties() const override {
     return MachineFunctionProperties().setNoVRegs();
@@ -143,11 +154,11 @@ struct AArch64CollectLOH : public MachineFunctionPass {
   }
 };
 
-char AArch64CollectLOH::ID = 0;
+char AArch64CollectLOHLegacy::ID = 0;
 
 } // end anonymous namespace.
 
-INITIALIZE_PASS(AArch64CollectLOH, "aarch64-collect-loh",
+INITIALIZE_PASS(AArch64CollectLOHLegacy, "aarch64-collect-loh",
                 AARCH64_COLLECT_LOH_NAME, false, false)
 
 static bool canAddBePartOfLOH(const MachineInstr &MI) {
@@ -536,10 +547,7 @@ static void handleNormalInst(const MachineInstr &MI, LOHInfo *LOHInfos) {
   }
 }
 
-bool AArch64CollectLOH::runOnMachineFunction(MachineFunction &MF) {
-  if (skipFunction(MF.getFunction()))
-    return false;
-
+bool AArch64CollectLOHImpl::run(MachineFunction &MF) {
   LLVM_DEBUG(dbgs() << "********** AArch64 Collect LOH **********\n"
                     << "Looking in function " << MF.getName() << '\n');
 
@@ -595,6 +603,17 @@ bool AArch64CollectLOH::runOnMachineFunction(MachineFunction &MF) {
   return false;
 }
 
+PreservedAnalyses
+AArch64CollectLOHPass::run(MachineFunction &MF,
+                           MachineFunctionAnalysisManager &MFAM) {
+  bool Changed = AArch64CollectLOHImpl().run(MF);
+  if (!Changed)
+    return PreservedAnalyses::all();
+  PreservedAnalyses PA = getMachineFunctionPassPreservedAnalyses();
+  PA.preserveSet<CFGAnalyses>();
+  return PA;
+}
+
 FunctionPass *llvm::createAArch64CollectLOHPass() {
-  return new AArch64CollectLOH();
+  return new AArch64CollectLOHLegacy();
 }
diff --git a/llvm/lib/Target/AArch64/AArch64PassRegistry.def b/llvm/lib/Target/AArch64/AArch64PassRegistry.def
index 47e6130d6891b..de1f08025edbc 100644
--- a/llvm/lib/Target/AArch64/AArch64PassRegistry.def
+++ b/llvm/lib/Target/AArch64/AArch64PassRegistry.def
@@ -27,6 +27,7 @@
 #define MACHINE_FUNCTION_PASS(NAME, CREATE_PASS)
 #endif
 MACHINE_FUNCTION_PASS("aarch64-branch-targets", AArch64BranchTargetsPass())
+MACHINE_FUNCTION_PASS("aarch64-collect-loh", AArch64CollectLOHPass())
 MACHINE_FUNCTION_PASS("aarch64-fix-cortex-a53-835769", AArch64A53Fix835769Pass())
 MACHINE_FUNCTION_PASS("aarch64-ldst-opt", AArch64LoadStoreOptPass())
 MACHINE_FUNCTION_PASS("aarch64-simd-scalar", AArch64AdvSIMDScalarPass())
diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
index 45d01c7d3ae93..4c2caab8c8cd3 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
@@ -248,7 +248,7 @@ LLVMInitializeAArch64Target() {
   initializeAArch64AdvSIMDScalarLegacyPass(PR);
   initializeAArch64AsmPrinterPass(PR);
   initializeAArch64BranchTargetsLegacyPass(PR);
-  initializeAArch64CollectLOHPass(PR);
+  initializeAArch64CollectLOHLegacyPass(PR);
   initializeAArch64CompressJumpTablesPass(PR);
   initializeAArch64ConditionalComparesPass(PR);
   initializeAArch64ConditionOptimizerPass(PR);

``````````

</details>


https://github.com/llvm/llvm-project/pull/185789