[clang] [llvm] [RISCV][MC] Add support of Zvzip extension (PR #185614)

[Craig Topper via llvm-commits]

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@@ -0,0 +1,28 @@
+//===---- RISCVInstrInfoZvzip.td - 'Zvzip' instructions ----*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the RISC-V instructions from the Zvzip standard extension
+// for reordering structured data in vector registers.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasStdExtZvzip], Constraints = "@earlyclobber $vd" in {
+  let VS1VS2Constraint = WidenV in {
+    def VZIP_VV : VALUVV<0b111110, OPMVV, "vzip.vv">;
+    def VUNZIPE_V : VALUVs2<0b010010, 0b01011, OPMVV, "vunzipe.v">;
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topperc wrote:

Can you put `VS1VS2Constraint = VS2Constraint` on the vunzip instructions. They don't have a vs1 operand so really shouldn't have a vs1 constraint.

https://github.com/llvm/llvm-project/pull/185614