[llvm] [TableGen] Do not order register classes based on heap addresses (PR #185644)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-tablegen

Author: Ivan Kosarev (kosarev)

<details>
<summary>Changes</summary>

Compare registers using their enum values instead, which I suspect was the intention in the first place, since we already have lexicographical ordering defined for CodeGenRegisters.

This does not cause any changes in .inc files and is likely NFC, but it's still best to have it be deterministic.

---
Full diff: https://github.com/llvm/llvm-project/pull/185644.diff


2 Files Affected:

- (modified) llvm/utils/TableGen/Common/CodeGenRegisters.cpp (+5-8) 
- (modified) llvm/utils/TableGen/Common/CodeGenRegisters.h (+4) 


``````````diff
diff --git a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
index fcd85cea6ffac..a55d035ebaae5 100644
--- a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
@@ -844,24 +844,21 @@ unsigned CodeGenRegisterClass::getWeight(const CodeGenRegBank &RegBank) const {
 bool CodeGenRegisterClass::Key::operator<(
     const CodeGenRegisterClass::Key &B) const {
   assert(Members && B.Members);
-  if (!IgnoreArtificialMembers)
-    return std::tie(*Members, RSI) < std::tie(*B.Members, B.RSI);
 
-  // Do the same lexicographical comparison, but ignoring
-  // artificial registers.
+  // Lexicographical comparison. Ignores artificial registers when asked.
   auto IA = Members->begin(), EA = Members->end();
   auto IB = B.Members->begin(), EB = B.Members->end();
   for (;;) {
-    while (IA != EA && (*IA)->Artificial)
+    while (IgnoreArtificialMembers && IA != EA && (*IA)->Artificial)
       ++IA;
-    while (IB != EB && (*IB)->Artificial)
+    while (IgnoreArtificialMembers && IB != EB && (*IB)->Artificial)
       ++IB;
     if (IA == EA && IB == EB)
       break;
     if (IA == EA || IB == EB)
       return IA == EA;
-    if (*IA != *IB)
-      return *IA < *IB;
+    if (**IA != **IB)
+      return **IA < **IB;
     ++IA;
     ++IB;
   }
diff --git a/llvm/utils/TableGen/Common/CodeGenRegisters.h b/llvm/utils/TableGen/Common/CodeGenRegisters.h
index 75aa167bc5f43..1de5973084fdd 100644
--- a/llvm/utils/TableGen/Common/CodeGenRegisters.h
+++ b/llvm/utils/TableGen/Common/CodeGenRegisters.h
@@ -318,6 +318,10 @@ inline bool operator==(const CodeGenRegister &A, const CodeGenRegister &B) {
   return A.EnumValue == B.EnumValue;
 }
 
+inline bool operator!=(const CodeGenRegister &A, const CodeGenRegister &B) {
+  return !(A == B);
+}
+
 class CodeGenRegisterClass {
   CodeGenRegister::Vec Members;
   // Bit mask of members, indexed by getRegIndex.

``````````

</details>


https://github.com/llvm/llvm-project/pull/185644