[llvm] [TableGen] Fix inferring missing sub-classes for various subreg indices (PR #185638)

[Ivan Kosarev via llvm-commits]

https://github.com/kosarev created https://github.com/llvm/llvm-project/pull/185638

We should not imply artificial registers have sub-registers for a given index even if the class is known to 'fully support' that index.

Fixes crashes reported in
https://github.com/llvm/llvm-project/pull/183371#discussion_r2905495313

>From b21719f9672db2246523f8a62a949af0f7cdc5e8 Mon Sep 17 00:00:00 2001
From: Ivan Kosarev <ivan.kosarev at amd.com>
Date: Tue, 10 Mar 2026 12:30:20 +0000
Subject: [PATCH] [TableGen] Fix inferring missing sub-classes for various
 subreg indices

We should not imply artificial registers have sub-registers for a given
index even if the class is known to 'fully support' that index.

Fixes crashes reported in
https://github.com/llvm/llvm-project/pull/183371#discussion_r2905495313
---
 llvm/utils/TableGen/Common/CodeGenRegisters.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
index fcd85cea6ffac..1c609826a6978 100644
--- a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
@@ -2485,9 +2485,9 @@ void CodeGenRegBank::inferMatchingSuperRegClass(
     SubRegs.clear();
     TopoSigs.reset();
     for (const CodeGenRegister *Super : RC->getMembers()) {
-      const CodeGenRegister *Sub = Super->getSubRegs().find(SubIdx)->second;
       if (Super->Artificial)
         continue;
+      const CodeGenRegister *Sub = Super->getSubRegs().find(SubIdx)->second;
       assert(Sub && "Missing sub-register");
       SubRegs.push_back(Sub);
       TopoSigs.set(Sub->getTopoSig());