[llvm] 2e5e38c - [AMDGPU] Update register class numbers in some tests (#185623)

[via llvm-commits]

Author: Jay Foad
Date: 2026-03-10T12:20:52Z
New Revision: 2e5e38cd5ed3e4b894b63e8af10c9be9abdbf7d9

URL: https://github.com/llvm/llvm-project/commit/2e5e38cd5ed3e4b894b63e8af10c9be9abdbf7d9
DIFF: https://github.com/llvm/llvm-project/commit/2e5e38cd5ed3e4b894b63e8af10c9be9abdbf7d9.diff

LOG: [AMDGPU] Update register class numbers in some tests (#185623)

Added: 
    

Modified: 
    llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/always-uniform-gmir.mir
    llvm/test/MachineVerifier/AMDGPU/verifier-ec-subreg-liveness.mir

Removed: 
    


################################################################################
diff  --git a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/always-uniform-gmir.mir b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/always-uniform-gmir.mir
index 1073ff6bf1d61..198dd9d2fe553 100644
--- a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/always-uniform-gmir.mir
+++ b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/always-uniform-gmir.mir
@@ -91,7 +91,7 @@ body:             |
 
     %0:_(s32) = COPY $vgpr0
     %2:vgpr_32 = COPY %0(s32)
-    INLINEASM &"; def $0, $1", 0 /* attdialect */, 1966090 /* regdef:SReg_32 */, def %1, 1835017 /* reguse:VGPR_32 */, %2
+    INLINEASM &"; def $0, $1", 0 /* attdialect */, 1572874 /* regdef:SReg_32 */, def %1, 1179657 /* reguse:VGPR_32 */, %2
     %3:_(s32) = COPY %1
     $vgpr0 = COPY %3(s32)
     SI_RETURN implicit $vgpr0
@@ -123,7 +123,7 @@ body:             |
     %0:_(s32) = COPY $vgpr0
     %6:_(p1) = G_IMPLICIT_DEF
     %3:vgpr_32 = COPY %0(s32)
-    INLINEASM &"; def $0, $1, $2", 0 /* attdialect */, 1966090 /* regdef:SReg_32 */, def %1, 1835018 /* regdef:VGPR_32 */, def %2, 1835017 /* reguse:VGPR_32 */, %3
+    INLINEASM &"; def $0, $1, $2", 0 /* attdialect */, 1572874 /* regdef:SReg_32 */, def %1, 1179658 /* regdef:VGPR_32 */, def %2, 1179657 /* reguse:VGPR_32 */, %3
     %4:_(s32) = COPY %1
     %5:_(s32) = COPY %2
     G_STORE %5(s32), %6(p1) :: (store (s32) into `ptr addrspace(1) undef`, addrspace 1)

diff  --git a/llvm/test/MachineVerifier/AMDGPU/verifier-ec-subreg-liveness.mir b/llvm/test/MachineVerifier/AMDGPU/verifier-ec-subreg-liveness.mir
index 4a972dec22e46..1d21620ed3ab6 100644
--- a/llvm/test/MachineVerifier/AMDGPU/verifier-ec-subreg-liveness.mir
+++ b/llvm/test/MachineVerifier/AMDGPU/verifier-ec-subreg-liveness.mir
@@ -10,7 +10,7 @@ body:             |
     liveins: $vgpr0_vgpr1
 
     ; CHECK-NOT: *** Bad machine code: Inconsistent valno->def ***
-    INLINEASM &"", 0 /* attdialect */,  2228235 /* regdef-ec:VGPR_32 */, def undef early-clobber %0.sub0:vreg_64, 2228234 /* regdef:VGPR_32 */, def undef %0.sub1:vreg_64
+    INLINEASM &"", 0 /* attdialect */,  1179659 /* regdef-ec:VGPR_32 */, def undef early-clobber %0.sub0:vreg_64, 1179658 /* regdef:VGPR_32 */, def undef %0.sub1:vreg_64
     FLAT_STORE_DWORDX2 $vgpr0_vgpr1, %0, 0, 0, implicit $exec, implicit $flat_scr :: (store (s64))
     S_ENDPGM 0
 
@@ -23,7 +23,7 @@ body:             |
     liveins: $vgpr0_vgpr1
 
     ; CHECK-NOT: *** Bad machine code: Inconsistent valno->def ***
-    INLINEASM &"", 0 /* attdialect */, 2228234 /* regdef:VGPR_32 */, def undef %0.sub0:vreg_64, 2228235 /* regdef-ec:VGPR_32 */, def undef early-clobber %0.sub1:vreg_64
+    INLINEASM &"", 0 /* attdialect */, 1179658 /* regdef:VGPR_32 */, def undef %0.sub0:vreg_64, 1179659 /* regdef-ec:VGPR_32 */, def undef early-clobber %0.sub1:vreg_64
     FLAT_STORE_DWORDX2 $vgpr0_vgpr1, %0, 0, 0, implicit $exec, implicit $flat_scr :: (store (s64))
     S_ENDPGM 0