[llvm] [SPIRV] Add tests documenting incorrect lowering of load/store atomic (PR #185628)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-spir-v

Author: Juan Manuel Martinez Caamaño (jmmartinez)

<details>
<summary>Changes</summary>

This patch only adds the tests documenting the broken behavior, but does not fix them.

---
Full diff: https://github.com/llvm/llvm-project/pull/185628.diff


2 Files Affected:

- (added) llvm/test/CodeGen/SPIRV/transcoding/load-atomic.ll (+63) 
- (added) llvm/test/CodeGen/SPIRV/transcoding/store-atomic.ll (+68) 


``````````diff
diff --git a/llvm/test/CodeGen/SPIRV/transcoding/load-atomic.ll b/llvm/test/CodeGen/SPIRV/transcoding/load-atomic.ll
new file mode 100644
index 0000000000000..8ae89c380c38b
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/transcoding/load-atomic.ll
@@ -0,0 +1,63 @@
+; RUN: llc -O0 -mtriple=spirv64-- %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-- %s -o - -filetype=obj | spirv-val %}
+
+; RUN: llc -O0 -mtriple=spirv32-- %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-- %s -o - -filetype=obj | spirv-val %}
+
+;; Check that 'load atomic' LLVM IR instructions are lowered.
+;; NOTE: The current lowering is incorrect: 'load atomic' should produce
+;; OpAtomicLoad but currently produces OpLoad, silently dropping the atomic
+;; ordering. This test documents the broken behaviour so it can be fixed.
+
+; CHECK-DAG: %[[#Int32:]] = OpTypeInt 32 0
+; CHECK-DAG: %[[#Int64:]] = OpTypeInt 64 0
+
+; CHECK-LABEL: OpFunction %[[#]]
+; CHECK:       %[[#ptr:]] = OpFunctionParameter %[[#]]
+; CHECK:       %[[#]] = OpLoad %[[#Int32]] %[[#ptr]] Aligned 4
+; CHECK:       OpReturnValue
+
+define i32 @load_i32_unordered(ptr addrspace(1) %ptr) {
+  %val = load atomic i32, ptr addrspace(1) %ptr unordered, align 4
+  ret i32 %val
+}
+
+; CHECK-LABEL: OpFunction %[[#]]
+; CHECK:       %[[#ptr:]] = OpFunctionParameter %[[#]]
+; CHECK:       %[[#]] = OpLoad %[[#Int32]] %[[#ptr]] Aligned 4
+; CHECK:       OpReturnValue
+
+define i32 @load_i32_monotonic(ptr addrspace(1) %ptr) {
+  %val = load atomic i32, ptr addrspace(1) %ptr monotonic, align 4
+  ret i32 %val
+}
+
+; CHECK-LABEL: OpFunction %[[#]]
+; CHECK:       %[[#ptr:]] = OpFunctionParameter %[[#]]
+; CHECK:       %[[#]] = OpLoad %[[#Int32]] %[[#ptr]] Aligned 4
+; CHECK:       OpReturnValue
+
+define i32 @load_i32_acquire(ptr addrspace(1) %ptr) {
+  %val = load atomic i32, ptr addrspace(1) %ptr acquire, align 4
+  ret i32 %val
+}
+
+; CHECK-LABEL: OpFunction %[[#]]
+; CHECK:       %[[#ptr:]] = OpFunctionParameter %[[#]]
+; CHECK:       %[[#]] = OpLoad %[[#Int32]] %[[#ptr]] Aligned 4
+; CHECK:       OpReturnValue
+
+define i32 @load_i32_seq_cst(ptr addrspace(1) %ptr) {
+  %val = load atomic i32, ptr addrspace(1) %ptr seq_cst, align 4
+  ret i32 %val
+}
+
+; CHECK-LABEL: OpFunction %[[#]]
+; CHECK:       %[[#ptr:]] = OpFunctionParameter %[[#]]
+; CHECK:       %[[#]] = OpLoad %[[#Int64]] %[[#ptr]] Aligned 8
+; CHECK:       OpReturnValue
+
+define i64 @load_i64_acquire(ptr addrspace(1) %ptr) {
+  %val = load atomic i64, ptr addrspace(1) %ptr acquire, align 8
+  ret i64 %val
+}
diff --git a/llvm/test/CodeGen/SPIRV/transcoding/store-atomic.ll b/llvm/test/CodeGen/SPIRV/transcoding/store-atomic.ll
new file mode 100644
index 0000000000000..5ca2448c157b4
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/transcoding/store-atomic.ll
@@ -0,0 +1,68 @@
+; RUN: llc -O0 -mtriple=spirv64-- %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-- %s -o - -filetype=obj | spirv-val %}
+
+; RUN: llc -O0 -mtriple=spirv32-- %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-- %s -o - -filetype=obj | spirv-val %}
+
+;; Check that 'store atomic' LLVM IR instructions are lowered.
+;; NOTE: The current lowering is incorrect: 'store atomic' should produce
+;; OpAtomicStore but currently produces OpStore, silently dropping the atomic
+;; ordering. This test documents the broken behaviour so it can be fixed.
+
+; CHECK-DAG: %[[#Int32:]] = OpTypeInt 32 0
+; CHECK-DAG: %[[#Int64:]] = OpTypeInt 64 0
+
+; CHECK-LABEL: OpFunction %[[#]]
+; CHECK:       %[[#ptr:]] = OpFunctionParameter %[[#]]
+; CHECK:       %[[#val:]] = OpFunctionParameter %[[#Int32]]
+; CHECK:       OpStore %[[#ptr]] %[[#val]] Aligned 4
+; CHECK:       OpReturn
+
+define void @store_i32_unordered(ptr addrspace(1) %ptr, i32 %val) {
+  store atomic i32 %val, ptr addrspace(1) %ptr unordered, align 4
+  ret void
+}
+
+; CHECK-LABEL: OpFunction %[[#]]
+; CHECK:       %[[#ptr:]] = OpFunctionParameter %[[#]]
+; CHECK:       %[[#val:]] = OpFunctionParameter %[[#Int32]]
+; CHECK:       OpStore %[[#ptr]] %[[#val]] Aligned 4
+; CHECK:       OpReturn
+
+define void @store_i32_monotonic(ptr addrspace(1) %ptr, i32 %val) {
+  store atomic i32 %val, ptr addrspace(1) %ptr monotonic, align 4
+  ret void
+}
+
+; CHECK-LABEL: OpFunction %[[#]]
+; CHECK:       %[[#ptr:]] = OpFunctionParameter %[[#]]
+; CHECK:       %[[#val:]] = OpFunctionParameter %[[#Int32]]
+; CHECK:       OpStore %[[#ptr]] %[[#val]] Aligned 4
+; CHECK:       OpReturn
+
+define void @store_i32_release(ptr addrspace(1) %ptr, i32 %val) {
+  store atomic i32 %val, ptr addrspace(1) %ptr release, align 4
+  ret void
+}
+
+; CHECK-LABEL: OpFunction %[[#]]
+; CHECK:       %[[#ptr:]] = OpFunctionParameter %[[#]]
+; CHECK:       %[[#val:]] = OpFunctionParameter %[[#Int32]]
+; CHECK:       OpStore %[[#ptr]] %[[#val]] Aligned 4
+; CHECK:       OpReturn
+
+define void @store_i32_seq_cst(ptr addrspace(1) %ptr, i32 %val) {
+  store atomic i32 %val, ptr addrspace(1) %ptr seq_cst, align 4
+  ret void
+}
+
+; CHECK-LABEL: OpFunction %[[#]]
+; CHECK:       %[[#ptr:]] = OpFunctionParameter %[[#]]
+; CHECK:       %[[#val:]] = OpFunctionParameter %[[#Int64]]
+; CHECK:       OpStore %[[#ptr]] %[[#val]] Aligned 8
+; CHECK:       OpReturn
+
+define void @store_i64_release(ptr addrspace(1) %ptr, i64 %val) {
+  store atomic i64 %val, ptr addrspace(1) %ptr release, align 8
+  ret void
+}

``````````

</details>


https://github.com/llvm/llvm-project/pull/185628