[llvm] [SPIR-V] Add support for SPV_INTEL_masked_gather_scatter extension (PR #185418)

[Juan Manuel Martinez Caamaño via llvm-commits]

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@@ -1724,6 +1729,68 @@ bool SPIRVInstructionSelector::selectStore(MachineInstr &I) const {
   return true;
 }
 
+bool SPIRVInstructionSelector::selectMaskedGather(Register ResVReg,
+                                                  SPIRVTypeInst ResType,
+                                                  MachineInstr &I) const {
+  assert(I.getNumExplicitDefs() == 1 && "Expected single def for gather");
+  // Operand indices (after explicit defs):
+  // 0: intrinsic ID
+  // 1: vector of pointers
+  // 2: alignment (i32 immediate)
+  // 3: mask (vector of i1)
+  // 4: passthru/fill value
+  Register PtrsReg = I.getOperand(I.getNumExplicitDefs() + 1).getReg();
+  uint32_t Alignment = I.getOperand(I.getNumExplicitDefs() + 2).getImm();
+  Register MaskReg = I.getOperand(I.getNumExplicitDefs() + 3).getReg();
+  Register PassthruReg = I.getOperand(I.getNumExplicitDefs() + 4).getReg();
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jmmartinez wrote:

Just above you have the assert about the number of explicit defs.

I think you can avoid using `I.getNumExplicitDefs()` at every operand and just write 2, 3, 4 and 5 (as you did in the scatter code).

https://github.com/llvm/llvm-project/pull/185418