[llvm] [RISCV]Lower one active interleaved load to normal segmented load (PR #185602)

[Luke Lau via llvm-commits]

https://github.com/lukel97 approved this pull request.

LGTM

I ran this on llvm-test-suite/SPEC CPU 2017 and there were no changes. Out of curiosity do you have modifications in your downstream that generate shuffles of this pattern?

https://github.com/llvm/llvm-project/pull/185602