[llvm] [RISCV] Generate landing pad based on cf-protection-branch flag only (PR #179960)
Kito Cheng via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 9 23:52:54 PDT 2026
https://github.com/kito-cheng updated https://github.com/llvm/llvm-project/pull/179960
>From 6a267361675b9acb1d7543e2a8a12a78b05cc33c Mon Sep 17 00:00:00 2001
From: Kito Cheng <kito.cheng at sifive.com>
Date: Thu, 5 Feb 2026 17:29:53 +0800
Subject: [PATCH 1/7] [RISCV] Generate landing pad based on
cf-protection-branch flag only
Previously, the backend generated lpad instructions when the Zicfilp
extension was enabled. This patch changes the behavior to generate lpad
instructions only when the cf-protection-branch module flag is set
(typically from -fcf-protection=branch).
This aligns with the Clang frontend's intent, which has a comment saying
"Always generate Zicfilp lpad insns, Non-zicfilp CPUs would read them
as NOP".
The Zicfilp extension is no longer required for lpad generation - only
the module flag matters. Tests that previously used -mattr=+experimental-zicfilp
to trigger lpad generation now use the cf-protection-branch module flag.
Additionally, the selection of NonX7 variants for indirect branches/calls
is now based on the cf-protection-branch module flag instead of the Zicfilp
extension. This ensures consistent behavior: when cf-protection-branch is
enabled, X7 is reserved for landing pad labels and cannot be used for
indirect branch/call target addresses.
---
llvm/lib/Target/RISCV/RISCVCallingConv.cpp | 4 +-
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 57 +++--
llvm/lib/Target/RISCV/RISCVISelLowering.h | 1 +
.../RISCV/RISCVIndirectBranchTracking.cpp | 5 +-
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 10 +-
llvm/lib/Target/RISCV/RISCVInstrInfo.td | 39 ++-
.../lib/Target/RISCV/RISCVLandingPadSetup.cpp | 4 +-
.../Target/RISCV/RISCVMachineFunctionInfo.cpp | 1 +
.../Target/RISCV/RISCVMachineFunctionInfo.h | 5 +
.../RISCV/branch-relaxation-rv32-cf-branch.ll | 95 +++++++
.../CodeGen/RISCV/branch-relaxation-rv32.ll | 25 +-
.../RISCV/branch-relaxation-rv64-cf-branch.ll | 95 +++++++
.../CodeGen/RISCV/branch-relaxation-rv64.ll | 25 +-
llvm/test/CodeGen/RISCV/calls-cf-branch.ll | 239 ++++++++++++++++++
llvm/test/CodeGen/RISCV/calls.ll | 174 +------------
llvm/test/CodeGen/RISCV/cf-branch-isel.ll | 46 ++++
.../test/CodeGen/RISCV/jumptable-swguarded.ll | 43 +---
llvm/test/CodeGen/RISCV/lpad.ll | 3 +
llvm/test/CodeGen/RISCV/nest-register.ll | 31 +--
llvm/test/CodeGen/RISCV/tail-calls.ll | 92 +++----
llvm/test/CodeGen/RISCV/tail-cf-branch.ll | 236 +++++++++++++++++
.../CodeGen/RISCV/zicfilp-indirect-branch.ll | 21 +-
22 files changed, 878 insertions(+), 373 deletions(-)
create mode 100644 llvm/test/CodeGen/RISCV/branch-relaxation-rv32-cf-branch.ll
create mode 100644 llvm/test/CodeGen/RISCV/branch-relaxation-rv64-cf-branch.ll
create mode 100644 llvm/test/CodeGen/RISCV/calls-cf-branch.ll
create mode 100644 llvm/test/CodeGen/RISCV/cf-branch-isel.ll
create mode 100644 llvm/test/CodeGen/RISCV/tail-cf-branch.ll
diff --git a/llvm/lib/Target/RISCV/RISCVCallingConv.cpp b/llvm/lib/Target/RISCV/RISCVCallingConv.cpp
index 54d0e0173227a..582e8e33afe0d 100644
--- a/llvm/lib/Target/RISCV/RISCVCallingConv.cpp
+++ b/llvm/lib/Target/RISCV/RISCVCallingConv.cpp
@@ -11,6 +11,7 @@
//===----------------------------------------------------------------------===//
#include "RISCVCallingConv.h"
+#include "RISCVMachineFunctionInfo.h"
#include "RISCVSubtarget.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/Module.h"
@@ -338,8 +339,7 @@ bool llvm::CC_RISCV(unsigned ValNo, MVT ValVT, MVT LocVT,
// so we assign t2/t3 for it as done in GCC's
// __builtin_call_with_static_chain
bool HasCFBranch =
- Subtarget.hasStdExtZicfilp() &&
- MF.getFunction().getParent()->getModuleFlag("cf-protection-branch");
+ MF.getInfo<RISCVMachineFunctionInfo>()->hasCFProtectionBranch();
// Normal: t2, Branch control flow protection: t3
const auto StaticChainReg = HasCFBranch ? RISCV::X28 : RISCV::X7;
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index d17911994e891..1e738142ab6c0 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -317,6 +317,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::BR_JT, MVT::Other, Expand);
setOperationAction(ISD::BR_CC, XLenVT, Expand);
+ setOperationAction(ISD::BRIND, MVT::Other, Custom);
setOperationAction(ISD::BRCOND, MVT::Other, Custom);
setOperationAction(ISD::SELECT_CC, XLenVT, Expand);
@@ -7820,6 +7821,8 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
return lowerSELECT(Op, DAG);
case ISD::BRCOND:
return lowerBRCOND(Op, DAG);
+ case ISD::BRIND:
+ return lowerBRIND(Op, DAG);
case ISD::VASTART:
return lowerVASTART(Op, DAG);
case ISD::FRAMEADDR:
@@ -9100,10 +9103,9 @@ SDValue RISCVTargetLowering::lowerINIT_TRAMPOLINE(SDValue Op,
// 28: <FunctionAddressOffset>
// 36:
+ const MachineFunction &MF = DAG.getMachineFunction();
const bool HasCFBranch =
- Subtarget.hasStdExtZicfilp() &&
- DAG.getMachineFunction().getFunction().getParent()->getModuleFlag(
- "cf-protection-branch");
+ MF.getInfo<RISCVMachineFunctionInfo>()->hasCFProtectionBranch();
const unsigned StaticChainIdx = HasCFBranch ? 5 : 4;
const unsigned StaticChainOffset = StaticChainIdx * 4;
const unsigned FunctionAddressOffset = StaticChainOffset + 8;
@@ -10100,6 +10102,19 @@ SDValue RISCVTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
DAG.getCondCode(ISD::SETNE), Op.getOperand(2));
}
+SDValue RISCVTargetLowering::lowerBRIND(SDValue Op, SelectionDAG &DAG) const {
+ // When cf-protection-branch is enabled, use BRIND_NONX7 to avoid using X7
+ // for the target address, since X7 is reserved for landing pad labels.
+ const MachineFunction &MF = DAG.getMachineFunction();
+ if (!MF.getInfo<RISCVMachineFunctionInfo>()->hasCFProtectionBranch())
+ return Op;
+
+ SDLoc DL(Op);
+ SDValue Chain = Op.getOperand(0);
+ SDValue Addr = Op.getOperand(1);
+ return DAG.getNode(RISCVISD::BRIND_NONX7, DL, Op.getValueType(), Chain, Addr);
+}
+
SDValue RISCVTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const {
MachineFunction &MF = DAG.getMachineFunction();
RISCVMachineFunctionInfo *FuncInfo = MF.getInfo<RISCVMachineFunctionInfo>();
@@ -24346,19 +24361,24 @@ SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI,
// Emit the call.
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
- // Use software guarded branch for large code model non-indirect calls
- // Tail call to external symbol will have a null CLI.CB and we need another
- // way to determine the callsite type
- bool NeedSWGuarded = false;
- if (getTargetMachine().getCodeModel() == CodeModel::Large &&
- Subtarget.hasStdExtZicfilp() &&
- ((CLI.CB && !CLI.CB->isIndirectCall()) || CalleeIsLargeExternalSymbol))
- NeedSWGuarded = true;
+ // Determine which call opcode to use based on cf-protection-branch and
+ // call type:
+ // - SW_GUARDED_*: Large code model direct calls need X7 for landing pad label
+ // - *_NONX7: Indirect calls with cf-protection must avoid X7
+ // - Regular: No cf-protection or direct calls in non-large code model
+ bool HasCFBranch =
+ MF.getInfo<RISCVMachineFunctionInfo>()->hasCFProtectionBranch();
+ bool IsIndirectCall = CLI.CB && CLI.CB->isIndirectCall();
+ bool NeedSWGuarded = getTargetMachine().getCodeModel() == CodeModel::Large &&
+ HasCFBranch &&
+ (!IsIndirectCall || CalleeIsLargeExternalSymbol);
+ bool NeedNonX7 = HasCFBranch && IsIndirectCall && !NeedSWGuarded;
if (IsTailCall) {
MF.getFrameInfo().setHasTailCall();
- unsigned CallOpc =
- NeedSWGuarded ? RISCVISD::SW_GUARDED_TAIL : RISCVISD::TAIL;
+ unsigned CallOpc = NeedSWGuarded ? RISCVISD::SW_GUARDED_TAIL
+ : NeedNonX7 ? RISCVISD::TAIL_NONX7
+ : RISCVISD::TAIL;
SDValue Ret = DAG.getNode(CallOpc, DL, NodeTys, Ops);
if (CLI.CFIType)
Ret.getNode()->setCFIType(CLI.CFIType->getZExtValue());
@@ -24367,7 +24387,9 @@ SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI,
return Ret;
}
- unsigned CallOpc = NeedSWGuarded ? RISCVISD::SW_GUARDED_CALL : RISCVISD::CALL;
+ unsigned CallOpc = NeedSWGuarded ? RISCVISD::SW_GUARDED_CALL
+ : NeedNonX7 ? RISCVISD::CALL_NONX7
+ : RISCVISD::CALL;
Chain = DAG.getNode(CallOpc, DL, NodeTys, Ops);
if (CLI.CFIType)
Chain.getNode()->setCFIType(CLI.CFIType->getZExtValue());
@@ -26007,9 +26029,10 @@ SDValue RISCVTargetLowering::expandIndirectJTBranch(const SDLoc &dl,
SDValue Value, SDValue Addr,
int JTI,
SelectionDAG &DAG) const {
- if (Subtarget.hasStdExtZicfilp()) {
- // When Zicfilp enabled, we need to use software guarded branch for jump
- // table branch.
+ const MachineFunction &MF = DAG.getMachineFunction();
+ if (MF.getInfo<RISCVMachineFunctionInfo>()->hasCFProtectionBranch()) {
+ // When cf-protection-branch enabled, we need to use software guarded
+ // branch for jump table branch.
SDValue Chain = Value;
// Jump table debug info is only needed if CodeView is enabled.
if (DAG.getTarget().getTargetTriple().isOSBinFormatCOFF())
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index 4a27bef2013ac..27f47c6547ff9 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -503,6 +503,7 @@ class RISCVTargetLowering : public TargetLowering {
SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
+ SDValue lowerBRIND(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
diff --git a/llvm/lib/Target/RISCV/RISCVIndirectBranchTracking.cpp b/llvm/lib/Target/RISCV/RISCVIndirectBranchTracking.cpp
index 0fc139a30ae76..7531a748d613f 100644
--- a/llvm/lib/Target/RISCV/RISCVIndirectBranchTracking.cpp
+++ b/llvm/lib/Target/RISCV/RISCVIndirectBranchTracking.cpp
@@ -14,12 +14,14 @@
#include "RISCV.h"
#include "RISCVInstrInfo.h"
+#include "RISCVMachineFunctionInfo.h"
#include "RISCVSubtarget.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
+#include "llvm/IR/Module.h"
#define DEBUG_TYPE "riscv-indirect-branch-tracking"
#define PASS_NAME "RISC-V Indirect Branch Tracking"
@@ -77,7 +79,8 @@ static bool isCallReturnTwice(const MachineOperand &MOp) {
bool RISCVIndirectBranchTracking::runOnMachineFunction(MachineFunction &MF) {
const auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
const RISCVInstrInfo *TII = Subtarget.getInstrInfo();
- if (!Subtarget.hasStdExtZicfilp())
+
+ if (!MF.getInfo<RISCVMachineFunctionInfo>()->hasCFProtectionBranch())
return false;
uint32_t FixedLabel = 0;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 2156d1919ddbe..67bb0a2af4252 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1462,8 +1462,12 @@ void RISCVInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB,
.addMBB(&DestBB, RISCVII::MO_CALL);
RS->enterBasicBlockEnd(MBB);
+ // When cf-protection-branch is enabled, we must use t2 (x7) for software
+ // guarded branches to hold the landing pad label.
+ bool HasCFBranch =
+ MF->getInfo<RISCVMachineFunctionInfo>()->hasCFProtectionBranch();
const TargetRegisterClass *RC = &RISCV::GPRRegClass;
- if (STI.hasStdExtZicfilp())
+ if (HasCFBranch)
RC = &RISCV::GPRX7RegClass;
Register TmpGPR =
RS->scavengeRegisterBackwards(*RC, MI.getIterator(),
@@ -1476,8 +1480,8 @@ void RISCVInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB,
// Pick s11(or s1 for rve) because it doesn't make a difference.
TmpGPR = STI.hasStdExtE() ? RISCV::X9 : RISCV::X27;
- // Force t2 if Zicfilp is on
- if (STI.hasStdExtZicfilp())
+ // Force t2 if cf-protection-branch is enabled
+ if (HasCFBranch)
TmpGPR = RISCV::X7;
int FrameIndex = RVFI->getBranchRelaxationScratchFrameIndex();
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 156e41ede2d1e..9451adc1c7b2a 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -91,6 +91,16 @@ def riscv_brcc : RVSDNode<"BR_CC", SDT_RISCVBrCC,
def riscv_sw_guarded_brind : RVSDNode<"SW_GUARDED_BRIND",
SDTBrind, [SDNPHasChain]>;
+// NonX7 variants for cf-protection-branch. These avoid using X7 for indirect
+// branches/calls since X7 is used for landing pad labels.
+def riscv_brind_nonx7 : RVSDNode<"BRIND_NONX7", SDTBrind, [SDNPHasChain]>;
+def riscv_call_nonx7 : RVSDNode<"CALL_NONX7", SDT_RISCVCall,
+ [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
+ SDNPVariadic]>;
+def riscv_tail_nonx7 : RVSDNode<"TAIL_NONX7", SDT_RISCVCall,
+ [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
+ SDNPVariadic]>;
+
// RV64I shifts, directly matching the semantics of the named RISC-V
// instructions.
def riscv_sllw : RVSDNode<"SLLW", SDT_RISCVIntBinOpW>;
@@ -1761,36 +1771,27 @@ let isBarrier = 1, isBranch = 1, isTerminator = 1 in
def PseudoBR : Pseudo<(outs), (ins simm21_lsb0_jal:$imm20), [(br bb:$imm20)]>,
PseudoInstExpansion<(JAL X0, simm21_lsb0_jal:$imm20)>;
-let Predicates = [NoStdExtZicfilp],
- isBarrier = 1, isBranch = 1, isIndirectBranch = 1, isTerminator = 1 in
+let isBarrier = 1, isBranch = 1, isIndirectBranch = 1, isTerminator = 1 in {
def PseudoBRIND : Pseudo<(outs), (ins GPRJALR:$rs1, simm12_lo:$imm12), []>,
PseudoInstExpansion<(JALR X0, GPR:$rs1, simm12_lo:$imm12)>;
-
-let Predicates = [HasStdExtZicfilp],
- isBarrier = 1, isBranch = 1, isIndirectBranch = 1, isTerminator = 1 in {
def PseudoBRINDNonX7 : Pseudo<(outs), (ins GPRJALRNonX7:$rs1, simm12_lo:$imm12), []>,
PseudoInstExpansion<(JALR X0, GPR:$rs1, simm12_lo:$imm12)>;
def PseudoBRINDX7 : Pseudo<(outs), (ins GPRX7:$rs1, simm12_lo:$imm12), []>,
PseudoInstExpansion<(JALR X0, GPR:$rs1, simm12_lo:$imm12)>;
}
-// For Zicfilp, need to avoid using X7/T2 for indirect branches which need
-// landing pad.
-let Predicates = [HasStdExtZicfilp] in {
-def : Pat<(brind GPRJALRNonX7:$rs1), (PseudoBRINDNonX7 GPRJALRNonX7:$rs1, 0)>;
-def : Pat<(brind (add GPRJALRNonX7:$rs1, simm12_lo:$imm12)),
+def : Pat<(riscv_brind_nonx7 GPRJALRNonX7:$rs1),
+ (PseudoBRINDNonX7 GPRJALRNonX7:$rs1, 0)>;
+def : Pat<(riscv_brind_nonx7 (add GPRJALRNonX7:$rs1, simm12_lo:$imm12)),
(PseudoBRINDNonX7 GPRJALRNonX7:$rs1, simm12_lo:$imm12)>;
def : Pat<(riscv_sw_guarded_brind GPRX7:$rs1), (PseudoBRINDX7 GPRX7:$rs1, 0)>;
def : Pat<(riscv_sw_guarded_brind (add GPRX7:$rs1, simm12_lo:$imm12)),
(PseudoBRINDX7 GPRX7:$rs1, simm12_lo:$imm12)>;
-}
-let Predicates = [NoStdExtZicfilp] in {
def : Pat<(brind GPRJALR:$rs1), (PseudoBRIND GPRJALR:$rs1, 0)>;
def : Pat<(brind (add GPRJALR:$rs1, simm12_lo:$imm12)),
(PseudoBRIND GPRJALR:$rs1, simm12_lo:$imm12)>;
-}
// PseudoCALLReg is a generic pseudo instruction for calls which will eventually
// expand to auipc and jalr while encoding, with any given register used as the
@@ -1823,20 +1824,16 @@ let Predicates = [HasStdExtSmrnmi] in
def : Pat<(riscv_mnret_glue), (MNRET)>;
let isCall = 1, Defs = [X1] in {
-let Predicates = [NoStdExtZicfilp] in
def PseudoCALLIndirect : Pseudo<(outs), (ins GPRJALR:$rs1),
[(riscv_call GPRJALR:$rs1)]>,
PseudoInstExpansion<(JALR X1, GPR:$rs1, 0)>;
-let Predicates = [HasStdExtZicfilp] in {
def PseudoCALLIndirectNonX7 : Pseudo<(outs), (ins GPRJALRNonX7:$rs1),
- [(riscv_call GPRJALRNonX7:$rs1)]>,
+ [(riscv_call_nonx7 GPRJALRNonX7:$rs1)]>,
PseudoInstExpansion<(JALR X1, GPR:$rs1, 0)>;
-// For large code model, non-indirect calls could be software-guarded
def PseudoCALLIndirectX7 : Pseudo<(outs), (ins GPRX7:$rs1),
[(riscv_sw_guarded_call GPRX7:$rs1)]>,
PseudoInstExpansion<(JALR X1, GPR:$rs1, 0)>;
}
-}
let isBarrier = 1, isReturn = 1, isTerminator = 1 in
def PseudoRET : Pseudo<(outs), (ins), [(riscv_ret_glue)]>,
@@ -1852,20 +1849,16 @@ def PseudoTAIL : Pseudo<(outs), (ins call_symbol:$dst), [],
Sched<[WriteIALU, WriteJalr, ReadJalr]>;
let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [X2] in {
-let Predicates = [NoStdExtZicfilp] in
def PseudoTAILIndirect : Pseudo<(outs), (ins GPRTC:$rs1),
[(riscv_tail GPRTC:$rs1)]>,
PseudoInstExpansion<(JALR X0, GPR:$rs1, 0)>;
-let Predicates = [HasStdExtZicfilp] in {
def PseudoTAILIndirectNonX7 : Pseudo<(outs), (ins GPRTCNonX7:$rs1),
- [(riscv_tail GPRTCNonX7:$rs1)]>,
+ [(riscv_tail_nonx7 GPRTCNonX7:$rs1)]>,
PseudoInstExpansion<(JALR X0, GPR:$rs1, 0)>;
-// For large code model, non-indirect calls could be software-guarded
def PseudoTAILIndirectX7 : Pseudo<(outs), (ins GPRX7:$rs1),
[(riscv_sw_guarded_tail GPRX7:$rs1)]>,
PseudoInstExpansion<(JALR X0, GPR:$rs1, 0)>;
}
-}
def : Pat<(riscv_tail (iPTR tglobaladdr:$dst)),
(PseudoTAIL tglobaladdr:$dst)>;
diff --git a/llvm/lib/Target/RISCV/RISCVLandingPadSetup.cpp b/llvm/lib/Target/RISCV/RISCVLandingPadSetup.cpp
index 072694e123084..5cc5dadb9ad89 100644
--- a/llvm/lib/Target/RISCV/RISCVLandingPadSetup.cpp
+++ b/llvm/lib/Target/RISCV/RISCVLandingPadSetup.cpp
@@ -13,9 +13,11 @@
#include "RISCV.h"
#include "RISCVInstrInfo.h"
+#include "RISCVMachineFunctionInfo.h"
#include "RISCVSubtarget.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/IR/Module.h"
using namespace llvm;
@@ -48,7 +50,7 @@ bool RISCVLandingPadSetup::runOnMachineFunction(MachineFunction &MF) {
const auto &STI = MF.getSubtarget<RISCVSubtarget>();
const RISCVInstrInfo &TII = *STI.getInstrInfo();
- if (!STI.hasStdExtZicfilp())
+ if (!MF.getInfo<RISCVMachineFunctionInfo>()->hasCFProtectionBranch())
return false;
uint32_t Label = 0;
diff --git a/llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.cpp b/llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.cpp
index 920a795737138..333fdb7ec972c 100644
--- a/llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.cpp
@@ -29,6 +29,7 @@ MachineFunctionInfo *RISCVMachineFunctionInfo::clone(
RISCVMachineFunctionInfo::RISCVMachineFunctionInfo(const Function &F,
const RISCVSubtarget *STI) {
+ CFProtectionBranch = F.getParent()->getModuleFlag("cf-protection-branch");
// The default stack probe size is 4096 if the function has no
// stack-probe-size attribute. This is a safe default because it is the
diff --git a/llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h b/llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
index f9be80feae211..854f2714d9599 100644
--- a/llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
@@ -86,6 +86,9 @@ class RISCVMachineFunctionInfo : public MachineFunctionInfo {
/// Does it probe the stack for a dynamic allocation?
bool HasDynamicAllocation = false;
+ /// Whether the function has cf-protection-branch module flag set.
+ bool CFProtectionBranch = false;
+
public:
RISCVMachineFunctionInfo(const Function &F, const RISCVSubtarget *STI);
@@ -218,6 +221,8 @@ class RISCVMachineFunctionInfo : public MachineFunctionInfo {
bool hasDynamicAllocation() const { return HasDynamicAllocation; }
void setDynamicAllocation() { HasDynamicAllocation = true; }
+
+ bool hasCFProtectionBranch() const { return CFProtectionBranch; }
};
} // end namespace llvm
diff --git a/llvm/test/CodeGen/RISCV/branch-relaxation-rv32-cf-branch.ll b/llvm/test/CodeGen/RISCV/branch-relaxation-rv32-cf-branch.ll
new file mode 100644
index 0000000000000..c7f744d33cb3c
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/branch-relaxation-rv32-cf-branch.ll
@@ -0,0 +1,95 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs -filetype=obj < %s \
+; RUN: -o /dev/null 2>&1
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
+; RUN: | FileCheck %s
+
+; Test branch relaxation with cf-protection-branch enabled.
+; Software-guarded branches should use t2 (x7) for the target address.
+
+define void @relax_bcc(i1 %a) nounwind {
+; CHECK-LABEL: relax_bcc:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lpad 0
+; CHECK-NEXT: andi a0, a0, 1
+; CHECK-NEXT: bnez a0, .LBB0_1
+; CHECK-NEXT: j .LBB0_2
+; CHECK-NEXT: .LBB0_1: # %iftrue
+; CHECK-NEXT: #APP
+; CHECK-NEXT: .zero 4096
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: .LBB0_2: # %tail
+; CHECK-NEXT: ret
+ br i1 %a, label %iftrue, label %tail
+
+iftrue:
+ call void asm sideeffect ".space 4096", ""()
+ br label %tail
+
+tail:
+ ret void
+}
+
+define i32 @relax_jal(i1 %a) nounwind {
+; CHECK-LABEL: relax_jal:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lpad 0
+; CHECK-NEXT: andi a0, a0, 1
+; CHECK-NEXT: bnez a0, .LBB1_1
+; CHECK-NEXT: # %bb.3:
+; CHECK-NEXT: jump .LBB1_2, t2
+; CHECK-NEXT: .LBB1_1: # %iftrue
+; CHECK-NEXT: addi sp, sp, -64
+; CHECK-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
+; CHECK-NEXT: sw s0, 56(sp) # 4-byte Folded Spill
+; CHECK-NEXT: sw s1, 52(sp) # 4-byte Folded Spill
+; CHECK-NEXT: sw s2, 48(sp) # 4-byte Folded Spill
+; CHECK-NEXT: sw s3, 44(sp) # 4-byte Folded Spill
+; CHECK-NEXT: sw s4, 40(sp) # 4-byte Folded Spill
+; CHECK-NEXT: sw s5, 36(sp) # 4-byte Folded Spill
+; CHECK-NEXT: sw s6, 32(sp) # 4-byte Folded Spill
+; CHECK-NEXT: sw s7, 28(sp) # 4-byte Folded Spill
+; CHECK-NEXT: sw s8, 24(sp) # 4-byte Folded Spill
+; CHECK-NEXT: sw s9, 20(sp) # 4-byte Folded Spill
+; CHECK-NEXT: sw s10, 16(sp) # 4-byte Folded Spill
+; CHECK-NEXT: sw s11, 12(sp) # 4-byte Folded Spill
+; CHECK-NEXT: #APP
+; CHECK-NEXT: # clobber lots of registers
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: #APP
+; CHECK-NEXT: .zero 1048576
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: li a0, 1
+; CHECK-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
+; CHECK-NEXT: lw s0, 56(sp) # 4-byte Folded Reload
+; CHECK-NEXT: lw s1, 52(sp) # 4-byte Folded Reload
+; CHECK-NEXT: lw s2, 48(sp) # 4-byte Folded Reload
+; CHECK-NEXT: lw s3, 44(sp) # 4-byte Folded Reload
+; CHECK-NEXT: lw s4, 40(sp) # 4-byte Folded Reload
+; CHECK-NEXT: lw s5, 36(sp) # 4-byte Folded Reload
+; CHECK-NEXT: lw s6, 32(sp) # 4-byte Folded Reload
+; CHECK-NEXT: lw s7, 28(sp) # 4-byte Folded Reload
+; CHECK-NEXT: lw s8, 24(sp) # 4-byte Folded Reload
+; CHECK-NEXT: lw s9, 20(sp) # 4-byte Folded Reload
+; CHECK-NEXT: lw s10, 16(sp) # 4-byte Folded Reload
+; CHECK-NEXT: lw s11, 12(sp) # 4-byte Folded Reload
+; CHECK-NEXT: addi sp, sp, 64
+; CHECK-NEXT: .LBB1_2: # %tail
+; CHECK-NEXT: ret
+ br i1 %a, label %iftrue, label %iffalse
+
+iftrue:
+ call void asm sideeffect "# clobber lots of registers", "~{x1},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x16},~{x17},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{x29},~{x30},~{x31}"()
+ call void asm sideeffect ".space 1048576", ""()
+ br label %tail
+
+iffalse:
+ br label %tail
+
+tail:
+ %val = phi i32 [1, %iftrue], [0, %iffalse]
+ ret i32 %val
+}
+
+!llvm.module.flags = !{!0}
+!0 = !{i32 8, !"cf-protection-branch", i32 1}
diff --git a/llvm/test/CodeGen/RISCV/branch-relaxation-rv32.ll b/llvm/test/CodeGen/RISCV/branch-relaxation-rv32.ll
index e987923233865..8a73549380424 100644
--- a/llvm/test/CodeGen/RISCV/branch-relaxation-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/branch-relaxation-rv32.ll
@@ -25,7 +25,6 @@ define void @relax_bcc(i1 %a) nounwind {
;
; CHECK-ZICFILP-LABEL: relax_bcc:
; CHECK-ZICFILP: # %bb.0:
-; CHECK-ZICFILP-NEXT: lpad 0
; CHECK-ZICFILP-NEXT: andi a0, a0, 1
; CHECK-ZICFILP-NEXT: bnez a0, .LBB0_1
; CHECK-ZICFILP-NEXT: j .LBB0_2
@@ -70,12 +69,11 @@ define i32 @relax_jal(i1 %a) nounwind {
;
; CHECK-ZICFILP-LABEL: relax_jal:
; CHECK-ZICFILP: # %bb.0:
-; CHECK-ZICFILP-NEXT: lpad 0
; CHECK-ZICFILP-NEXT: addi sp, sp, -16
; CHECK-ZICFILP-NEXT: andi a0, a0, 1
; CHECK-ZICFILP-NEXT: bnez a0, .LBB1_1
; CHECK-ZICFILP-NEXT: # %bb.4:
-; CHECK-ZICFILP-NEXT: jump .LBB1_2, t2
+; CHECK-ZICFILP-NEXT: jump .LBB1_2, a0
; CHECK-ZICFILP-NEXT: .LBB1_1: # %iftrue
; CHECK-ZICFILP-NEXT: #APP
; CHECK-ZICFILP-NEXT: #NO_APP
@@ -351,7 +349,6 @@ define void @relax_jal_spill_32() {
;
; CHECK-ZICFILP-LABEL: relax_jal_spill_32:
; CHECK-ZICFILP: # %bb.0:
-; CHECK-ZICFILP-NEXT: lpad 0
; CHECK-ZICFILP-NEXT: addi sp, sp, -64
; CHECK-ZICFILP-NEXT: .cfi_def_cfa_offset 64
; CHECK-ZICFILP-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
@@ -466,15 +463,15 @@ define void @relax_jal_spill_32() {
; CHECK-ZICFILP-NEXT: #NO_APP
; CHECK-ZICFILP-NEXT: beq t5, t6, .LBB2_1
; CHECK-ZICFILP-NEXT: # %bb.3:
-; CHECK-ZICFILP-NEXT: sw t2, 0(sp) # 4-byte Folded Spill
-; CHECK-ZICFILP-NEXT: jump .LBB2_4, t2
+; CHECK-ZICFILP-NEXT: sw s11, 0(sp) # 4-byte Folded Spill
+; CHECK-ZICFILP-NEXT: jump .LBB2_4, s11
; CHECK-ZICFILP-NEXT: .LBB2_1: # %branch_1
; CHECK-ZICFILP-NEXT: #APP
; CHECK-ZICFILP-NEXT: .zero 1048576
; CHECK-ZICFILP-NEXT: #NO_APP
; CHECK-ZICFILP-NEXT: j .LBB2_2
; CHECK-ZICFILP-NEXT: .LBB2_4: # %branch_2
-; CHECK-ZICFILP-NEXT: lw t2, 0(sp) # 4-byte Folded Reload
+; CHECK-ZICFILP-NEXT: lw s11, 0(sp) # 4-byte Folded Reload
; CHECK-ZICFILP-NEXT: .LBB2_2: # %branch_2
; CHECK-ZICFILP-NEXT: #APP
; CHECK-ZICFILP-NEXT: # reg use ra
@@ -913,7 +910,6 @@ define void @relax_jal_spill_32_adjust_spill_slot() {
;
; CHECK-ZICFILP-LABEL: relax_jal_spill_32_adjust_spill_slot:
; CHECK-ZICFILP: # %bb.0:
-; CHECK-ZICFILP-NEXT: lpad 0
; CHECK-ZICFILP-NEXT: addi sp, sp, -2032
; CHECK-ZICFILP-NEXT: .cfi_def_cfa_offset 2032
; CHECK-ZICFILP-NEXT: sw ra, 2028(sp) # 4-byte Folded Spill
@@ -1035,15 +1031,15 @@ define void @relax_jal_spill_32_adjust_spill_slot() {
; CHECK-ZICFILP-NEXT: #NO_APP
; CHECK-ZICFILP-NEXT: beq t5, t6, .LBB3_1
; CHECK-ZICFILP-NEXT: # %bb.3:
-; CHECK-ZICFILP-NEXT: sw t2, 0(sp) # 4-byte Folded Spill
-; CHECK-ZICFILP-NEXT: jump .LBB3_4, t2
+; CHECK-ZICFILP-NEXT: sw s11, 0(sp) # 4-byte Folded Spill
+; CHECK-ZICFILP-NEXT: jump .LBB3_4, s11
; CHECK-ZICFILP-NEXT: .LBB3_1: # %branch_1
; CHECK-ZICFILP-NEXT: #APP
; CHECK-ZICFILP-NEXT: .zero 1048576
; CHECK-ZICFILP-NEXT: #NO_APP
; CHECK-ZICFILP-NEXT: j .LBB3_2
; CHECK-ZICFILP-NEXT: .LBB3_4: # %branch_2
-; CHECK-ZICFILP-NEXT: lw t2, 0(sp) # 4-byte Folded Reload
+; CHECK-ZICFILP-NEXT: lw s11, 0(sp) # 4-byte Folded Reload
; CHECK-ZICFILP-NEXT: .LBB3_2: # %branch_2
; CHECK-ZICFILP-NEXT: #APP
; CHECK-ZICFILP-NEXT: # reg use ra
@@ -1492,7 +1488,6 @@ define void @relax_jal_spill_32_restore_block_correspondence() {
;
; CHECK-ZICFILP-LABEL: relax_jal_spill_32_restore_block_correspondence:
; CHECK-ZICFILP: # %bb.0: # %entry
-; CHECK-ZICFILP-NEXT: lpad 0
; CHECK-ZICFILP-NEXT: addi sp, sp, -64
; CHECK-ZICFILP-NEXT: .cfi_def_cfa_offset 64
; CHECK-ZICFILP-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
@@ -1609,7 +1604,7 @@ define void @relax_jal_spill_32_restore_block_correspondence() {
; CHECK-ZICFILP-NEXT: bne t5, t6, .LBB4_2
; CHECK-ZICFILP-NEXT: j .LBB4_1
; CHECK-ZICFILP-NEXT: .LBB4_8: # %dest_1
-; CHECK-ZICFILP-NEXT: lw t2, 0(sp) # 4-byte Folded Reload
+; CHECK-ZICFILP-NEXT: lw s11, 0(sp) # 4-byte Folded Reload
; CHECK-ZICFILP-NEXT: .LBB4_1: # %dest_1
; CHECK-ZICFILP-NEXT: #APP
; CHECK-ZICFILP-NEXT: # dest 1
@@ -1746,8 +1741,8 @@ define void @relax_jal_spill_32_restore_block_correspondence() {
; CHECK-ZICFILP-NEXT: .zero 1048576
; CHECK-ZICFILP-NEXT: #NO_APP
; CHECK-ZICFILP-NEXT: # %bb.7: # %space
-; CHECK-ZICFILP-NEXT: sw t2, 0(sp) # 4-byte Folded Spill
-; CHECK-ZICFILP-NEXT: jump .LBB4_8, t2
+; CHECK-ZICFILP-NEXT: sw s11, 0(sp) # 4-byte Folded Spill
+; CHECK-ZICFILP-NEXT: jump .LBB4_8, s11
entry:
%ra = call i32 asm sideeffect "addi ra, x0, 1", "={ra}"()
%t0 = call i32 asm sideeffect "addi t0, x0, 5", "={t0}"()
diff --git a/llvm/test/CodeGen/RISCV/branch-relaxation-rv64-cf-branch.ll b/llvm/test/CodeGen/RISCV/branch-relaxation-rv64-cf-branch.ll
new file mode 100644
index 0000000000000..e868731e571e7
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/branch-relaxation-rv64-cf-branch.ll
@@ -0,0 +1,95 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -verify-machineinstrs -filetype=obj < %s \
+; RUN: -o /dev/null 2>&1
+; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
+; RUN: | FileCheck %s
+
+; Test branch relaxation with cf-protection-branch enabled.
+; Software-guarded branches should use t2 (x7) for the target address.
+
+define void @relax_bcc(i1 %a) nounwind {
+; CHECK-LABEL: relax_bcc:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lpad 0
+; CHECK-NEXT: andi a0, a0, 1
+; CHECK-NEXT: bnez a0, .LBB0_1
+; CHECK-NEXT: j .LBB0_2
+; CHECK-NEXT: .LBB0_1: # %iftrue
+; CHECK-NEXT: #APP
+; CHECK-NEXT: .zero 4096
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: .LBB0_2: # %tail
+; CHECK-NEXT: ret
+ br i1 %a, label %iftrue, label %tail
+
+iftrue:
+ call void asm sideeffect ".space 4096", ""()
+ br label %tail
+
+tail:
+ ret void
+}
+
+define i32 @relax_jal(i1 %a) nounwind {
+; CHECK-LABEL: relax_jal:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lpad 0
+; CHECK-NEXT: andi a0, a0, 1
+; CHECK-NEXT: bnez a0, .LBB1_1
+; CHECK-NEXT: # %bb.3:
+; CHECK-NEXT: jump .LBB1_2, t2
+; CHECK-NEXT: .LBB1_1: # %iftrue
+; CHECK-NEXT: addi sp, sp, -112
+; CHECK-NEXT: sd ra, 104(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd s0, 96(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd s1, 88(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd s2, 80(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd s3, 72(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd s4, 64(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd s5, 56(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd s6, 48(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd s7, 40(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd s8, 32(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd s9, 24(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd s10, 16(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd s11, 8(sp) # 8-byte Folded Spill
+; CHECK-NEXT: #APP
+; CHECK-NEXT: # clobber lots of registers
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: #APP
+; CHECK-NEXT: .zero 1048576
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: li a0, 1
+; CHECK-NEXT: ld ra, 104(sp) # 8-byte Folded Reload
+; CHECK-NEXT: ld s0, 96(sp) # 8-byte Folded Reload
+; CHECK-NEXT: ld s1, 88(sp) # 8-byte Folded Reload
+; CHECK-NEXT: ld s2, 80(sp) # 8-byte Folded Reload
+; CHECK-NEXT: ld s3, 72(sp) # 8-byte Folded Reload
+; CHECK-NEXT: ld s4, 64(sp) # 8-byte Folded Reload
+; CHECK-NEXT: ld s5, 56(sp) # 8-byte Folded Reload
+; CHECK-NEXT: ld s6, 48(sp) # 8-byte Folded Reload
+; CHECK-NEXT: ld s7, 40(sp) # 8-byte Folded Reload
+; CHECK-NEXT: ld s8, 32(sp) # 8-byte Folded Reload
+; CHECK-NEXT: ld s9, 24(sp) # 8-byte Folded Reload
+; CHECK-NEXT: ld s10, 16(sp) # 8-byte Folded Reload
+; CHECK-NEXT: ld s11, 8(sp) # 8-byte Folded Reload
+; CHECK-NEXT: addi sp, sp, 112
+; CHECK-NEXT: .LBB1_2: # %tail
+; CHECK-NEXT: ret
+ br i1 %a, label %iftrue, label %iffalse
+
+iftrue:
+ call void asm sideeffect "# clobber lots of registers", "~{x1},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x16},~{x17},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{x29},~{x30},~{x31}"()
+ call void asm sideeffect ".space 1048576", ""()
+ br label %tail
+
+iffalse:
+ br label %tail
+
+tail:
+ %val = phi i32 [1, %iftrue], [0, %iffalse]
+ ret i32 %val
+}
+
+!llvm.module.flags = !{!0}
+!0 = !{i32 8, !"cf-protection-branch", i32 1}
diff --git a/llvm/test/CodeGen/RISCV/branch-relaxation-rv64.ll b/llvm/test/CodeGen/RISCV/branch-relaxation-rv64.ll
index c54ed1b06b1c8..c21b4fbcc12f7 100644
--- a/llvm/test/CodeGen/RISCV/branch-relaxation-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/branch-relaxation-rv64.ll
@@ -25,7 +25,6 @@ define void @relax_bcc(i1 %a) nounwind {
;
; CHECK-ZICFILP-LABEL: relax_bcc:
; CHECK-ZICFILP: # %bb.0:
-; CHECK-ZICFILP-NEXT: lpad 0
; CHECK-ZICFILP-NEXT: andi a0, a0, 1
; CHECK-ZICFILP-NEXT: bnez a0, .LBB0_1
; CHECK-ZICFILP-NEXT: j .LBB0_2
@@ -70,12 +69,11 @@ define i32 @relax_jal(i1 %a) nounwind {
;
; CHECK-ZICFILP-LABEL: relax_jal:
; CHECK-ZICFILP: # %bb.0:
-; CHECK-ZICFILP-NEXT: lpad 0
; CHECK-ZICFILP-NEXT: addi sp, sp, -16
; CHECK-ZICFILP-NEXT: andi a0, a0, 1
; CHECK-ZICFILP-NEXT: bnez a0, .LBB1_1
; CHECK-ZICFILP-NEXT: # %bb.4:
-; CHECK-ZICFILP-NEXT: jump .LBB1_2, t2
+; CHECK-ZICFILP-NEXT: jump .LBB1_2, a0
; CHECK-ZICFILP-NEXT: .LBB1_1: # %iftrue
; CHECK-ZICFILP-NEXT: #APP
; CHECK-ZICFILP-NEXT: #NO_APP
@@ -353,7 +351,6 @@ define void @relax_jal_spill_64() {
;
; CHECK-ZICFILP-LABEL: relax_jal_spill_64:
; CHECK-ZICFILP: # %bb.0:
-; CHECK-ZICFILP-NEXT: lpad 0
; CHECK-ZICFILP-NEXT: addi sp, sp, -112
; CHECK-ZICFILP-NEXT: .cfi_def_cfa_offset 112
; CHECK-ZICFILP-NEXT: sd ra, 104(sp) # 8-byte Folded Spill
@@ -468,15 +465,15 @@ define void @relax_jal_spill_64() {
; CHECK-ZICFILP-NEXT: #NO_APP
; CHECK-ZICFILP-NEXT: beq t5, t6, .LBB2_1
; CHECK-ZICFILP-NEXT: # %bb.3:
-; CHECK-ZICFILP-NEXT: sd t2, 0(sp) # 8-byte Folded Spill
-; CHECK-ZICFILP-NEXT: jump .LBB2_4, t2
+; CHECK-ZICFILP-NEXT: sd s11, 0(sp) # 8-byte Folded Spill
+; CHECK-ZICFILP-NEXT: jump .LBB2_4, s11
; CHECK-ZICFILP-NEXT: .LBB2_1: # %branch_1
; CHECK-ZICFILP-NEXT: #APP
; CHECK-ZICFILP-NEXT: .zero 1048576
; CHECK-ZICFILP-NEXT: #NO_APP
; CHECK-ZICFILP-NEXT: j .LBB2_2
; CHECK-ZICFILP-NEXT: .LBB2_4: # %branch_2
-; CHECK-ZICFILP-NEXT: ld t2, 0(sp) # 8-byte Folded Reload
+; CHECK-ZICFILP-NEXT: ld s11, 0(sp) # 8-byte Folded Reload
; CHECK-ZICFILP-NEXT: .LBB2_2: # %branch_2
; CHECK-ZICFILP-NEXT: #APP
; CHECK-ZICFILP-NEXT: # reg use ra
@@ -916,7 +913,6 @@ define void @relax_jal_spill_64_adjust_spill_slot() {
;
; CHECK-ZICFILP-LABEL: relax_jal_spill_64_adjust_spill_slot:
; CHECK-ZICFILP: # %bb.0:
-; CHECK-ZICFILP-NEXT: lpad 0
; CHECK-ZICFILP-NEXT: addi sp, sp, -2032
; CHECK-ZICFILP-NEXT: .cfi_def_cfa_offset 2032
; CHECK-ZICFILP-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill
@@ -1038,15 +1034,15 @@ define void @relax_jal_spill_64_adjust_spill_slot() {
; CHECK-ZICFILP-NEXT: #NO_APP
; CHECK-ZICFILP-NEXT: beq t5, t6, .LBB3_1
; CHECK-ZICFILP-NEXT: # %bb.3:
-; CHECK-ZICFILP-NEXT: sd t2, 0(sp) # 8-byte Folded Spill
-; CHECK-ZICFILP-NEXT: jump .LBB3_4, t2
+; CHECK-ZICFILP-NEXT: sd s11, 0(sp) # 8-byte Folded Spill
+; CHECK-ZICFILP-NEXT: jump .LBB3_4, s11
; CHECK-ZICFILP-NEXT: .LBB3_1: # %branch_1
; CHECK-ZICFILP-NEXT: #APP
; CHECK-ZICFILP-NEXT: .zero 1048576
; CHECK-ZICFILP-NEXT: #NO_APP
; CHECK-ZICFILP-NEXT: j .LBB3_2
; CHECK-ZICFILP-NEXT: .LBB3_4: # %branch_2
-; CHECK-ZICFILP-NEXT: ld t2, 0(sp) # 8-byte Folded Reload
+; CHECK-ZICFILP-NEXT: ld s11, 0(sp) # 8-byte Folded Reload
; CHECK-ZICFILP-NEXT: .LBB3_2: # %branch_2
; CHECK-ZICFILP-NEXT: #APP
; CHECK-ZICFILP-NEXT: # reg use ra
@@ -1496,7 +1492,6 @@ define void @relax_jal_spill_64_restore_block_correspondence() {
;
; CHECK-ZICFILP-LABEL: relax_jal_spill_64_restore_block_correspondence:
; CHECK-ZICFILP: # %bb.0: # %entry
-; CHECK-ZICFILP-NEXT: lpad 0
; CHECK-ZICFILP-NEXT: addi sp, sp, -112
; CHECK-ZICFILP-NEXT: .cfi_def_cfa_offset 112
; CHECK-ZICFILP-NEXT: sd ra, 104(sp) # 8-byte Folded Spill
@@ -1613,7 +1608,7 @@ define void @relax_jal_spill_64_restore_block_correspondence() {
; CHECK-ZICFILP-NEXT: bne t5, t6, .LBB4_2
; CHECK-ZICFILP-NEXT: j .LBB4_1
; CHECK-ZICFILP-NEXT: .LBB4_8: # %dest_1
-; CHECK-ZICFILP-NEXT: ld t2, 0(sp) # 8-byte Folded Reload
+; CHECK-ZICFILP-NEXT: ld s11, 0(sp) # 8-byte Folded Reload
; CHECK-ZICFILP-NEXT: .LBB4_1: # %dest_1
; CHECK-ZICFILP-NEXT: #APP
; CHECK-ZICFILP-NEXT: # dest 1
@@ -1750,8 +1745,8 @@ define void @relax_jal_spill_64_restore_block_correspondence() {
; CHECK-ZICFILP-NEXT: .zero 1048576
; CHECK-ZICFILP-NEXT: #NO_APP
; CHECK-ZICFILP-NEXT: # %bb.7: # %space
-; CHECK-ZICFILP-NEXT: sd t2, 0(sp) # 8-byte Folded Spill
-; CHECK-ZICFILP-NEXT: jump .LBB4_8, t2
+; CHECK-ZICFILP-NEXT: sd s11, 0(sp) # 8-byte Folded Spill
+; CHECK-ZICFILP-NEXT: jump .LBB4_8, s11
entry:
%ra = call i64 asm sideeffect "addi ra, x0, 1", "={ra}"()
%t0 = call i64 asm sideeffect "addi t0, x0, 5", "={t0}"()
diff --git a/llvm/test/CodeGen/RISCV/calls-cf-branch.ll b/llvm/test/CodeGen/RISCV/calls-cf-branch.ll
new file mode 100644
index 0000000000000..90d7460f54849
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/calls-cf-branch.ll
@@ -0,0 +1,239 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV32I %s
+; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV64I %s
+; RUN: llc -code-model=large -mtriple=riscv64 -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV64I-LARGE %s
+
+; Test call generation with cf-protection-branch enabled.
+; This tests landing pad generation and NonX7 variants for indirect calls.
+
+declare i32 @external_function(i32)
+
+define i32 @test_call_external(i32 %a) nounwind {
+; RV32I-LABEL: test_call_external:
+; RV32I: # %bb.0:
+; RV32I-NEXT: lpad 0
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call external_function
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: test_call_external:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lpad 0
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: call external_function
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
+;
+; RV64I-LARGE-LABEL: test_call_external:
+; RV64I-LARGE: # %bb.0:
+; RV64I-LARGE-NEXT: lpad 0
+; RV64I-LARGE-NEXT: addi sp, sp, -16
+; RV64I-LARGE-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-LARGE-NEXT: .Lpcrel_hi0:
+; RV64I-LARGE-NEXT: auipc a1, %pcrel_hi(.LCPI0_0)
+; RV64I-LARGE-NEXT: ld t2, %pcrel_lo(.Lpcrel_hi0)(a1)
+; RV64I-LARGE-NEXT: jalr t2
+; RV64I-LARGE-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-LARGE-NEXT: addi sp, sp, 16
+; RV64I-LARGE-NEXT: ret
+ %1 = call i32 @external_function(i32 %a)
+ ret i32 %1
+}
+
+define i32 @test_call_indirect(ptr %a, i32 %b) nounwind {
+; RV32I-LABEL: test_call_indirect:
+; RV32I: # %bb.0:
+; RV32I-NEXT: lpad 0
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv a2, a0
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: jalr a2
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: test_call_indirect:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lpad 0
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv a2, a0
+; RV64I-NEXT: mv a0, a1
+; RV64I-NEXT: jalr a2
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
+;
+; RV64I-LARGE-LABEL: test_call_indirect:
+; RV64I-LARGE: # %bb.0:
+; RV64I-LARGE-NEXT: lpad 0
+; RV64I-LARGE-NEXT: addi sp, sp, -16
+; RV64I-LARGE-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-LARGE-NEXT: mv a2, a0
+; RV64I-LARGE-NEXT: mv a0, a1
+; RV64I-LARGE-NEXT: jalr a2
+; RV64I-LARGE-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-LARGE-NEXT: addi sp, sp, 16
+; RV64I-LARGE-NEXT: ret
+ %1 = call i32 %a(i32 %b)
+ ret i32 %1
+}
+
+; Make sure we don't use t0 as the source for jalr as that is a hint to pop the
+; return address stack on some microarchitectures.
+define i32 @test_call_indirect_no_t0(ptr %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h) nounwind {
+; RV32I-LABEL: test_call_indirect_no_t0:
+; RV32I: # %bb.0:
+; RV32I-NEXT: lpad 0
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv t1, a0
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: mv a1, a2
+; RV32I-NEXT: mv a2, a3
+; RV32I-NEXT: mv a3, a4
+; RV32I-NEXT: mv a4, a5
+; RV32I-NEXT: mv a5, a6
+; RV32I-NEXT: mv a6, a7
+; RV32I-NEXT: jalr t1
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: test_call_indirect_no_t0:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lpad 0
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv t1, a0
+; RV64I-NEXT: mv a0, a1
+; RV64I-NEXT: mv a1, a2
+; RV64I-NEXT: mv a2, a3
+; RV64I-NEXT: mv a3, a4
+; RV64I-NEXT: mv a4, a5
+; RV64I-NEXT: mv a5, a6
+; RV64I-NEXT: mv a6, a7
+; RV64I-NEXT: jalr t1
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
+;
+; RV64I-LARGE-LABEL: test_call_indirect_no_t0:
+; RV64I-LARGE: # %bb.0:
+; RV64I-LARGE-NEXT: lpad 0
+; RV64I-LARGE-NEXT: addi sp, sp, -16
+; RV64I-LARGE-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-LARGE-NEXT: mv t1, a0
+; RV64I-LARGE-NEXT: mv a0, a1
+; RV64I-LARGE-NEXT: mv a1, a2
+; RV64I-LARGE-NEXT: mv a2, a3
+; RV64I-LARGE-NEXT: mv a3, a4
+; RV64I-LARGE-NEXT: mv a4, a5
+; RV64I-LARGE-NEXT: mv a5, a6
+; RV64I-LARGE-NEXT: mv a6, a7
+; RV64I-LARGE-NEXT: jalr t1
+; RV64I-LARGE-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-LARGE-NEXT: addi sp, sp, 16
+; RV64I-LARGE-NEXT: ret
+ %1 = call i32 %a(i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h)
+ ret i32 %1
+}
+
+declare i32 @external_many_args(i32, i32, i32, i32, i32, i32, i32, i32, i32, i32) nounwind
+
+define fastcc void @fastcc_call_nonfastcc(){
+; RV32I-LABEL: fastcc_call_nonfastcc:
+; RV32I: # %bb.0:
+; RV32I-NEXT: lpad 0
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: .cfi_def_cfa_offset 16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: .cfi_offset ra, -4
+; RV32I-NEXT: li t0, 10
+; RV32I-NEXT: li t1, 9
+; RV32I-NEXT: li a0, 1
+; RV32I-NEXT: li a1, 2
+; RV32I-NEXT: li a2, 3
+; RV32I-NEXT: li a3, 4
+; RV32I-NEXT: li a4, 5
+; RV32I-NEXT: li a5, 6
+; RV32I-NEXT: li a6, 7
+; RV32I-NEXT: li a7, 8
+; RV32I-NEXT: sw t1, 0(sp)
+; RV32I-NEXT: sw t0, 4(sp)
+; RV32I-NEXT: call external_many_args
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: .cfi_restore ra
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: .cfi_def_cfa_offset 0
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: fastcc_call_nonfastcc:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lpad 0
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: .cfi_def_cfa_offset 32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: .cfi_offset ra, -8
+; RV64I-NEXT: li t0, 10
+; RV64I-NEXT: li t1, 9
+; RV64I-NEXT: li a0, 1
+; RV64I-NEXT: li a1, 2
+; RV64I-NEXT: li a2, 3
+; RV64I-NEXT: li a3, 4
+; RV64I-NEXT: li a4, 5
+; RV64I-NEXT: li a5, 6
+; RV64I-NEXT: li a6, 7
+; RV64I-NEXT: li a7, 8
+; RV64I-NEXT: sd t1, 0(sp)
+; RV64I-NEXT: sd t0, 8(sp)
+; RV64I-NEXT: call external_many_args
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: .cfi_restore ra
+; RV64I-NEXT: addi sp, sp, 32
+; RV64I-NEXT: .cfi_def_cfa_offset 0
+; RV64I-NEXT: ret
+;
+; RV64I-LARGE-LABEL: fastcc_call_nonfastcc:
+; RV64I-LARGE: # %bb.0:
+; RV64I-LARGE-NEXT: lpad 0
+; RV64I-LARGE-NEXT: addi sp, sp, -32
+; RV64I-LARGE-NEXT: .cfi_def_cfa_offset 32
+; RV64I-LARGE-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-LARGE-NEXT: .cfi_offset ra, -8
+; RV64I-LARGE-NEXT: li t0, 10
+; RV64I-LARGE-NEXT: li t1, 9
+; RV64I-LARGE-NEXT: .Lpcrel_hi1:
+; RV64I-LARGE-NEXT: auipc a5, %pcrel_hi(.LCPI3_0)
+; RV64I-LARGE-NEXT: li a0, 1
+; RV64I-LARGE-NEXT: li a1, 2
+; RV64I-LARGE-NEXT: li a2, 3
+; RV64I-LARGE-NEXT: li a3, 4
+; RV64I-LARGE-NEXT: li a4, 5
+; RV64I-LARGE-NEXT: ld t2, %pcrel_lo(.Lpcrel_hi1)(a5)
+; RV64I-LARGE-NEXT: li a5, 6
+; RV64I-LARGE-NEXT: li a6, 7
+; RV64I-LARGE-NEXT: li a7, 8
+; RV64I-LARGE-NEXT: sd t1, 0(sp)
+; RV64I-LARGE-NEXT: sd t0, 8(sp)
+; RV64I-LARGE-NEXT: jalr t2
+; RV64I-LARGE-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-LARGE-NEXT: .cfi_restore ra
+; RV64I-LARGE-NEXT: addi sp, sp, 32
+; RV64I-LARGE-NEXT: .cfi_def_cfa_offset 0
+; RV64I-LARGE-NEXT: ret
+ call void @external_many_args(i32 1, i32 2,i32 3,i32 4,i32 5,i32 6,i32 7,i32 8,i32 9,i32 10)
+ ret void
+}
+
+!llvm.module.flags = !{!0}
+!0 = !{i32 8, !"cf-protection-branch", i32 1}
diff --git a/llvm/test/CodeGen/RISCV/calls.ll b/llvm/test/CodeGen/RISCV/calls.ll
index f30c453d7f6bc..7637978c40f78 100644
--- a/llvm/test/CodeGen/RISCV/calls.ll
+++ b/llvm/test/CodeGen/RISCV/calls.ll
@@ -12,7 +12,7 @@
; RUN: llc -code-model=large -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I-LARGE %s
; RUN: llc -code-model=large -mtriple=riscv64 -mattr=experimental-zicfilp -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefix=RV64I-LARGE-ZICFILP %s
+; RUN: | FileCheck -check-prefix=RV64I-LARGE %s
declare i32 @external_function(i32)
@@ -65,18 +65,6 @@ define i32 @test_call_external(i32 %a) nounwind {
; RV64I-LARGE-NEXT: addi sp, sp, 16
; RV64I-LARGE-NEXT: ret
;
-; RV64I-LARGE-ZICFILP-LABEL: test_call_external:
-; RV64I-LARGE-ZICFILP: # %bb.0:
-; RV64I-LARGE-ZICFILP-NEXT: lpad 0
-; RV64I-LARGE-ZICFILP-NEXT: addi sp, sp, -16
-; RV64I-LARGE-ZICFILP-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-LARGE-ZICFILP-NEXT: .Lpcrel_hi0:
-; RV64I-LARGE-ZICFILP-NEXT: auipc a1, %pcrel_hi(.LCPI0_0)
-; RV64I-LARGE-ZICFILP-NEXT: ld t2, %pcrel_lo(.Lpcrel_hi0)(a1)
-; RV64I-LARGE-ZICFILP-NEXT: jalr t2
-; RV64I-LARGE-ZICFILP-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-LARGE-ZICFILP-NEXT: addi sp, sp, 16
-; RV64I-LARGE-ZICFILP-NEXT: ret
%1 = call i32 @external_function(i32 %a)
ret i32 %1
}
@@ -132,18 +120,6 @@ define i32 @test_call_dso_local(i32 %a) nounwind {
; RV64I-LARGE-NEXT: addi sp, sp, 16
; RV64I-LARGE-NEXT: ret
;
-; RV64I-LARGE-ZICFILP-LABEL: test_call_dso_local:
-; RV64I-LARGE-ZICFILP: # %bb.0:
-; RV64I-LARGE-ZICFILP-NEXT: lpad 0
-; RV64I-LARGE-ZICFILP-NEXT: addi sp, sp, -16
-; RV64I-LARGE-ZICFILP-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-LARGE-ZICFILP-NEXT: .Lpcrel_hi1:
-; RV64I-LARGE-ZICFILP-NEXT: auipc a1, %pcrel_hi(.LCPI1_0)
-; RV64I-LARGE-ZICFILP-NEXT: ld t2, %pcrel_lo(.Lpcrel_hi1)(a1)
-; RV64I-LARGE-ZICFILP-NEXT: jalr t2
-; RV64I-LARGE-ZICFILP-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-LARGE-ZICFILP-NEXT: addi sp, sp, 16
-; RV64I-LARGE-ZICFILP-NEXT: ret
%1 = call i32 @dso_local_function(i32 %a)
ret i32 %1
}
@@ -174,11 +150,6 @@ define i32 @defined_function(i32 %a) nounwind {
; RV64I-LARGE-NEXT: addiw a0, a0, 1
; RV64I-LARGE-NEXT: ret
;
-; RV64I-LARGE-ZICFILP-LABEL: defined_function:
-; RV64I-LARGE-ZICFILP: # %bb.0:
-; RV64I-LARGE-ZICFILP-NEXT: lpad 0
-; RV64I-LARGE-ZICFILP-NEXT: addiw a0, a0, 1
-; RV64I-LARGE-ZICFILP-NEXT: ret
%1 = add i32 %a, 1
ret i32 %1
}
@@ -232,18 +203,6 @@ define i32 @test_call_defined(i32 %a) nounwind {
; RV64I-LARGE-NEXT: addi sp, sp, 16
; RV64I-LARGE-NEXT: ret
;
-; RV64I-LARGE-ZICFILP-LABEL: test_call_defined:
-; RV64I-LARGE-ZICFILP: # %bb.0:
-; RV64I-LARGE-ZICFILP-NEXT: lpad 0
-; RV64I-LARGE-ZICFILP-NEXT: addi sp, sp, -16
-; RV64I-LARGE-ZICFILP-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-LARGE-ZICFILP-NEXT: .Lpcrel_hi2:
-; RV64I-LARGE-ZICFILP-NEXT: auipc a1, %pcrel_hi(.LCPI3_0)
-; RV64I-LARGE-ZICFILP-NEXT: ld t2, %pcrel_lo(.Lpcrel_hi2)(a1)
-; RV64I-LARGE-ZICFILP-NEXT: jalr t2
-; RV64I-LARGE-ZICFILP-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-LARGE-ZICFILP-NEXT: addi sp, sp, 16
-; RV64I-LARGE-ZICFILP-NEXT: ret
%1 = call i32 @defined_function(i32 %a)
ret i32 %1
}
@@ -304,17 +263,6 @@ define i32 @test_call_indirect(ptr %a, i32 %b) nounwind {
; RV64I-LARGE-NEXT: addi sp, sp, 16
; RV64I-LARGE-NEXT: ret
;
-; RV64I-LARGE-ZICFILP-LABEL: test_call_indirect:
-; RV64I-LARGE-ZICFILP: # %bb.0:
-; RV64I-LARGE-ZICFILP-NEXT: lpad 0
-; RV64I-LARGE-ZICFILP-NEXT: addi sp, sp, -16
-; RV64I-LARGE-ZICFILP-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-LARGE-ZICFILP-NEXT: mv a2, a0
-; RV64I-LARGE-ZICFILP-NEXT: mv a0, a1
-; RV64I-LARGE-ZICFILP-NEXT: jalr a2
-; RV64I-LARGE-ZICFILP-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-LARGE-ZICFILP-NEXT: addi sp, sp, 16
-; RV64I-LARGE-ZICFILP-NEXT: ret
%1 = call i32 %a(i32 %b)
ret i32 %1
}
@@ -407,23 +355,6 @@ define i32 @test_call_indirect_no_t0(ptr %a, i32 %b, i32 %c, i32 %d, i32 %e, i32
; RV64I-LARGE-NEXT: addi sp, sp, 16
; RV64I-LARGE-NEXT: ret
;
-; RV64I-LARGE-ZICFILP-LABEL: test_call_indirect_no_t0:
-; RV64I-LARGE-ZICFILP: # %bb.0:
-; RV64I-LARGE-ZICFILP-NEXT: lpad 0
-; RV64I-LARGE-ZICFILP-NEXT: addi sp, sp, -16
-; RV64I-LARGE-ZICFILP-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-LARGE-ZICFILP-NEXT: mv t1, a0
-; RV64I-LARGE-ZICFILP-NEXT: mv a0, a1
-; RV64I-LARGE-ZICFILP-NEXT: mv a1, a2
-; RV64I-LARGE-ZICFILP-NEXT: mv a2, a3
-; RV64I-LARGE-ZICFILP-NEXT: mv a3, a4
-; RV64I-LARGE-ZICFILP-NEXT: mv a4, a5
-; RV64I-LARGE-ZICFILP-NEXT: mv a5, a6
-; RV64I-LARGE-ZICFILP-NEXT: mv a6, a7
-; RV64I-LARGE-ZICFILP-NEXT: jalr t1
-; RV64I-LARGE-ZICFILP-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-LARGE-ZICFILP-NEXT: addi sp, sp, 16
-; RV64I-LARGE-ZICFILP-NEXT: ret
%1 = call i32 %a(i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h)
ret i32 %1
}
@@ -457,11 +388,6 @@ define fastcc i32 @fastcc_function(i32 %a, i32 %b) nounwind {
; RV64I-LARGE-NEXT: addw a0, a0, a1
; RV64I-LARGE-NEXT: ret
;
-; RV64I-LARGE-ZICFILP-LABEL: fastcc_function:
-; RV64I-LARGE-ZICFILP: # %bb.0:
-; RV64I-LARGE-ZICFILP-NEXT: lpad 0
-; RV64I-LARGE-ZICFILP-NEXT: addw a0, a0, a1
-; RV64I-LARGE-ZICFILP-NEXT: ret
%1 = add i32 %a, %b
ret i32 %1
}
@@ -536,23 +462,6 @@ define i32 @test_call_fastcc(i32 %a, i32 %b) nounwind {
; RV64I-LARGE-NEXT: addi sp, sp, 16
; RV64I-LARGE-NEXT: ret
;
-; RV64I-LARGE-ZICFILP-LABEL: test_call_fastcc:
-; RV64I-LARGE-ZICFILP: # %bb.0:
-; RV64I-LARGE-ZICFILP-NEXT: lpad 0
-; RV64I-LARGE-ZICFILP-NEXT: addi sp, sp, -16
-; RV64I-LARGE-ZICFILP-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-LARGE-ZICFILP-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
-; RV64I-LARGE-ZICFILP-NEXT: mv s0, a0
-; RV64I-LARGE-ZICFILP-NEXT: .Lpcrel_hi3:
-; RV64I-LARGE-ZICFILP-NEXT: auipc a0, %pcrel_hi(.LCPI7_0)
-; RV64I-LARGE-ZICFILP-NEXT: ld t2, %pcrel_lo(.Lpcrel_hi3)(a0)
-; RV64I-LARGE-ZICFILP-NEXT: mv a0, s0
-; RV64I-LARGE-ZICFILP-NEXT: jalr t2
-; RV64I-LARGE-ZICFILP-NEXT: mv a0, s0
-; RV64I-LARGE-ZICFILP-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-LARGE-ZICFILP-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
-; RV64I-LARGE-ZICFILP-NEXT: addi sp, sp, 16
-; RV64I-LARGE-ZICFILP-NEXT: ret
%1 = call fastcc i32 @fastcc_function(i32 %a, i32 %b)
ret i32 %a
}
@@ -674,32 +583,6 @@ define i32 @test_call_external_many_args(i32 %a) nounwind {
; RV64I-LARGE-NEXT: addi sp, sp, 32
; RV64I-LARGE-NEXT: ret
;
-; RV64I-LARGE-ZICFILP-LABEL: test_call_external_many_args:
-; RV64I-LARGE-ZICFILP: # %bb.0:
-; RV64I-LARGE-ZICFILP-NEXT: lpad 0
-; RV64I-LARGE-ZICFILP-NEXT: addi sp, sp, -32
-; RV64I-LARGE-ZICFILP-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
-; RV64I-LARGE-ZICFILP-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
-; RV64I-LARGE-ZICFILP-NEXT: mv s0, a0
-; RV64I-LARGE-ZICFILP-NEXT: .Lpcrel_hi4:
-; RV64I-LARGE-ZICFILP-NEXT: auipc a0, %pcrel_hi(.LCPI8_0)
-; RV64I-LARGE-ZICFILP-NEXT: ld t2, %pcrel_lo(.Lpcrel_hi4)(a0)
-; RV64I-LARGE-ZICFILP-NEXT: sd s0, 0(sp)
-; RV64I-LARGE-ZICFILP-NEXT: sd s0, 8(sp)
-; RV64I-LARGE-ZICFILP-NEXT: mv a0, s0
-; RV64I-LARGE-ZICFILP-NEXT: mv a1, s0
-; RV64I-LARGE-ZICFILP-NEXT: mv a2, s0
-; RV64I-LARGE-ZICFILP-NEXT: mv a3, s0
-; RV64I-LARGE-ZICFILP-NEXT: mv a4, s0
-; RV64I-LARGE-ZICFILP-NEXT: mv a5, s0
-; RV64I-LARGE-ZICFILP-NEXT: mv a6, s0
-; RV64I-LARGE-ZICFILP-NEXT: mv a7, s0
-; RV64I-LARGE-ZICFILP-NEXT: jalr t2
-; RV64I-LARGE-ZICFILP-NEXT: mv a0, s0
-; RV64I-LARGE-ZICFILP-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
-; RV64I-LARGE-ZICFILP-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
-; RV64I-LARGE-ZICFILP-NEXT: addi sp, sp, 32
-; RV64I-LARGE-ZICFILP-NEXT: ret
%1 = call i32 @external_many_args(i32 %a, i32 %a, i32 %a, i32 %a, i32 %a,
i32 %a, i32 %a, i32 %a, i32 %a, i32 %a)
ret i32 %a
@@ -736,12 +619,6 @@ define i32 @defined_many_args(i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 %
; RV64I-LARGE-NEXT: addiw a0, a0, 1
; RV64I-LARGE-NEXT: ret
;
-; RV64I-LARGE-ZICFILP-LABEL: defined_many_args:
-; RV64I-LARGE-ZICFILP: # %bb.0:
-; RV64I-LARGE-ZICFILP-NEXT: lpad 0
-; RV64I-LARGE-ZICFILP-NEXT: lw a0, 8(sp)
-; RV64I-LARGE-ZICFILP-NEXT: addiw a0, a0, 1
-; RV64I-LARGE-ZICFILP-NEXT: ret
%added = add i32 %j, 1
ret i32 %added
}
@@ -840,27 +717,6 @@ define i32 @test_call_defined_many_args(i32 %a) nounwind {
; RV64I-LARGE-NEXT: addi sp, sp, 32
; RV64I-LARGE-NEXT: ret
;
-; RV64I-LARGE-ZICFILP-LABEL: test_call_defined_many_args:
-; RV64I-LARGE-ZICFILP: # %bb.0:
-; RV64I-LARGE-ZICFILP-NEXT: lpad 0
-; RV64I-LARGE-ZICFILP-NEXT: addi sp, sp, -32
-; RV64I-LARGE-ZICFILP-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
-; RV64I-LARGE-ZICFILP-NEXT: .Lpcrel_hi5:
-; RV64I-LARGE-ZICFILP-NEXT: auipc a1, %pcrel_hi(.LCPI10_0)
-; RV64I-LARGE-ZICFILP-NEXT: ld t2, %pcrel_lo(.Lpcrel_hi5)(a1)
-; RV64I-LARGE-ZICFILP-NEXT: sd a0, 0(sp)
-; RV64I-LARGE-ZICFILP-NEXT: sd a0, 8(sp)
-; RV64I-LARGE-ZICFILP-NEXT: mv a1, a0
-; RV64I-LARGE-ZICFILP-NEXT: mv a2, a0
-; RV64I-LARGE-ZICFILP-NEXT: mv a3, a0
-; RV64I-LARGE-ZICFILP-NEXT: mv a4, a0
-; RV64I-LARGE-ZICFILP-NEXT: mv a5, a0
-; RV64I-LARGE-ZICFILP-NEXT: mv a6, a0
-; RV64I-LARGE-ZICFILP-NEXT: mv a7, a0
-; RV64I-LARGE-ZICFILP-NEXT: jalr t2
-; RV64I-LARGE-ZICFILP-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
-; RV64I-LARGE-ZICFILP-NEXT: addi sp, sp, 32
-; RV64I-LARGE-ZICFILP-NEXT: ret
%1 = call i32 @defined_many_args(i32 %a, i32 %a, i32 %a, i32 %a, i32 %a,
i32 %a, i32 %a, i32 %a, i32 %a, i32 %a)
ret i32 %1
@@ -995,34 +851,6 @@ define fastcc void @fastcc_call_nonfastcc(){
; RV64I-LARGE-NEXT: .cfi_def_cfa_offset 0
; RV64I-LARGE-NEXT: ret
;
-; RV64I-LARGE-ZICFILP-LABEL: fastcc_call_nonfastcc:
-; RV64I-LARGE-ZICFILP: # %bb.0:
-; RV64I-LARGE-ZICFILP-NEXT: lpad 0
-; RV64I-LARGE-ZICFILP-NEXT: addi sp, sp, -32
-; RV64I-LARGE-ZICFILP-NEXT: .cfi_def_cfa_offset 32
-; RV64I-LARGE-ZICFILP-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
-; RV64I-LARGE-ZICFILP-NEXT: .cfi_offset ra, -8
-; RV64I-LARGE-ZICFILP-NEXT: li t0, 10
-; RV64I-LARGE-ZICFILP-NEXT: li t1, 9
-; RV64I-LARGE-ZICFILP-NEXT: .Lpcrel_hi6:
-; RV64I-LARGE-ZICFILP-NEXT: auipc a5, %pcrel_hi(.LCPI11_0)
-; RV64I-LARGE-ZICFILP-NEXT: li a0, 1
-; RV64I-LARGE-ZICFILP-NEXT: li a1, 2
-; RV64I-LARGE-ZICFILP-NEXT: li a2, 3
-; RV64I-LARGE-ZICFILP-NEXT: li a3, 4
-; RV64I-LARGE-ZICFILP-NEXT: li a4, 5
-; RV64I-LARGE-ZICFILP-NEXT: ld t2, %pcrel_lo(.Lpcrel_hi6)(a5)
-; RV64I-LARGE-ZICFILP-NEXT: li a5, 6
-; RV64I-LARGE-ZICFILP-NEXT: li a6, 7
-; RV64I-LARGE-ZICFILP-NEXT: li a7, 8
-; RV64I-LARGE-ZICFILP-NEXT: sd t1, 0(sp)
-; RV64I-LARGE-ZICFILP-NEXT: sd t0, 8(sp)
-; RV64I-LARGE-ZICFILP-NEXT: jalr t2
-; RV64I-LARGE-ZICFILP-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
-; RV64I-LARGE-ZICFILP-NEXT: .cfi_restore ra
-; RV64I-LARGE-ZICFILP-NEXT: addi sp, sp, 32
-; RV64I-LARGE-ZICFILP-NEXT: .cfi_def_cfa_offset 0
-; RV64I-LARGE-ZICFILP-NEXT: ret
call void @external_many_args(i32 1, i32 2,i32 3,i32 4,i32 5,i32 6,i32 7,i32 8,i32 9,i32 10)
ret void
}
diff --git a/llvm/test/CodeGen/RISCV/cf-branch-isel.ll b/llvm/test/CodeGen/RISCV/cf-branch-isel.ll
new file mode 100644
index 0000000000000..fc5d0277af71b
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/cf-branch-isel.ll
@@ -0,0 +1,46 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
+; RUN: llc -mtriple=riscv64 -stop-after=finalize-isel < %s | FileCheck %s
+
+; Test that with cf-protection-branch enabled, indirect branches/calls select
+; the NonX7 variants to avoid using X7 for the target address.
+
+ at brind.arr = internal unnamed_addr constant [2 x ptr] [ptr blockaddress(@brind, %bb1), ptr blockaddress(@brind, %bb2)], align 8
+ at x = dso_local global i32 0, align 4
+
+define void @brind(i32 noundef signext %0) {
+ ; CHECK-LABEL: name: brind
+ ; CHECK: PseudoBRINDNonX7 killed %{{[0-9]+}}, 0
+ %2 = sext i32 %0 to i64
+ %3 = getelementptr inbounds [2 x ptr], ptr @brind.arr, i64 0, i64 %2
+ %4 = load ptr, ptr %3, align 8
+ indirectbr ptr %4, [label %bb1, label %bb2]
+
+bb1:
+ %5 = load i32, ptr @x, align 4
+ %6 = add nsw i32 %5, 2
+ store i32 %6, ptr @x, align 4
+ br label %bb2
+
+bb2:
+ %7 = load i32, ptr @x, align 4
+ %8 = add nsw i32 %7, 1
+ store i32 %8, ptr @x, align 4
+ ret void
+}
+
+define i32 @indirect_call(ptr %0) {
+ ; CHECK-LABEL: name: indirect_call
+ ; CHECK: PseudoCALLIndirectNonX7
+ call void %0()
+ ret i32 0
+}
+
+define void @indirect_tail(ptr %0) {
+ ; CHECK-LABEL: name: indirect_tail
+ ; CHECK: PseudoTAILIndirectNonX7
+ tail call void %0()
+ ret void
+}
+
+!llvm.module.flags = !{!0}
+!0 = !{i32 8, !"cf-protection-branch", i32 1}
diff --git a/llvm/test/CodeGen/RISCV/jumptable-swguarded.ll b/llvm/test/CodeGen/RISCV/jumptable-swguarded.ll
index b4ab0585c0cc9..03e4c7e410b4f 100644
--- a/llvm/test/CodeGen/RISCV/jumptable-swguarded.ll
+++ b/llvm/test/CodeGen/RISCV/jumptable-swguarded.ll
@@ -1,8 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple riscv32 -mattr=+experimental-zicfilp < %s | FileCheck %s
-; RUN: llc -mtriple riscv64 -mattr=+experimental-zicfilp < %s | FileCheck %s
-; RUN: llc -mtriple riscv32 < %s | FileCheck %s --check-prefix=NO-ZICFILP
-; RUN: llc -mtriple riscv64 < %s | FileCheck %s --check-prefix=NO-ZICFILP
+; RUN: llc -mtriple riscv32 < %s | FileCheck %s
+; RUN: llc -mtriple riscv64 < %s | FileCheck %s
; Test using t2 to jump table branch.
define void @above_threshold(i32 signext %in, ptr %out) nounwind {
@@ -40,40 +38,6 @@ define void @above_threshold(i32 signext %in, ptr %out) nounwind {
; CHECK-NEXT: sw a0, 0(a1)
; CHECK-NEXT: .LBB0_9: # %exit
; CHECK-NEXT: ret
-;
-; NO-ZICFILP-LABEL: above_threshold:
-; NO-ZICFILP: # %bb.0: # %entry
-; NO-ZICFILP-NEXT: addi a0, a0, -1
-; NO-ZICFILP-NEXT: li a2, 5
-; NO-ZICFILP-NEXT: bltu a2, a0, .LBB0_9
-; NO-ZICFILP-NEXT: # %bb.1: # %entry
-; NO-ZICFILP-NEXT: slli a0, a0, 2
-; NO-ZICFILP-NEXT: lui a2, %hi(.LJTI0_0)
-; NO-ZICFILP-NEXT: addi a2, a2, %lo(.LJTI0_0)
-; NO-ZICFILP-NEXT: add a0, a2, a0
-; NO-ZICFILP-NEXT: lw a0, 0(a0)
-; NO-ZICFILP-NEXT: jr a0
-; NO-ZICFILP-NEXT: .LBB0_2: # %bb1
-; NO-ZICFILP-NEXT: li a0, 4
-; NO-ZICFILP-NEXT: j .LBB0_8
-; NO-ZICFILP-NEXT: .LBB0_3: # %bb5
-; NO-ZICFILP-NEXT: li a0, 100
-; NO-ZICFILP-NEXT: j .LBB0_8
-; NO-ZICFILP-NEXT: .LBB0_4: # %bb3
-; NO-ZICFILP-NEXT: li a0, 2
-; NO-ZICFILP-NEXT: j .LBB0_8
-; NO-ZICFILP-NEXT: .LBB0_5: # %bb4
-; NO-ZICFILP-NEXT: li a0, 1
-; NO-ZICFILP-NEXT: j .LBB0_8
-; NO-ZICFILP-NEXT: .LBB0_6: # %bb2
-; NO-ZICFILP-NEXT: li a0, 3
-; NO-ZICFILP-NEXT: j .LBB0_8
-; NO-ZICFILP-NEXT: .LBB0_7: # %bb6
-; NO-ZICFILP-NEXT: li a0, 200
-; NO-ZICFILP-NEXT: .LBB0_8: # %exit
-; NO-ZICFILP-NEXT: sw a0, 0(a1)
-; NO-ZICFILP-NEXT: .LBB0_9: # %exit
-; NO-ZICFILP-NEXT: ret
entry:
switch i32 %in, label %exit [
i32 1, label %bb1
@@ -104,3 +68,6 @@ bb6:
exit:
ret void
}
+
+!llvm.module.flags = !{!0}
+!0 = !{i32 8, !"cf-protection-branch", i32 1}
diff --git a/llvm/test/CodeGen/RISCV/lpad.ll b/llvm/test/CodeGen/RISCV/lpad.ll
index 28873ab6c49a4..71ad708e425a0 100644
--- a/llvm/test/CodeGen/RISCV/lpad.ll
+++ b/llvm/test/CodeGen/RISCV/lpad.ll
@@ -360,3 +360,6 @@ define i32 @test_returns_twice() {
%call = call i32 @setjmp(ptr %buf)
ret i32 %call
}
+
+!llvm.module.flags = !{!0}
+!0 = !{i32 8, !"cf-protection-branch", i32 1}
diff --git a/llvm/test/CodeGen/RISCV/nest-register.ll b/llvm/test/CodeGen/RISCV/nest-register.ll
index 6e892e05c4297..aaf8be4d2d8a1 100644
--- a/llvm/test/CodeGen/RISCV/nest-register.ll
+++ b/llvm/test/CodeGen/RISCV/nest-register.ll
@@ -4,7 +4,7 @@
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicfilp -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefix=RV64I-ZICFILP %s
+; RUN: | FileCheck -check-prefix=RV64I %s
; RUN: not llc -mtriple=riscv64 -target-abi=lp64e -mattr=+experimental-zicfilp \
; RUN: -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=LP64E-ZICFILP %s
@@ -14,28 +14,25 @@
define ptr @nest_receiver(ptr nest %arg) nounwind {
; RV32I-LABEL: nest_receiver:
; RV32I: # %bb.0:
-; RV32I-NEXT: mv a0, t2
+; RV32I-NEXT: lpad 0
+; RV32I-NEXT: mv a0, t3
; RV32I-NEXT: ret
;
; RV64I-LABEL: nest_receiver:
; RV64I: # %bb.0:
-; RV64I-NEXT: mv a0, t2
+; RV64I-NEXT: lpad 0
+; RV64I-NEXT: mv a0, t3
; RV64I-NEXT: ret
-;
-; RV64I-ZICFILP-LABEL: nest_receiver:
-; RV64I-ZICFILP: # %bb.0:
-; RV64I-ZICFILP-NEXT: lpad 0
-; RV64I-ZICFILP-NEXT: mv a0, t3
-; RV64I-ZICFILP-NEXT: ret
ret ptr %arg
}
define ptr @nest_caller(ptr %arg) nounwind {
; RV32I-LABEL: nest_caller:
; RV32I: # %bb.0:
+; RV32I-NEXT: lpad 0
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32I-NEXT: mv t2, a0
+; RV32I-NEXT: mv t3, a0
; RV32I-NEXT: call nest_receiver
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
@@ -43,24 +40,14 @@ define ptr @nest_caller(ptr %arg) nounwind {
;
; RV64I-LABEL: nest_caller:
; RV64I: # %bb.0:
+; RV64I-NEXT: lpad 0
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv t2, a0
+; RV64I-NEXT: mv t3, a0
; RV64I-NEXT: call nest_receiver
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
-;
-; RV64I-ZICFILP-LABEL: nest_caller:
-; RV64I-ZICFILP: # %bb.0:
-; RV64I-ZICFILP-NEXT: lpad 0
-; RV64I-ZICFILP-NEXT: addi sp, sp, -16
-; RV64I-ZICFILP-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-ZICFILP-NEXT: mv t3, a0
-; RV64I-ZICFILP-NEXT: call nest_receiver
-; RV64I-ZICFILP-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-ZICFILP-NEXT: addi sp, sp, 16
-; RV64I-ZICFILP-NEXT: ret
%result = call ptr @nest_receiver(ptr nest %arg)
ret ptr %result
}
diff --git a/llvm/test/CodeGen/RISCV/tail-calls.ll b/llvm/test/CodeGen/RISCV/tail-calls.ll
index 6756fea8a1f85..367e79930520e 100644
--- a/llvm/test/CodeGen/RISCV/tail-calls.ll
+++ b/llvm/test/CodeGen/RISCV/tail-calls.ll
@@ -14,11 +14,10 @@ define i32 @caller_tail(i32 %i) nounwind {
;
; CHECK-LARGE-ZICFILP-LABEL: caller_tail:
; CHECK-LARGE-ZICFILP: # %bb.0: # %entry
-; CHECK-LARGE-ZICFILP-NEXT: lpad 0
; CHECK-LARGE-ZICFILP-NEXT: .Lpcrel_hi0:
; CHECK-LARGE-ZICFILP-NEXT: auipc a1, %pcrel_hi(.LCPI0_0)
-; CHECK-LARGE-ZICFILP-NEXT: lw t2, %pcrel_lo(.Lpcrel_hi0)(a1)
-; CHECK-LARGE-ZICFILP-NEXT: jr t2
+; CHECK-LARGE-ZICFILP-NEXT: lw t1, %pcrel_lo(.Lpcrel_hi0)(a1)
+; CHECK-LARGE-ZICFILP-NEXT: jr t1
entry:
%r = tail call i32 @callee_tail(i32 %i)
ret i32 %r
@@ -39,18 +38,17 @@ define void @caller_extern(ptr %src) optsize {
;
; CHECK-LARGE-ZICFILP-LABEL: caller_extern:
; CHECK-LARGE-ZICFILP: # %bb.0: # %entry
-; CHECK-LARGE-ZICFILP-NEXT: lpad 0
; CHECK-LARGE-ZICFILP-NEXT: .Lpcrel_hi1:
; CHECK-LARGE-ZICFILP-NEXT: auipc a1, %pcrel_hi(.LCPI1_0)
; CHECK-LARGE-ZICFILP-NEXT: .Lpcrel_hi2:
; CHECK-LARGE-ZICFILP-NEXT: auipc a2, %pcrel_hi(.LCPI1_1)
; CHECK-LARGE-ZICFILP-NEXT: lw a1, %pcrel_lo(.Lpcrel_hi1)(a1)
-; CHECK-LARGE-ZICFILP-NEXT: lw t2, %pcrel_lo(.Lpcrel_hi2)(a2)
+; CHECK-LARGE-ZICFILP-NEXT: lw t1, %pcrel_lo(.Lpcrel_hi2)(a2)
; CHECK-LARGE-ZICFILP-NEXT: li a2, 7
; CHECK-LARGE-ZICFILP-NEXT: mv a3, a0
; CHECK-LARGE-ZICFILP-NEXT: mv a0, a1
; CHECK-LARGE-ZICFILP-NEXT: mv a1, a3
-; CHECK-LARGE-ZICFILP-NEXT: jr t2
+; CHECK-LARGE-ZICFILP-NEXT: jr t1
entry:
tail call void @llvm.memcpy.p0.p0.i32(ptr @dest, ptr %src, i32 7, i1 false)
ret void
@@ -71,18 +69,17 @@ define void @caller_extern_pgso(ptr %src) !prof !14 {
;
; CHECK-LARGE-ZICFILP-LABEL: caller_extern_pgso:
; CHECK-LARGE-ZICFILP: # %bb.0: # %entry
-; CHECK-LARGE-ZICFILP-NEXT: lpad 0
; CHECK-LARGE-ZICFILP-NEXT: .Lpcrel_hi3:
; CHECK-LARGE-ZICFILP-NEXT: auipc a1, %pcrel_hi(.LCPI2_0)
; CHECK-LARGE-ZICFILP-NEXT: .Lpcrel_hi4:
; CHECK-LARGE-ZICFILP-NEXT: auipc a2, %pcrel_hi(.LCPI2_1)
; CHECK-LARGE-ZICFILP-NEXT: lw a1, %pcrel_lo(.Lpcrel_hi3)(a1)
-; CHECK-LARGE-ZICFILP-NEXT: lw t2, %pcrel_lo(.Lpcrel_hi4)(a2)
+; CHECK-LARGE-ZICFILP-NEXT: lw t1, %pcrel_lo(.Lpcrel_hi4)(a2)
; CHECK-LARGE-ZICFILP-NEXT: li a2, 7
; CHECK-LARGE-ZICFILP-NEXT: mv a3, a0
; CHECK-LARGE-ZICFILP-NEXT: mv a0, a1
; CHECK-LARGE-ZICFILP-NEXT: mv a1, a3
-; CHECK-LARGE-ZICFILP-NEXT: jr t2
+; CHECK-LARGE-ZICFILP-NEXT: jr t1
entry:
tail call void @llvm.memcpy.p0.p0.i32(ptr @dest_pgso, ptr %src, i32 7, i1 false)
ret void
@@ -106,7 +103,6 @@ define void @caller_indirect_tail(i32 %a) nounwind {
;
; CHECK-LARGE-ZICFILP-LABEL: caller_indirect_tail:
; CHECK-LARGE-ZICFILP: # %bb.0: # %entry
-; CHECK-LARGE-ZICFILP-NEXT: lpad 0
; CHECK-LARGE-ZICFILP-NEXT: beqz a0, .LBB3_2
; CHECK-LARGE-ZICFILP-NEXT: # %bb.1: # %entry
; CHECK-LARGE-ZICFILP-NEXT: .Lpcrel_hi6:
@@ -142,7 +138,6 @@ define i32 @caller_indirect_no_t0(ptr %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5
;
; CHECK-LARGE-ZICFILP-LABEL: caller_indirect_no_t0:
; CHECK-LARGE-ZICFILP: # %bb.0:
-; CHECK-LARGE-ZICFILP-NEXT: lpad 0
; CHECK-LARGE-ZICFILP-NEXT: mv t1, a0
; CHECK-LARGE-ZICFILP-NEXT: mv a0, a1
; CHECK-LARGE-ZICFILP-NEXT: mv a1, a2
@@ -177,12 +172,11 @@ define void @caller_varargs(i32 %a, i32 %b) nounwind {
;
; CHECK-LARGE-ZICFILP-LABEL: caller_varargs:
; CHECK-LARGE-ZICFILP: # %bb.0: # %entry
-; CHECK-LARGE-ZICFILP-NEXT: lpad 0
; CHECK-LARGE-ZICFILP-NEXT: addi sp, sp, -16
; CHECK-LARGE-ZICFILP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; CHECK-LARGE-ZICFILP-NEXT: .Lpcrel_hi7:
; CHECK-LARGE-ZICFILP-NEXT: auipc a2, %pcrel_hi(.LCPI5_0)
-; CHECK-LARGE-ZICFILP-NEXT: lw t2, %pcrel_lo(.Lpcrel_hi7)(a2)
+; CHECK-LARGE-ZICFILP-NEXT: lw t1, %pcrel_lo(.Lpcrel_hi7)(a2)
; CHECK-LARGE-ZICFILP-NEXT: sw a0, 0(sp)
; CHECK-LARGE-ZICFILP-NEXT: mv a2, a1
; CHECK-LARGE-ZICFILP-NEXT: mv a3, a0
@@ -190,7 +184,7 @@ define void @caller_varargs(i32 %a, i32 %b) nounwind {
; CHECK-LARGE-ZICFILP-NEXT: mv a5, a1
; CHECK-LARGE-ZICFILP-NEXT: mv a6, a1
; CHECK-LARGE-ZICFILP-NEXT: mv a7, a0
-; CHECK-LARGE-ZICFILP-NEXT: jalr t2
+; CHECK-LARGE-ZICFILP-NEXT: jalr t1
; CHECK-LARGE-ZICFILP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; CHECK-LARGE-ZICFILP-NEXT: addi sp, sp, 16
; CHECK-LARGE-ZICFILP-NEXT: ret
@@ -225,25 +219,24 @@ define i32 @caller_args(i32 %a, i32 %b, i32 %c, i32 %dd, i32 %e, i32 %ff, i32 %g
;
; CHECK-LARGE-ZICFILP-LABEL: caller_args:
; CHECK-LARGE-ZICFILP: # %bb.0: # %entry
-; CHECK-LARGE-ZICFILP-NEXT: lpad 0
; CHECK-LARGE-ZICFILP-NEXT: addi sp, sp, -32
; CHECK-LARGE-ZICFILP-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; CHECK-LARGE-ZICFILP-NEXT: lw t0, 32(sp)
; CHECK-LARGE-ZICFILP-NEXT: lw t1, 36(sp)
-; CHECK-LARGE-ZICFILP-NEXT: lw t3, 40(sp)
-; CHECK-LARGE-ZICFILP-NEXT: lw t4, 44(sp)
-; CHECK-LARGE-ZICFILP-NEXT: lw t2, 48(sp)
+; CHECK-LARGE-ZICFILP-NEXT: lw t2, 40(sp)
+; CHECK-LARGE-ZICFILP-NEXT: lw t3, 44(sp)
+; CHECK-LARGE-ZICFILP-NEXT: lw t4, 48(sp)
; CHECK-LARGE-ZICFILP-NEXT: lw t5, 52(sp)
-; CHECK-LARGE-ZICFILP-NEXT: sw t2, 16(sp)
+; CHECK-LARGE-ZICFILP-NEXT: sw t4, 16(sp)
; CHECK-LARGE-ZICFILP-NEXT: sw t5, 20(sp)
; CHECK-LARGE-ZICFILP-NEXT: .Lpcrel_hi8:
-; CHECK-LARGE-ZICFILP-NEXT: auipc t2, %pcrel_hi(.LCPI6_0)
-; CHECK-LARGE-ZICFILP-NEXT: lw t2, %pcrel_lo(.Lpcrel_hi8)(t2)
+; CHECK-LARGE-ZICFILP-NEXT: auipc t4, %pcrel_hi(.LCPI6_0)
+; CHECK-LARGE-ZICFILP-NEXT: lw t4, %pcrel_lo(.Lpcrel_hi8)(t4)
; CHECK-LARGE-ZICFILP-NEXT: sw t0, 0(sp)
; CHECK-LARGE-ZICFILP-NEXT: sw t1, 4(sp)
-; CHECK-LARGE-ZICFILP-NEXT: sw t3, 8(sp)
-; CHECK-LARGE-ZICFILP-NEXT: sw t4, 12(sp)
-; CHECK-LARGE-ZICFILP-NEXT: jalr t2
+; CHECK-LARGE-ZICFILP-NEXT: sw t2, 8(sp)
+; CHECK-LARGE-ZICFILP-NEXT: sw t3, 12(sp)
+; CHECK-LARGE-ZICFILP-NEXT: jalr t4
; CHECK-LARGE-ZICFILP-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; CHECK-LARGE-ZICFILP-NEXT: addi sp, sp, 32
; CHECK-LARGE-ZICFILP-NEXT: ret
@@ -272,19 +265,18 @@ define void @caller_indirect_args() nounwind {
;
; CHECK-LARGE-ZICFILP-LABEL: caller_indirect_args:
; CHECK-LARGE-ZICFILP: # %bb.0: # %entry
-; CHECK-LARGE-ZICFILP-NEXT: lpad 0
; CHECK-LARGE-ZICFILP-NEXT: addi sp, sp, -32
; CHECK-LARGE-ZICFILP-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; CHECK-LARGE-ZICFILP-NEXT: lui a1, 262128
; CHECK-LARGE-ZICFILP-NEXT: .Lpcrel_hi9:
; CHECK-LARGE-ZICFILP-NEXT: auipc a0, %pcrel_hi(.LCPI7_0)
-; CHECK-LARGE-ZICFILP-NEXT: lw t2, %pcrel_lo(.Lpcrel_hi9)(a0)
+; CHECK-LARGE-ZICFILP-NEXT: lw a2, %pcrel_lo(.Lpcrel_hi9)(a0)
; CHECK-LARGE-ZICFILP-NEXT: mv a0, sp
; CHECK-LARGE-ZICFILP-NEXT: sw zero, 0(sp)
; CHECK-LARGE-ZICFILP-NEXT: sw zero, 4(sp)
; CHECK-LARGE-ZICFILP-NEXT: sw zero, 8(sp)
; CHECK-LARGE-ZICFILP-NEXT: sw a1, 12(sp)
-; CHECK-LARGE-ZICFILP-NEXT: jalr t2
+; CHECK-LARGE-ZICFILP-NEXT: jalr a2
; CHECK-LARGE-ZICFILP-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; CHECK-LARGE-ZICFILP-NEXT: addi sp, sp, 32
; CHECK-LARGE-ZICFILP-NEXT: ret
@@ -302,11 +294,10 @@ define void @caller_weak() nounwind {
;
; CHECK-LARGE-ZICFILP-LABEL: caller_weak:
; CHECK-LARGE-ZICFILP: # %bb.0: # %entry
-; CHECK-LARGE-ZICFILP-NEXT: lpad 0
; CHECK-LARGE-ZICFILP-NEXT: .Lpcrel_hi10:
; CHECK-LARGE-ZICFILP-NEXT: auipc a0, %pcrel_hi(.LCPI8_0)
-; CHECK-LARGE-ZICFILP-NEXT: lw t2, %pcrel_lo(.Lpcrel_hi10)(a0)
-; CHECK-LARGE-ZICFILP-NEXT: jr t2
+; CHECK-LARGE-ZICFILP-NEXT: lw t1, %pcrel_lo(.Lpcrel_hi10)(a0)
+; CHECK-LARGE-ZICFILP-NEXT: jr t1
entry:
tail call void @callee_weak()
ret void
@@ -377,8 +368,8 @@ define void @caller_irq() nounwind "interrupt"="machine" {
; CHECK-LARGE-ZICFILP-NEXT: sw t6, 0(sp) # 4-byte Folded Spill
; CHECK-LARGE-ZICFILP-NEXT: .Lpcrel_hi11:
; CHECK-LARGE-ZICFILP-NEXT: auipc a0, %pcrel_hi(.LCPI9_0)
-; CHECK-LARGE-ZICFILP-NEXT: lw t2, %pcrel_lo(.Lpcrel_hi11)(a0)
-; CHECK-LARGE-ZICFILP-NEXT: jalr t2
+; CHECK-LARGE-ZICFILP-NEXT: lw a0, %pcrel_lo(.Lpcrel_hi11)(a0)
+; CHECK-LARGE-ZICFILP-NEXT: jalr a0
; CHECK-LARGE-ZICFILP-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
; CHECK-LARGE-ZICFILP-NEXT: lw t0, 56(sp) # 4-byte Folded Reload
; CHECK-LARGE-ZICFILP-NEXT: lw t1, 52(sp) # 4-byte Folded Reload
@@ -421,16 +412,15 @@ define i32 @caller_byval() nounwind {
;
; CHECK-LARGE-ZICFILP-LABEL: caller_byval:
; CHECK-LARGE-ZICFILP: # %bb.0: # %entry
-; CHECK-LARGE-ZICFILP-NEXT: lpad 0
; CHECK-LARGE-ZICFILP-NEXT: addi sp, sp, -16
; CHECK-LARGE-ZICFILP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; CHECK-LARGE-ZICFILP-NEXT: lw a0, 8(sp)
; CHECK-LARGE-ZICFILP-NEXT: sw a0, 4(sp)
; CHECK-LARGE-ZICFILP-NEXT: .Lpcrel_hi12:
; CHECK-LARGE-ZICFILP-NEXT: auipc a0, %pcrel_hi(.LCPI10_0)
-; CHECK-LARGE-ZICFILP-NEXT: lw t2, %pcrel_lo(.Lpcrel_hi12)(a0)
+; CHECK-LARGE-ZICFILP-NEXT: lw a1, %pcrel_lo(.Lpcrel_hi12)(a0)
; CHECK-LARGE-ZICFILP-NEXT: addi a0, sp, 4
-; CHECK-LARGE-ZICFILP-NEXT: jalr t2
+; CHECK-LARGE-ZICFILP-NEXT: jalr a1
; CHECK-LARGE-ZICFILP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; CHECK-LARGE-ZICFILP-NEXT: addi sp, sp, 16
; CHECK-LARGE-ZICFILP-NEXT: ret
@@ -459,7 +449,6 @@ define void @caller_nostruct() nounwind {
;
; CHECK-LARGE-ZICFILP-LABEL: caller_nostruct:
; CHECK-LARGE-ZICFILP: # %bb.0: # %entry
-; CHECK-LARGE-ZICFILP-NEXT: lpad 0
; CHECK-LARGE-ZICFILP-NEXT: addi sp, sp, -16
; CHECK-LARGE-ZICFILP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; CHECK-LARGE-ZICFILP-NEXT: .Lpcrel_hi13:
@@ -467,8 +456,8 @@ define void @caller_nostruct() nounwind {
; CHECK-LARGE-ZICFILP-NEXT: .Lpcrel_hi14:
; CHECK-LARGE-ZICFILP-NEXT: auipc a1, %pcrel_hi(.LCPI11_1)
; CHECK-LARGE-ZICFILP-NEXT: lw a0, %pcrel_lo(.Lpcrel_hi13)(a0)
-; CHECK-LARGE-ZICFILP-NEXT: lw t2, %pcrel_lo(.Lpcrel_hi14)(a1)
-; CHECK-LARGE-ZICFILP-NEXT: jalr t2
+; CHECK-LARGE-ZICFILP-NEXT: lw a1, %pcrel_lo(.Lpcrel_hi14)(a1)
+; CHECK-LARGE-ZICFILP-NEXT: jalr a1
; CHECK-LARGE-ZICFILP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; CHECK-LARGE-ZICFILP-NEXT: addi sp, sp, 16
; CHECK-LARGE-ZICFILP-NEXT: ret
@@ -491,13 +480,12 @@ define void @caller_struct(ptr sret(%struct.A) %a) nounwind {
;
; CHECK-LARGE-ZICFILP-LABEL: caller_struct:
; CHECK-LARGE-ZICFILP: # %bb.0: # %entry
-; CHECK-LARGE-ZICFILP-NEXT: lpad 0
; CHECK-LARGE-ZICFILP-NEXT: addi sp, sp, -16
; CHECK-LARGE-ZICFILP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; CHECK-LARGE-ZICFILP-NEXT: .Lpcrel_hi15:
; CHECK-LARGE-ZICFILP-NEXT: auipc a0, %pcrel_hi(.LCPI12_0)
-; CHECK-LARGE-ZICFILP-NEXT: lw t2, %pcrel_lo(.Lpcrel_hi15)(a0)
-; CHECK-LARGE-ZICFILP-NEXT: jalr t2
+; CHECK-LARGE-ZICFILP-NEXT: lw a0, %pcrel_lo(.Lpcrel_hi15)(a0)
+; CHECK-LARGE-ZICFILP-NEXT: jalr a0
; CHECK-LARGE-ZICFILP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; CHECK-LARGE-ZICFILP-NEXT: addi sp, sp, 16
; CHECK-LARGE-ZICFILP-NEXT: ret
@@ -519,13 +507,12 @@ define i32 @disable_tail_calls(i32 %i) nounwind "disable-tail-calls"="true" {
;
; CHECK-LARGE-ZICFILP-LABEL: disable_tail_calls:
; CHECK-LARGE-ZICFILP: # %bb.0: # %entry
-; CHECK-LARGE-ZICFILP-NEXT: lpad 0
; CHECK-LARGE-ZICFILP-NEXT: addi sp, sp, -16
; CHECK-LARGE-ZICFILP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; CHECK-LARGE-ZICFILP-NEXT: .Lpcrel_hi16:
; CHECK-LARGE-ZICFILP-NEXT: auipc a1, %pcrel_hi(.LCPI13_0)
-; CHECK-LARGE-ZICFILP-NEXT: lw t2, %pcrel_lo(.Lpcrel_hi16)(a1)
-; CHECK-LARGE-ZICFILP-NEXT: jalr t2
+; CHECK-LARGE-ZICFILP-NEXT: lw a1, %pcrel_lo(.Lpcrel_hi16)(a1)
+; CHECK-LARGE-ZICFILP-NEXT: jalr a1
; CHECK-LARGE-ZICFILP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; CHECK-LARGE-ZICFILP-NEXT: addi sp, sp, 16
; CHECK-LARGE-ZICFILP-NEXT: ret
@@ -558,7 +545,6 @@ define i32 @duplicate_returns(i32 %a, i32 %b) nounwind {
;
; CHECK-LARGE-ZICFILP-LABEL: duplicate_returns:
; CHECK-LARGE-ZICFILP: # %bb.0: # %entry
-; CHECK-LARGE-ZICFILP-NEXT: lpad 0
; CHECK-LARGE-ZICFILP-NEXT: beqz a0, .LBB14_4
; CHECK-LARGE-ZICFILP-NEXT: # %bb.1: # %if.else
; CHECK-LARGE-ZICFILP-NEXT: beqz a1, .LBB14_5
@@ -567,23 +553,23 @@ define i32 @duplicate_returns(i32 %a, i32 %b) nounwind {
; CHECK-LARGE-ZICFILP-NEXT: # %bb.3: # %if.then6
; CHECK-LARGE-ZICFILP-NEXT: .Lpcrel_hi19:
; CHECK-LARGE-ZICFILP-NEXT: auipc a0, %pcrel_hi(.LCPI14_1)
-; CHECK-LARGE-ZICFILP-NEXT: lw t2, %pcrel_lo(.Lpcrel_hi19)(a0)
-; CHECK-LARGE-ZICFILP-NEXT: jr t2
+; CHECK-LARGE-ZICFILP-NEXT: lw t1, %pcrel_lo(.Lpcrel_hi19)(a0)
+; CHECK-LARGE-ZICFILP-NEXT: jr t1
; CHECK-LARGE-ZICFILP-NEXT: .LBB14_4: # %if.then
; CHECK-LARGE-ZICFILP-NEXT: .Lpcrel_hi17:
; CHECK-LARGE-ZICFILP-NEXT: auipc a0, %pcrel_hi(.LCPI14_3)
-; CHECK-LARGE-ZICFILP-NEXT: lw t2, %pcrel_lo(.Lpcrel_hi17)(a0)
-; CHECK-LARGE-ZICFILP-NEXT: jr t2
+; CHECK-LARGE-ZICFILP-NEXT: lw t1, %pcrel_lo(.Lpcrel_hi17)(a0)
+; CHECK-LARGE-ZICFILP-NEXT: jr t1
; CHECK-LARGE-ZICFILP-NEXT: .LBB14_5: # %if.then2
; CHECK-LARGE-ZICFILP-NEXT: .Lpcrel_hi18:
; CHECK-LARGE-ZICFILP-NEXT: auipc a0, %pcrel_hi(.LCPI14_2)
-; CHECK-LARGE-ZICFILP-NEXT: lw t2, %pcrel_lo(.Lpcrel_hi18)(a0)
-; CHECK-LARGE-ZICFILP-NEXT: jr t2
+; CHECK-LARGE-ZICFILP-NEXT: lw t1, %pcrel_lo(.Lpcrel_hi18)(a0)
+; CHECK-LARGE-ZICFILP-NEXT: jr t1
; CHECK-LARGE-ZICFILP-NEXT: .LBB14_6: # %if.else8
; CHECK-LARGE-ZICFILP-NEXT: .Lpcrel_hi20:
; CHECK-LARGE-ZICFILP-NEXT: auipc a0, %pcrel_hi(.LCPI14_0)
-; CHECK-LARGE-ZICFILP-NEXT: lw t2, %pcrel_lo(.Lpcrel_hi20)(a0)
-; CHECK-LARGE-ZICFILP-NEXT: jr t2
+; CHECK-LARGE-ZICFILP-NEXT: lw t1, %pcrel_lo(.Lpcrel_hi20)(a0)
+; CHECK-LARGE-ZICFILP-NEXT: jr t1
entry:
%cmp = icmp eq i32 %a, 0
br i1 %cmp, label %if.then, label %if.else
diff --git a/llvm/test/CodeGen/RISCV/tail-cf-branch.ll b/llvm/test/CodeGen/RISCV/tail-cf-branch.ll
new file mode 100644
index 0000000000000..7b0fc9b6f5992
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/tail-cf-branch.ll
@@ -0,0 +1,236 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV32I %s
+; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV64I %s
+; RUN: llc -code-model=large -mtriple=riscv32 -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV32I-LARGE %s
+; RUN: llc -code-model=large -mtriple=riscv64 -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV64I-LARGE %s
+
+; Test tail call generation with cf-protection-branch enabled.
+; This tests landing pad generation and NonX7 variants for indirect tail calls.
+
+declare i32 @callee_tail(i32 %i)
+
+define i32 @caller_tail(i32 %i) nounwind {
+; RV32I-LABEL: caller_tail:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lpad 0
+; RV32I-NEXT: tail callee_tail
+;
+; RV64I-LABEL: caller_tail:
+; RV64I: # %bb.0: # %entry
+; RV64I-NEXT: lpad 0
+; RV64I-NEXT: tail callee_tail
+;
+; RV32I-LARGE-LABEL: caller_tail:
+; RV32I-LARGE: # %bb.0: # %entry
+; RV32I-LARGE-NEXT: lpad 0
+; RV32I-LARGE-NEXT: .Lpcrel_hi0:
+; RV32I-LARGE-NEXT: auipc a1, %pcrel_hi(.LCPI0_0)
+; RV32I-LARGE-NEXT: lw t2, %pcrel_lo(.Lpcrel_hi0)(a1)
+; RV32I-LARGE-NEXT: jr t2
+;
+; RV64I-LARGE-LABEL: caller_tail:
+; RV64I-LARGE: # %bb.0: # %entry
+; RV64I-LARGE-NEXT: lpad 0
+; RV64I-LARGE-NEXT: .Lpcrel_hi0:
+; RV64I-LARGE-NEXT: auipc a1, %pcrel_hi(.LCPI0_0)
+; RV64I-LARGE-NEXT: ld t2, %pcrel_lo(.Lpcrel_hi0)(a1)
+; RV64I-LARGE-NEXT: jr t2
+entry:
+ %r = tail call i32 @callee_tail(i32 %i)
+ ret i32 %r
+}
+
+ at dest = global [2 x i8] zeroinitializer
+
+define void @caller_extern(ptr %src) optsize {
+; RV32I-LABEL: caller_extern:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lpad 0
+; RV32I-NEXT: lui a1, %hi(dest)
+; RV32I-NEXT: addi a1, a1, %lo(dest)
+; RV32I-NEXT: li a2, 7
+; RV32I-NEXT: mv a3, a0
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: mv a1, a3
+; RV32I-NEXT: tail memcpy
+;
+; RV64I-LABEL: caller_extern:
+; RV64I: # %bb.0: # %entry
+; RV64I-NEXT: lpad 0
+; RV64I-NEXT: lui a1, %hi(dest)
+; RV64I-NEXT: addi a1, a1, %lo(dest)
+; RV64I-NEXT: li a2, 7
+; RV64I-NEXT: mv a3, a0
+; RV64I-NEXT: mv a0, a1
+; RV64I-NEXT: mv a1, a3
+; RV64I-NEXT: tail memcpy
+;
+; RV32I-LARGE-LABEL: caller_extern:
+; RV32I-LARGE: # %bb.0: # %entry
+; RV32I-LARGE-NEXT: lpad 0
+; RV32I-LARGE-NEXT: .Lpcrel_hi1:
+; RV32I-LARGE-NEXT: auipc a1, %pcrel_hi(.LCPI1_0)
+; RV32I-LARGE-NEXT: .Lpcrel_hi2:
+; RV32I-LARGE-NEXT: auipc a2, %pcrel_hi(.LCPI1_1)
+; RV32I-LARGE-NEXT: lw a1, %pcrel_lo(.Lpcrel_hi1)(a1)
+; RV32I-LARGE-NEXT: lw t2, %pcrel_lo(.Lpcrel_hi2)(a2)
+; RV32I-LARGE-NEXT: li a2, 7
+; RV32I-LARGE-NEXT: mv a3, a0
+; RV32I-LARGE-NEXT: mv a0, a1
+; RV32I-LARGE-NEXT: mv a1, a3
+; RV32I-LARGE-NEXT: jr t2
+;
+; RV64I-LARGE-LABEL: caller_extern:
+; RV64I-LARGE: # %bb.0: # %entry
+; RV64I-LARGE-NEXT: lpad 0
+; RV64I-LARGE-NEXT: .Lpcrel_hi1:
+; RV64I-LARGE-NEXT: auipc a1, %pcrel_hi(.LCPI1_0)
+; RV64I-LARGE-NEXT: .Lpcrel_hi2:
+; RV64I-LARGE-NEXT: auipc a2, %pcrel_hi(.LCPI1_1)
+; RV64I-LARGE-NEXT: ld a1, %pcrel_lo(.Lpcrel_hi1)(a1)
+; RV64I-LARGE-NEXT: ld t2, %pcrel_lo(.Lpcrel_hi2)(a2)
+; RV64I-LARGE-NEXT: li a2, 7
+; RV64I-LARGE-NEXT: mv a3, a0
+; RV64I-LARGE-NEXT: mv a0, a1
+; RV64I-LARGE-NEXT: mv a1, a3
+; RV64I-LARGE-NEXT: jr t2
+entry:
+ tail call void @llvm.memcpy.p0.p0.i32(ptr @dest, ptr %src, i32 7, i1 false)
+ ret void
+}
+
+declare void @llvm.memcpy.p0.p0.i32(ptr, ptr, i32, i1)
+
+; Indirect tail call
+declare void @callee_indirect1()
+declare void @callee_indirect2()
+
+define void @caller_indirect_tail(i32 %a) nounwind {
+; RV32I-LABEL: caller_indirect_tail:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lpad 0
+; RV32I-NEXT: beqz a0, .LBB2_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: lui t1, %hi(callee_indirect2)
+; RV32I-NEXT: addi t1, t1, %lo(callee_indirect2)
+; RV32I-NEXT: jr t1
+; RV32I-NEXT: .LBB2_2:
+; RV32I-NEXT: lui t1, %hi(callee_indirect1)
+; RV32I-NEXT: addi t1, t1, %lo(callee_indirect1)
+; RV32I-NEXT: jr t1
+;
+; RV64I-LABEL: caller_indirect_tail:
+; RV64I: # %bb.0: # %entry
+; RV64I-NEXT: lpad 0
+; RV64I-NEXT: sext.w a0, a0
+; RV64I-NEXT: beqz a0, .LBB2_2
+; RV64I-NEXT: # %bb.1: # %entry
+; RV64I-NEXT: lui t1, %hi(callee_indirect2)
+; RV64I-NEXT: addi t1, t1, %lo(callee_indirect2)
+; RV64I-NEXT: jr t1
+; RV64I-NEXT: .LBB2_2:
+; RV64I-NEXT: lui t1, %hi(callee_indirect1)
+; RV64I-NEXT: addi t1, t1, %lo(callee_indirect1)
+; RV64I-NEXT: jr t1
+;
+; RV32I-LARGE-LABEL: caller_indirect_tail:
+; RV32I-LARGE: # %bb.0: # %entry
+; RV32I-LARGE-NEXT: lpad 0
+; RV32I-LARGE-NEXT: beqz a0, .LBB2_2
+; RV32I-LARGE-NEXT: # %bb.1: # %entry
+; RV32I-LARGE-NEXT: .Lpcrel_hi4:
+; RV32I-LARGE-NEXT: auipc a0, %pcrel_hi(.LCPI2_0)
+; RV32I-LARGE-NEXT: lw t1, %pcrel_lo(.Lpcrel_hi4)(a0)
+; RV32I-LARGE-NEXT: jr t1
+; RV32I-LARGE-NEXT: .LBB2_2:
+; RV32I-LARGE-NEXT: .Lpcrel_hi3:
+; RV32I-LARGE-NEXT: auipc a0, %pcrel_hi(.LCPI2_1)
+; RV32I-LARGE-NEXT: lw t1, %pcrel_lo(.Lpcrel_hi3)(a0)
+; RV32I-LARGE-NEXT: jr t1
+;
+; RV64I-LARGE-LABEL: caller_indirect_tail:
+; RV64I-LARGE: # %bb.0: # %entry
+; RV64I-LARGE-NEXT: lpad 0
+; RV64I-LARGE-NEXT: sext.w a0, a0
+; RV64I-LARGE-NEXT: beqz a0, .LBB2_2
+; RV64I-LARGE-NEXT: # %bb.1: # %entry
+; RV64I-LARGE-NEXT: .Lpcrel_hi4:
+; RV64I-LARGE-NEXT: auipc a0, %pcrel_hi(.LCPI2_0)
+; RV64I-LARGE-NEXT: ld t1, %pcrel_lo(.Lpcrel_hi4)(a0)
+; RV64I-LARGE-NEXT: jr t1
+; RV64I-LARGE-NEXT: .LBB2_2:
+; RV64I-LARGE-NEXT: .Lpcrel_hi3:
+; RV64I-LARGE-NEXT: auipc a0, %pcrel_hi(.LCPI2_1)
+; RV64I-LARGE-NEXT: ld t1, %pcrel_lo(.Lpcrel_hi3)(a0)
+; RV64I-LARGE-NEXT: jr t1
+entry:
+ %tobool = icmp eq i32 %a, 0
+ %callee = select i1 %tobool, ptr @callee_indirect1, ptr @callee_indirect2
+ tail call void %callee()
+ ret void
+}
+
+; Make sure we don't use t0 as the source for jr as that is a hint to pop the
+; return address stack on some microarchitectures.
+define i32 @caller_indirect_no_t0(ptr %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6, i32 %7) nounwind {
+; RV32I-LABEL: caller_indirect_no_t0:
+; RV32I: # %bb.0:
+; RV32I-NEXT: lpad 0
+; RV32I-NEXT: mv t1, a0
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: mv a1, a2
+; RV32I-NEXT: mv a2, a3
+; RV32I-NEXT: mv a3, a4
+; RV32I-NEXT: mv a4, a5
+; RV32I-NEXT: mv a5, a6
+; RV32I-NEXT: mv a6, a7
+; RV32I-NEXT: jr t1
+;
+; RV64I-LABEL: caller_indirect_no_t0:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lpad 0
+; RV64I-NEXT: mv t1, a0
+; RV64I-NEXT: mv a0, a1
+; RV64I-NEXT: mv a1, a2
+; RV64I-NEXT: mv a2, a3
+; RV64I-NEXT: mv a3, a4
+; RV64I-NEXT: mv a4, a5
+; RV64I-NEXT: mv a5, a6
+; RV64I-NEXT: mv a6, a7
+; RV64I-NEXT: jr t1
+;
+; RV32I-LARGE-LABEL: caller_indirect_no_t0:
+; RV32I-LARGE: # %bb.0:
+; RV32I-LARGE-NEXT: lpad 0
+; RV32I-LARGE-NEXT: mv t1, a0
+; RV32I-LARGE-NEXT: mv a0, a1
+; RV32I-LARGE-NEXT: mv a1, a2
+; RV32I-LARGE-NEXT: mv a2, a3
+; RV32I-LARGE-NEXT: mv a3, a4
+; RV32I-LARGE-NEXT: mv a4, a5
+; RV32I-LARGE-NEXT: mv a5, a6
+; RV32I-LARGE-NEXT: mv a6, a7
+; RV32I-LARGE-NEXT: jr t1
+;
+; RV64I-LARGE-LABEL: caller_indirect_no_t0:
+; RV64I-LARGE: # %bb.0:
+; RV64I-LARGE-NEXT: lpad 0
+; RV64I-LARGE-NEXT: mv t1, a0
+; RV64I-LARGE-NEXT: mv a0, a1
+; RV64I-LARGE-NEXT: mv a1, a2
+; RV64I-LARGE-NEXT: mv a2, a3
+; RV64I-LARGE-NEXT: mv a3, a4
+; RV64I-LARGE-NEXT: mv a4, a5
+; RV64I-LARGE-NEXT: mv a5, a6
+; RV64I-LARGE-NEXT: mv a6, a7
+; RV64I-LARGE-NEXT: jr t1
+ %9 = tail call i32 %0(i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6, i32 %7)
+ ret i32 %9
+}
+
+!llvm.module.flags = !{!0}
+!0 = !{i32 8, !"cf-protection-branch", i32 1}
diff --git a/llvm/test/CodeGen/RISCV/zicfilp-indirect-branch.ll b/llvm/test/CodeGen/RISCV/zicfilp-indirect-branch.ll
index bccd28ee7e2b3..7f7c8fcd380d3 100644
--- a/llvm/test/CodeGen/RISCV/zicfilp-indirect-branch.ll
+++ b/llvm/test/CodeGen/RISCV/zicfilp-indirect-branch.ll
@@ -1,15 +1,17 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
; RUN: llc -mtriple=riscv64 -stop-after=finalize-isel < %s | FileCheck %s
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicfilp -stop-after=finalize-isel < %s | FileCheck -check-prefixes=ZICFILP %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicfilp -stop-after=finalize-isel < %s | FileCheck %s
+
+; Test that indirect branches/calls use NonX7 variants when cf-protection-branch
+; module flag is set, regardless of whether Zicfilp extension is enabled.
+; The NonX7 variants are selected based on cf-protection-branch, not Zicfilp.
@brind.arr = internal unnamed_addr constant [2 x ptr] [ptr blockaddress(@brind, %5), ptr blockaddress(@brind, %8)], align 8
@x = dso_local global i32 0, align 4
define void @brind(i32 noundef signext %0) {
; CHECK-LABEL: name: brind
- ; CHECK: PseudoBRIND killed [[VAR:%.*]], 0
- ; ZICFILP-LABEL: name: brind
- ; ZICFILP: PseudoBRINDNonX7 killed [[VAR:%.*]], 0
+ ; CHECK: PseudoBRINDNonX7 killed [[VAR:%.*]], 0
%2 = sext i32 %0 to i64
%3 = getelementptr inbounds [2 x ptr], ptr @brind.arr, i64 0, i64 %2
%4 = load ptr, ptr %3, align 8
@@ -30,9 +32,7 @@ define void @brind(i32 noundef signext %0) {
define i32 @indirect_call(ptr %0) {
; CHECK-LABEL: name: indirect_call
- ; CHECK: PseudoCALLIndirect
- ; ZICFILP-LABEL: name: indirect_call
- ; ZICFILP: PseudoCALLIndirectNonX7
+ ; CHECK: PseudoCALLIndirectNonX7
call void %0()
ret i32 0
}
@@ -40,9 +40,10 @@ define i32 @indirect_call(ptr %0) {
define void @indirect_tail(ptr %0) {
; CHECK-LABEL: name: indirect_tail
- ; CHECK: PseudoTAILIndirect
- ; ZICFILP-LABEL: name: indirect_tail
- ; ZICFILP: PseudoTAILIndirectNonX7
+ ; CHECK: PseudoTAILIndirectNonX7
tail call void %0()
ret void
}
+
+!llvm.module.flags = !{!0}
+!0 = !{i32 8, !"cf-protection-branch", i32 1}
>From 683181f3a98f8e77aea709f18386f6f98f06a29a Mon Sep 17 00:00:00 2001
From: Kito Cheng <kito.cheng at sifive.com>
Date: Wed, 25 Feb 2026 18:35:22 +0800
Subject: [PATCH 2/7] !fixup Address comment
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 22 ++++++++++++-------
.../RISCV/RISCVIndirectBranchTracking.cpp | 1 -
.../lib/Target/RISCV/RISCVLandingPadSetup.cpp | 1 -
.../Target/RISCV/RISCVMachineFunctionInfo.cpp | 4 +++-
.../RISCV/branch-relaxation-rv32-cf-branch.ll | 3 ++-
.../RISCV/branch-relaxation-rv64-cf-branch.ll | 3 ++-
llvm/test/CodeGen/RISCV/calls-cf-branch.ll | 5 +++--
llvm/test/CodeGen/RISCV/tail-cf-branch.ll | 4 ++++
8 files changed, 28 insertions(+), 15 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 1e738142ab6c0..c12bf9e3deb03 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -24372,14 +24372,23 @@ SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI,
bool NeedSWGuarded = getTargetMachine().getCodeModel() == CodeModel::Large &&
HasCFBranch &&
(!IsIndirectCall || CalleeIsLargeExternalSymbol);
- bool NeedNonX7 = HasCFBranch && IsIndirectCall && !NeedSWGuarded;
+ bool NeedNonX7 = HasCFBranch && IsIndirectCall;
+
+ unsigned TailOpc, CallOpc;
+ if (NeedSWGuarded) {
+ TailOpc = RISCVISD::SW_GUARDED_TAIL;
+ CallOpc = RISCVISD::SW_GUARDED_CALL;
+ } else if (NeedNonX7) {
+ TailOpc = RISCVISD::TAIL_NONX7;
+ CallOpc = RISCVISD::CALL_NONX7;
+ } else {
+ TailOpc = RISCVISD::TAIL;
+ CallOpc = RISCVISD::CALL;
+ }
if (IsTailCall) {
MF.getFrameInfo().setHasTailCall();
- unsigned CallOpc = NeedSWGuarded ? RISCVISD::SW_GUARDED_TAIL
- : NeedNonX7 ? RISCVISD::TAIL_NONX7
- : RISCVISD::TAIL;
- SDValue Ret = DAG.getNode(CallOpc, DL, NodeTys, Ops);
+ SDValue Ret = DAG.getNode(TailOpc, DL, NodeTys, Ops);
if (CLI.CFIType)
Ret.getNode()->setCFIType(CLI.CFIType->getZExtValue());
DAG.addNoMergeSiteInfo(Ret.getNode(), CLI.NoMerge);
@@ -24387,9 +24396,6 @@ SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI,
return Ret;
}
- unsigned CallOpc = NeedSWGuarded ? RISCVISD::SW_GUARDED_CALL
- : NeedNonX7 ? RISCVISD::CALL_NONX7
- : RISCVISD::CALL;
Chain = DAG.getNode(CallOpc, DL, NodeTys, Ops);
if (CLI.CFIType)
Chain.getNode()->setCFIType(CLI.CFIType->getZExtValue());
diff --git a/llvm/lib/Target/RISCV/RISCVIndirectBranchTracking.cpp b/llvm/lib/Target/RISCV/RISCVIndirectBranchTracking.cpp
index 7531a748d613f..bbe8aab27bcbe 100644
--- a/llvm/lib/Target/RISCV/RISCVIndirectBranchTracking.cpp
+++ b/llvm/lib/Target/RISCV/RISCVIndirectBranchTracking.cpp
@@ -21,7 +21,6 @@
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
-#include "llvm/IR/Module.h"
#define DEBUG_TYPE "riscv-indirect-branch-tracking"
#define PASS_NAME "RISC-V Indirect Branch Tracking"
diff --git a/llvm/lib/Target/RISCV/RISCVLandingPadSetup.cpp b/llvm/lib/Target/RISCV/RISCVLandingPadSetup.cpp
index 5cc5dadb9ad89..089ffb4edaf39 100644
--- a/llvm/lib/Target/RISCV/RISCVLandingPadSetup.cpp
+++ b/llvm/lib/Target/RISCV/RISCVLandingPadSetup.cpp
@@ -17,7 +17,6 @@
#include "RISCVSubtarget.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
-#include "llvm/IR/Module.h"
using namespace llvm;
diff --git a/llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.cpp b/llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.cpp
index 333fdb7ec972c..4944df1e731a8 100644
--- a/llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.cpp
@@ -29,7 +29,9 @@ MachineFunctionInfo *RISCVMachineFunctionInfo::clone(
RISCVMachineFunctionInfo::RISCVMachineFunctionInfo(const Function &F,
const RISCVSubtarget *STI) {
- CFProtectionBranch = F.getParent()->getModuleFlag("cf-protection-branch");
+ if (const auto *CFB = mdconst::extract_or_null<ConstantInt>(
+ F.getParent()->getModuleFlag("cf-protection-branch")))
+ CFProtectionBranch = CFB->getZExtValue() != 0;
// The default stack probe size is 4096 if the function has no
// stack-probe-size attribute. This is a safe default because it is the
diff --git a/llvm/test/CodeGen/RISCV/branch-relaxation-rv32-cf-branch.ll b/llvm/test/CodeGen/RISCV/branch-relaxation-rv32-cf-branch.ll
index c7f744d33cb3c..d6cfb2c58f1a7 100644
--- a/llvm/test/CodeGen/RISCV/branch-relaxation-rv32-cf-branch.ll
+++ b/llvm/test/CodeGen/RISCV/branch-relaxation-rv32-cf-branch.ll
@@ -4,7 +4,8 @@
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s
-; Test branch relaxation with cf-protection-branch enabled.
+; This file contains tests similar to branch-relaxation-rv32.ll but with
+; cf-protection-branch module flag enabled.
; Software-guarded branches should use t2 (x7) for the target address.
define void @relax_bcc(i1 %a) nounwind {
diff --git a/llvm/test/CodeGen/RISCV/branch-relaxation-rv64-cf-branch.ll b/llvm/test/CodeGen/RISCV/branch-relaxation-rv64-cf-branch.ll
index e868731e571e7..f3d87b69aa2a8 100644
--- a/llvm/test/CodeGen/RISCV/branch-relaxation-rv64-cf-branch.ll
+++ b/llvm/test/CodeGen/RISCV/branch-relaxation-rv64-cf-branch.ll
@@ -4,7 +4,8 @@
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck %s
-; Test branch relaxation with cf-protection-branch enabled.
+; This file contains tests similar to branch-relaxation-rv64.ll but with
+; cf-protection-branch module flag enabled.
; Software-guarded branches should use t2 (x7) for the target address.
define void @relax_bcc(i1 %a) nounwind {
diff --git a/llvm/test/CodeGen/RISCV/calls-cf-branch.ll b/llvm/test/CodeGen/RISCV/calls-cf-branch.ll
index 90d7460f54849..8f574d246fed2 100644
--- a/llvm/test/CodeGen/RISCV/calls-cf-branch.ll
+++ b/llvm/test/CodeGen/RISCV/calls-cf-branch.ll
@@ -6,8 +6,9 @@
; RUN: llc -code-model=large -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I-LARGE %s
-; Test call generation with cf-protection-branch enabled.
-; This tests landing pad generation and NonX7 variants for indirect calls.
+; This file contains tests similar to calls.ll but with cf-protection-branch
+; module flag enabled. It tests landing pad generation and NonX7 variants for
+; indirect calls.
declare i32 @external_function(i32)
diff --git a/llvm/test/CodeGen/RISCV/tail-cf-branch.ll b/llvm/test/CodeGen/RISCV/tail-cf-branch.ll
index 7b0fc9b6f5992..9e87493f97cdd 100644
--- a/llvm/test/CodeGen/RISCV/tail-cf-branch.ll
+++ b/llvm/test/CodeGen/RISCV/tail-cf-branch.ll
@@ -8,6 +8,10 @@
; RUN: llc -code-model=large -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I-LARGE %s
+; This file contains tests similar to tail-calls.ll but with cf-protection-branch
+; module flag enabled. It tests landing pad generation and NonX7 variants for
+; indirect tail calls.
+
; Test tail call generation with cf-protection-branch enabled.
; This tests landing pad generation and NonX7 variants for indirect tail calls.
>From a0778b7859da2b4100a03dd4259f51191a90410e Mon Sep 17 00:00:00 2001
From: Kito Cheng <kito.cheng at sifive.com>
Date: Thu, 26 Feb 2026 00:13:42 +0800
Subject: [PATCH 3/7] !fixup Merge cf-branch test files into their original
counterparts.
Use sed in RUN lines to inject cf-protection-branch module flags at
runtime, eliminating the need for separate cf-branch test files that
duplicate IR functions.
- branch-relaxation-rv{32,64}-cf-branch.ll merged into
branch-relaxation-rv{32,64}.ll
- tail-cf-branch.ll merged into tail-calls.ll
---
.../RISCV/branch-relaxation-rv32-cf-branch.ll | 96 -
.../CodeGen/RISCV/branch-relaxation-rv32.ll | 1565 +++++++++--------
.../RISCV/branch-relaxation-rv64-cf-branch.ll | 96 -
.../CodeGen/RISCV/branch-relaxation-rv64.ll | 1565 +++++++++--------
llvm/test/CodeGen/RISCV/tail-calls.ll | 1189 ++++++++++---
llvm/test/CodeGen/RISCV/tail-cf-branch.ll | 240 ---
6 files changed, 2522 insertions(+), 2229 deletions(-)
delete mode 100644 llvm/test/CodeGen/RISCV/branch-relaxation-rv32-cf-branch.ll
delete mode 100644 llvm/test/CodeGen/RISCV/branch-relaxation-rv64-cf-branch.ll
delete mode 100644 llvm/test/CodeGen/RISCV/tail-cf-branch.ll
diff --git a/llvm/test/CodeGen/RISCV/branch-relaxation-rv32-cf-branch.ll b/llvm/test/CodeGen/RISCV/branch-relaxation-rv32-cf-branch.ll
deleted file mode 100644
index d6cfb2c58f1a7..0000000000000
--- a/llvm/test/CodeGen/RISCV/branch-relaxation-rv32-cf-branch.ll
+++ /dev/null
@@ -1,96 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -verify-machineinstrs -filetype=obj < %s \
-; RUN: -o /dev/null 2>&1
-; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
-; RUN: | FileCheck %s
-
-; This file contains tests similar to branch-relaxation-rv32.ll but with
-; cf-protection-branch module flag enabled.
-; Software-guarded branches should use t2 (x7) for the target address.
-
-define void @relax_bcc(i1 %a) nounwind {
-; CHECK-LABEL: relax_bcc:
-; CHECK: # %bb.0:
-; CHECK-NEXT: lpad 0
-; CHECK-NEXT: andi a0, a0, 1
-; CHECK-NEXT: bnez a0, .LBB0_1
-; CHECK-NEXT: j .LBB0_2
-; CHECK-NEXT: .LBB0_1: # %iftrue
-; CHECK-NEXT: #APP
-; CHECK-NEXT: .zero 4096
-; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: .LBB0_2: # %tail
-; CHECK-NEXT: ret
- br i1 %a, label %iftrue, label %tail
-
-iftrue:
- call void asm sideeffect ".space 4096", ""()
- br label %tail
-
-tail:
- ret void
-}
-
-define i32 @relax_jal(i1 %a) nounwind {
-; CHECK-LABEL: relax_jal:
-; CHECK: # %bb.0:
-; CHECK-NEXT: lpad 0
-; CHECK-NEXT: andi a0, a0, 1
-; CHECK-NEXT: bnez a0, .LBB1_1
-; CHECK-NEXT: # %bb.3:
-; CHECK-NEXT: jump .LBB1_2, t2
-; CHECK-NEXT: .LBB1_1: # %iftrue
-; CHECK-NEXT: addi sp, sp, -64
-; CHECK-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
-; CHECK-NEXT: sw s0, 56(sp) # 4-byte Folded Spill
-; CHECK-NEXT: sw s1, 52(sp) # 4-byte Folded Spill
-; CHECK-NEXT: sw s2, 48(sp) # 4-byte Folded Spill
-; CHECK-NEXT: sw s3, 44(sp) # 4-byte Folded Spill
-; CHECK-NEXT: sw s4, 40(sp) # 4-byte Folded Spill
-; CHECK-NEXT: sw s5, 36(sp) # 4-byte Folded Spill
-; CHECK-NEXT: sw s6, 32(sp) # 4-byte Folded Spill
-; CHECK-NEXT: sw s7, 28(sp) # 4-byte Folded Spill
-; CHECK-NEXT: sw s8, 24(sp) # 4-byte Folded Spill
-; CHECK-NEXT: sw s9, 20(sp) # 4-byte Folded Spill
-; CHECK-NEXT: sw s10, 16(sp) # 4-byte Folded Spill
-; CHECK-NEXT: sw s11, 12(sp) # 4-byte Folded Spill
-; CHECK-NEXT: #APP
-; CHECK-NEXT: # clobber lots of registers
-; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: #APP
-; CHECK-NEXT: .zero 1048576
-; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: li a0, 1
-; CHECK-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
-; CHECK-NEXT: lw s0, 56(sp) # 4-byte Folded Reload
-; CHECK-NEXT: lw s1, 52(sp) # 4-byte Folded Reload
-; CHECK-NEXT: lw s2, 48(sp) # 4-byte Folded Reload
-; CHECK-NEXT: lw s3, 44(sp) # 4-byte Folded Reload
-; CHECK-NEXT: lw s4, 40(sp) # 4-byte Folded Reload
-; CHECK-NEXT: lw s5, 36(sp) # 4-byte Folded Reload
-; CHECK-NEXT: lw s6, 32(sp) # 4-byte Folded Reload
-; CHECK-NEXT: lw s7, 28(sp) # 4-byte Folded Reload
-; CHECK-NEXT: lw s8, 24(sp) # 4-byte Folded Reload
-; CHECK-NEXT: lw s9, 20(sp) # 4-byte Folded Reload
-; CHECK-NEXT: lw s10, 16(sp) # 4-byte Folded Reload
-; CHECK-NEXT: lw s11, 12(sp) # 4-byte Folded Reload
-; CHECK-NEXT: addi sp, sp, 64
-; CHECK-NEXT: .LBB1_2: # %tail
-; CHECK-NEXT: ret
- br i1 %a, label %iftrue, label %iffalse
-
-iftrue:
- call void asm sideeffect "# clobber lots of registers", "~{x1},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x16},~{x17},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{x29},~{x30},~{x31}"()
- call void asm sideeffect ".space 1048576", ""()
- br label %tail
-
-iffalse:
- br label %tail
-
-tail:
- %val = phi i32 [1, %iftrue], [0, %iffalse]
- ret i32 %val
-}
-
-!llvm.module.flags = !{!0}
-!0 = !{i32 8, !"cf-protection-branch", i32 1}
diff --git a/llvm/test/CodeGen/RISCV/branch-relaxation-rv32.ll b/llvm/test/CodeGen/RISCV/branch-relaxation-rv32.ll
index 8a73549380424..bb07b9310935a 100644
--- a/llvm/test/CodeGen/RISCV/branch-relaxation-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/branch-relaxation-rv32.ll
@@ -7,8 +7,9 @@
; RUN: | FileCheck %s
; RUN: llc -mtriple=riscv32 -relocation-model=pic -verify-machineinstrs < %s \
; RUN: | FileCheck %s
-; RUN: llc -mtriple=riscv32 -verify-machineinstrs -mattr=+experimental-zicfilp < %s \
-; RUN: | FileCheck %s --check-prefixes=CHECK-ZICFILP
+; RUN: sed 's/^;CFBRANCH: //' %s \
+; RUN: | llc -mtriple=riscv32 -verify-machineinstrs \
+; RUN: | FileCheck %s --check-prefix=CHECK-CF
define void @relax_bcc(i1 %a) nounwind {
; CHECK-LABEL: relax_bcc:
@@ -23,17 +24,18 @@ define void @relax_bcc(i1 %a) nounwind {
; CHECK-NEXT: .LBB0_2: # %tail
; CHECK-NEXT: ret
;
-; CHECK-ZICFILP-LABEL: relax_bcc:
-; CHECK-ZICFILP: # %bb.0:
-; CHECK-ZICFILP-NEXT: andi a0, a0, 1
-; CHECK-ZICFILP-NEXT: bnez a0, .LBB0_1
-; CHECK-ZICFILP-NEXT: j .LBB0_2
-; CHECK-ZICFILP-NEXT: .LBB0_1: # %iftrue
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: .zero 4096
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: .LBB0_2: # %tail
-; CHECK-ZICFILP-NEXT: ret
+; CHECK-CF-LABEL: relax_bcc:
+; CHECK-CF: # %bb.0:
+; CHECK-CF-NEXT: lpad 0
+; CHECK-CF-NEXT: andi a0, a0, 1
+; CHECK-CF-NEXT: bnez a0, .LBB0_1
+; CHECK-CF-NEXT: j .LBB0_2
+; CHECK-CF-NEXT: .LBB0_1: # %iftrue
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: .zero 4096
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: .LBB0_2: # %tail
+; CHECK-CF-NEXT: ret
br i1 %a, label %iftrue, label %tail
iftrue:
@@ -67,27 +69,28 @@ define i32 @relax_jal(i1 %a) nounwind {
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
;
-; CHECK-ZICFILP-LABEL: relax_jal:
-; CHECK-ZICFILP: # %bb.0:
-; CHECK-ZICFILP-NEXT: addi sp, sp, -16
-; CHECK-ZICFILP-NEXT: andi a0, a0, 1
-; CHECK-ZICFILP-NEXT: bnez a0, .LBB1_1
-; CHECK-ZICFILP-NEXT: # %bb.4:
-; CHECK-ZICFILP-NEXT: jump .LBB1_2, a0
-; CHECK-ZICFILP-NEXT: .LBB1_1: # %iftrue
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: .zero 1048576
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: j .LBB1_3
-; CHECK-ZICFILP-NEXT: .LBB1_2: # %jmp
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: .LBB1_3: # %tail
-; CHECK-ZICFILP-NEXT: li a0, 1
-; CHECK-ZICFILP-NEXT: addi sp, sp, 16
-; CHECK-ZICFILP-NEXT: ret
+; CHECK-CF-LABEL: relax_jal:
+; CHECK-CF: # %bb.0:
+; CHECK-CF-NEXT: lpad 0
+; CHECK-CF-NEXT: addi sp, sp, -16
+; CHECK-CF-NEXT: andi a0, a0, 1
+; CHECK-CF-NEXT: bnez a0, .LBB1_1
+; CHECK-CF-NEXT: # %bb.4:
+; CHECK-CF-NEXT: jump .LBB1_2, t2
+; CHECK-CF-NEXT: .LBB1_1: # %iftrue
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: .zero 1048576
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: j .LBB1_3
+; CHECK-CF-NEXT: .LBB1_2: # %jmp
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: .LBB1_3: # %tail
+; CHECK-CF-NEXT: li a0, 1
+; CHECK-CF-NEXT: addi sp, sp, 16
+; CHECK-CF-NEXT: ret
br i1 %a, label %iftrue, label %jmp
jmp:
@@ -347,245 +350,246 @@ define void @relax_jal_spill_32() {
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: ret
;
-; CHECK-ZICFILP-LABEL: relax_jal_spill_32:
-; CHECK-ZICFILP: # %bb.0:
-; CHECK-ZICFILP-NEXT: addi sp, sp, -64
-; CHECK-ZICFILP-NEXT: .cfi_def_cfa_offset 64
-; CHECK-ZICFILP-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sw s0, 56(sp) # 4-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sw s1, 52(sp) # 4-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sw s2, 48(sp) # 4-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sw s3, 44(sp) # 4-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sw s4, 40(sp) # 4-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sw s5, 36(sp) # 4-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sw s6, 32(sp) # 4-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sw s7, 28(sp) # 4-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sw s8, 24(sp) # 4-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sw s9, 20(sp) # 4-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sw s10, 16(sp) # 4-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sw s11, 12(sp) # 4-byte Folded Spill
-; CHECK-ZICFILP-NEXT: .cfi_offset ra, -4
-; CHECK-ZICFILP-NEXT: .cfi_offset s0, -8
-; CHECK-ZICFILP-NEXT: .cfi_offset s1, -12
-; CHECK-ZICFILP-NEXT: .cfi_offset s2, -16
-; CHECK-ZICFILP-NEXT: .cfi_offset s3, -20
-; CHECK-ZICFILP-NEXT: .cfi_offset s4, -24
-; CHECK-ZICFILP-NEXT: .cfi_offset s5, -28
-; CHECK-ZICFILP-NEXT: .cfi_offset s6, -32
-; CHECK-ZICFILP-NEXT: .cfi_offset s7, -36
-; CHECK-ZICFILP-NEXT: .cfi_offset s8, -40
-; CHECK-ZICFILP-NEXT: .cfi_offset s9, -44
-; CHECK-ZICFILP-NEXT: .cfi_offset s10, -48
-; CHECK-ZICFILP-NEXT: .cfi_offset s11, -52
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li ra, 1
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li t0, 5
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li t1, 6
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li t2, 7
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s0, 8
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s1, 9
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li a0, 10
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li a1, 11
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li a2, 12
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li a3, 13
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li a4, 14
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li a5, 15
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li a6, 16
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li a7, 17
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s2, 18
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s3, 19
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s4, 20
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s5, 21
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s6, 22
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s7, 23
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s8, 24
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s9, 25
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s10, 26
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s11, 27
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li t3, 28
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li t4, 29
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li t5, 30
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li t6, 31
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: beq t5, t6, .LBB2_1
-; CHECK-ZICFILP-NEXT: # %bb.3:
-; CHECK-ZICFILP-NEXT: sw s11, 0(sp) # 4-byte Folded Spill
-; CHECK-ZICFILP-NEXT: jump .LBB2_4, s11
-; CHECK-ZICFILP-NEXT: .LBB2_1: # %branch_1
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: .zero 1048576
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: j .LBB2_2
-; CHECK-ZICFILP-NEXT: .LBB2_4: # %branch_2
-; CHECK-ZICFILP-NEXT: lw s11, 0(sp) # 4-byte Folded Reload
-; CHECK-ZICFILP-NEXT: .LBB2_2: # %branch_2
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use ra
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use t0
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use t1
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use t2
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s0
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s1
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use a0
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use a1
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use a2
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use a3
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use a4
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use a5
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use a6
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use a7
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s2
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s3
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s4
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s5
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s6
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s7
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s8
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s9
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s10
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s11
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use t3
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use t4
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use t5
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use t6
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
-; CHECK-ZICFILP-NEXT: lw s0, 56(sp) # 4-byte Folded Reload
-; CHECK-ZICFILP-NEXT: lw s1, 52(sp) # 4-byte Folded Reload
-; CHECK-ZICFILP-NEXT: lw s2, 48(sp) # 4-byte Folded Reload
-; CHECK-ZICFILP-NEXT: lw s3, 44(sp) # 4-byte Folded Reload
-; CHECK-ZICFILP-NEXT: lw s4, 40(sp) # 4-byte Folded Reload
-; CHECK-ZICFILP-NEXT: lw s5, 36(sp) # 4-byte Folded Reload
-; CHECK-ZICFILP-NEXT: lw s6, 32(sp) # 4-byte Folded Reload
-; CHECK-ZICFILP-NEXT: lw s7, 28(sp) # 4-byte Folded Reload
-; CHECK-ZICFILP-NEXT: lw s8, 24(sp) # 4-byte Folded Reload
-; CHECK-ZICFILP-NEXT: lw s9, 20(sp) # 4-byte Folded Reload
-; CHECK-ZICFILP-NEXT: lw s10, 16(sp) # 4-byte Folded Reload
-; CHECK-ZICFILP-NEXT: lw s11, 12(sp) # 4-byte Folded Reload
-; CHECK-ZICFILP-NEXT: .cfi_restore ra
-; CHECK-ZICFILP-NEXT: .cfi_restore s0
-; CHECK-ZICFILP-NEXT: .cfi_restore s1
-; CHECK-ZICFILP-NEXT: .cfi_restore s2
-; CHECK-ZICFILP-NEXT: .cfi_restore s3
-; CHECK-ZICFILP-NEXT: .cfi_restore s4
-; CHECK-ZICFILP-NEXT: .cfi_restore s5
-; CHECK-ZICFILP-NEXT: .cfi_restore s6
-; CHECK-ZICFILP-NEXT: .cfi_restore s7
-; CHECK-ZICFILP-NEXT: .cfi_restore s8
-; CHECK-ZICFILP-NEXT: .cfi_restore s9
-; CHECK-ZICFILP-NEXT: .cfi_restore s10
-; CHECK-ZICFILP-NEXT: .cfi_restore s11
-; CHECK-ZICFILP-NEXT: addi sp, sp, 64
-; CHECK-ZICFILP-NEXT: .cfi_def_cfa_offset 0
-; CHECK-ZICFILP-NEXT: ret
+; CHECK-CF-LABEL: relax_jal_spill_32:
+; CHECK-CF: # %bb.0:
+; CHECK-CF-NEXT: lpad 0
+; CHECK-CF-NEXT: addi sp, sp, -64
+; CHECK-CF-NEXT: .cfi_def_cfa_offset 64
+; CHECK-CF-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
+; CHECK-CF-NEXT: sw s0, 56(sp) # 4-byte Folded Spill
+; CHECK-CF-NEXT: sw s1, 52(sp) # 4-byte Folded Spill
+; CHECK-CF-NEXT: sw s2, 48(sp) # 4-byte Folded Spill
+; CHECK-CF-NEXT: sw s3, 44(sp) # 4-byte Folded Spill
+; CHECK-CF-NEXT: sw s4, 40(sp) # 4-byte Folded Spill
+; CHECK-CF-NEXT: sw s5, 36(sp) # 4-byte Folded Spill
+; CHECK-CF-NEXT: sw s6, 32(sp) # 4-byte Folded Spill
+; CHECK-CF-NEXT: sw s7, 28(sp) # 4-byte Folded Spill
+; CHECK-CF-NEXT: sw s8, 24(sp) # 4-byte Folded Spill
+; CHECK-CF-NEXT: sw s9, 20(sp) # 4-byte Folded Spill
+; CHECK-CF-NEXT: sw s10, 16(sp) # 4-byte Folded Spill
+; CHECK-CF-NEXT: sw s11, 12(sp) # 4-byte Folded Spill
+; CHECK-CF-NEXT: .cfi_offset ra, -4
+; CHECK-CF-NEXT: .cfi_offset s0, -8
+; CHECK-CF-NEXT: .cfi_offset s1, -12
+; CHECK-CF-NEXT: .cfi_offset s2, -16
+; CHECK-CF-NEXT: .cfi_offset s3, -20
+; CHECK-CF-NEXT: .cfi_offset s4, -24
+; CHECK-CF-NEXT: .cfi_offset s5, -28
+; CHECK-CF-NEXT: .cfi_offset s6, -32
+; CHECK-CF-NEXT: .cfi_offset s7, -36
+; CHECK-CF-NEXT: .cfi_offset s8, -40
+; CHECK-CF-NEXT: .cfi_offset s9, -44
+; CHECK-CF-NEXT: .cfi_offset s10, -48
+; CHECK-CF-NEXT: .cfi_offset s11, -52
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li ra, 1
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li t0, 5
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li t1, 6
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li t2, 7
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s0, 8
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s1, 9
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li a0, 10
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li a1, 11
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li a2, 12
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li a3, 13
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li a4, 14
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li a5, 15
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li a6, 16
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li a7, 17
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s2, 18
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s3, 19
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s4, 20
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s5, 21
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s6, 22
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s7, 23
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s8, 24
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s9, 25
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s10, 26
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s11, 27
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li t3, 28
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li t4, 29
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li t5, 30
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li t6, 31
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: beq t5, t6, .LBB2_1
+; CHECK-CF-NEXT: # %bb.3:
+; CHECK-CF-NEXT: sw t2, 0(sp) # 4-byte Folded Spill
+; CHECK-CF-NEXT: jump .LBB2_4, t2
+; CHECK-CF-NEXT: .LBB2_1: # %branch_1
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: .zero 1048576
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: j .LBB2_2
+; CHECK-CF-NEXT: .LBB2_4: # %branch_2
+; CHECK-CF-NEXT: lw t2, 0(sp) # 4-byte Folded Reload
+; CHECK-CF-NEXT: .LBB2_2: # %branch_2
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use ra
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use t0
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use t1
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use t2
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s0
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s1
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use a0
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use a1
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use a2
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use a3
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use a4
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use a5
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use a6
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use a7
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s2
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s3
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s4
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s5
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s6
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s7
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s8
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s9
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s10
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s11
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use t3
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use t4
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use t5
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use t6
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
+; CHECK-CF-NEXT: lw s0, 56(sp) # 4-byte Folded Reload
+; CHECK-CF-NEXT: lw s1, 52(sp) # 4-byte Folded Reload
+; CHECK-CF-NEXT: lw s2, 48(sp) # 4-byte Folded Reload
+; CHECK-CF-NEXT: lw s3, 44(sp) # 4-byte Folded Reload
+; CHECK-CF-NEXT: lw s4, 40(sp) # 4-byte Folded Reload
+; CHECK-CF-NEXT: lw s5, 36(sp) # 4-byte Folded Reload
+; CHECK-CF-NEXT: lw s6, 32(sp) # 4-byte Folded Reload
+; CHECK-CF-NEXT: lw s7, 28(sp) # 4-byte Folded Reload
+; CHECK-CF-NEXT: lw s8, 24(sp) # 4-byte Folded Reload
+; CHECK-CF-NEXT: lw s9, 20(sp) # 4-byte Folded Reload
+; CHECK-CF-NEXT: lw s10, 16(sp) # 4-byte Folded Reload
+; CHECK-CF-NEXT: lw s11, 12(sp) # 4-byte Folded Reload
+; CHECK-CF-NEXT: .cfi_restore ra
+; CHECK-CF-NEXT: .cfi_restore s0
+; CHECK-CF-NEXT: .cfi_restore s1
+; CHECK-CF-NEXT: .cfi_restore s2
+; CHECK-CF-NEXT: .cfi_restore s3
+; CHECK-CF-NEXT: .cfi_restore s4
+; CHECK-CF-NEXT: .cfi_restore s5
+; CHECK-CF-NEXT: .cfi_restore s6
+; CHECK-CF-NEXT: .cfi_restore s7
+; CHECK-CF-NEXT: .cfi_restore s8
+; CHECK-CF-NEXT: .cfi_restore s9
+; CHECK-CF-NEXT: .cfi_restore s10
+; CHECK-CF-NEXT: .cfi_restore s11
+; CHECK-CF-NEXT: addi sp, sp, 64
+; CHECK-CF-NEXT: .cfi_def_cfa_offset 0
+; CHECK-CF-NEXT: ret
%ra = call i32 asm sideeffect "addi ra, x0, 1", "={ra}"()
%t0 = call i32 asm sideeffect "addi t0, x0, 5", "={t0}"()
%t1 = call i32 asm sideeffect "addi t1, x0, 6", "={t1}"()
@@ -908,254 +912,255 @@ define void @relax_jal_spill_32_adjust_spill_slot() {
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: ret
;
-; CHECK-ZICFILP-LABEL: relax_jal_spill_32_adjust_spill_slot:
-; CHECK-ZICFILP: # %bb.0:
-; CHECK-ZICFILP-NEXT: addi sp, sp, -2032
-; CHECK-ZICFILP-NEXT: .cfi_def_cfa_offset 2032
-; CHECK-ZICFILP-NEXT: sw ra, 2028(sp) # 4-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sw s0, 2024(sp) # 4-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sw s1, 2020(sp) # 4-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sw s2, 2016(sp) # 4-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sw s3, 2012(sp) # 4-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sw s4, 2008(sp) # 4-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sw s5, 2004(sp) # 4-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sw s6, 2000(sp) # 4-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sw s7, 1996(sp) # 4-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sw s8, 1992(sp) # 4-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sw s9, 1988(sp) # 4-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sw s10, 1984(sp) # 4-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sw s11, 1980(sp) # 4-byte Folded Spill
-; CHECK-ZICFILP-NEXT: .cfi_offset ra, -4
-; CHECK-ZICFILP-NEXT: .cfi_offset s0, -8
-; CHECK-ZICFILP-NEXT: .cfi_offset s1, -12
-; CHECK-ZICFILP-NEXT: .cfi_offset s2, -16
-; CHECK-ZICFILP-NEXT: .cfi_offset s3, -20
-; CHECK-ZICFILP-NEXT: .cfi_offset s4, -24
-; CHECK-ZICFILP-NEXT: .cfi_offset s5, -28
-; CHECK-ZICFILP-NEXT: .cfi_offset s6, -32
-; CHECK-ZICFILP-NEXT: .cfi_offset s7, -36
-; CHECK-ZICFILP-NEXT: .cfi_offset s8, -40
-; CHECK-ZICFILP-NEXT: .cfi_offset s9, -44
-; CHECK-ZICFILP-NEXT: .cfi_offset s10, -48
-; CHECK-ZICFILP-NEXT: .cfi_offset s11, -52
-; CHECK-ZICFILP-NEXT: addi s0, sp, 2032
-; CHECK-ZICFILP-NEXT: .cfi_def_cfa s0, 0
-; CHECK-ZICFILP-NEXT: lui a0, 2
-; CHECK-ZICFILP-NEXT: addi a0, a0, -2032
-; CHECK-ZICFILP-NEXT: sub sp, sp, a0
-; CHECK-ZICFILP-NEXT: srli a0, sp, 12
-; CHECK-ZICFILP-NEXT: slli sp, a0, 12
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li ra, 1
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li t0, 5
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li t1, 6
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li t2, 7
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s0, 8
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s1, 9
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li a0, 10
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li a1, 11
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li a2, 12
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li a3, 13
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li a4, 14
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li a5, 15
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li a6, 16
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li a7, 17
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s2, 18
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s3, 19
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s4, 20
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s5, 21
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s6, 22
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s7, 23
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s8, 24
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s9, 25
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s10, 26
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s11, 27
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li t3, 28
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li t4, 29
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li t5, 30
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li t6, 31
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: beq t5, t6, .LBB3_1
-; CHECK-ZICFILP-NEXT: # %bb.3:
-; CHECK-ZICFILP-NEXT: sw s11, 0(sp) # 4-byte Folded Spill
-; CHECK-ZICFILP-NEXT: jump .LBB3_4, s11
-; CHECK-ZICFILP-NEXT: .LBB3_1: # %branch_1
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: .zero 1048576
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: j .LBB3_2
-; CHECK-ZICFILP-NEXT: .LBB3_4: # %branch_2
-; CHECK-ZICFILP-NEXT: lw s11, 0(sp) # 4-byte Folded Reload
-; CHECK-ZICFILP-NEXT: .LBB3_2: # %branch_2
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use ra
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use t0
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use t1
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use t2
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s0
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s1
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use a0
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use a1
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use a2
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use a3
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use a4
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use a5
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use a6
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use a7
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s2
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s3
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s4
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s5
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s6
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s7
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s8
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s9
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s10
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s11
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use t3
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use t4
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use t5
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use t6
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: addi sp, s0, -2032
-; CHECK-ZICFILP-NEXT: .cfi_def_cfa sp, 2032
-; CHECK-ZICFILP-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload
-; CHECK-ZICFILP-NEXT: lw s0, 2024(sp) # 4-byte Folded Reload
-; CHECK-ZICFILP-NEXT: lw s1, 2020(sp) # 4-byte Folded Reload
-; CHECK-ZICFILP-NEXT: lw s2, 2016(sp) # 4-byte Folded Reload
-; CHECK-ZICFILP-NEXT: lw s3, 2012(sp) # 4-byte Folded Reload
-; CHECK-ZICFILP-NEXT: lw s4, 2008(sp) # 4-byte Folded Reload
-; CHECK-ZICFILP-NEXT: lw s5, 2004(sp) # 4-byte Folded Reload
-; CHECK-ZICFILP-NEXT: lw s6, 2000(sp) # 4-byte Folded Reload
-; CHECK-ZICFILP-NEXT: lw s7, 1996(sp) # 4-byte Folded Reload
-; CHECK-ZICFILP-NEXT: lw s8, 1992(sp) # 4-byte Folded Reload
-; CHECK-ZICFILP-NEXT: lw s9, 1988(sp) # 4-byte Folded Reload
-; CHECK-ZICFILP-NEXT: lw s10, 1984(sp) # 4-byte Folded Reload
-; CHECK-ZICFILP-NEXT: lw s11, 1980(sp) # 4-byte Folded Reload
-; CHECK-ZICFILP-NEXT: .cfi_restore ra
-; CHECK-ZICFILP-NEXT: .cfi_restore s0
-; CHECK-ZICFILP-NEXT: .cfi_restore s1
-; CHECK-ZICFILP-NEXT: .cfi_restore s2
-; CHECK-ZICFILP-NEXT: .cfi_restore s3
-; CHECK-ZICFILP-NEXT: .cfi_restore s4
-; CHECK-ZICFILP-NEXT: .cfi_restore s5
-; CHECK-ZICFILP-NEXT: .cfi_restore s6
-; CHECK-ZICFILP-NEXT: .cfi_restore s7
-; CHECK-ZICFILP-NEXT: .cfi_restore s8
-; CHECK-ZICFILP-NEXT: .cfi_restore s9
-; CHECK-ZICFILP-NEXT: .cfi_restore s10
-; CHECK-ZICFILP-NEXT: .cfi_restore s11
-; CHECK-ZICFILP-NEXT: addi sp, sp, 2032
-; CHECK-ZICFILP-NEXT: .cfi_def_cfa_offset 0
-; CHECK-ZICFILP-NEXT: ret
+; CHECK-CF-LABEL: relax_jal_spill_32_adjust_spill_slot:
+; CHECK-CF: # %bb.0:
+; CHECK-CF-NEXT: lpad 0
+; CHECK-CF-NEXT: addi sp, sp, -2032
+; CHECK-CF-NEXT: .cfi_def_cfa_offset 2032
+; CHECK-CF-NEXT: sw ra, 2028(sp) # 4-byte Folded Spill
+; CHECK-CF-NEXT: sw s0, 2024(sp) # 4-byte Folded Spill
+; CHECK-CF-NEXT: sw s1, 2020(sp) # 4-byte Folded Spill
+; CHECK-CF-NEXT: sw s2, 2016(sp) # 4-byte Folded Spill
+; CHECK-CF-NEXT: sw s3, 2012(sp) # 4-byte Folded Spill
+; CHECK-CF-NEXT: sw s4, 2008(sp) # 4-byte Folded Spill
+; CHECK-CF-NEXT: sw s5, 2004(sp) # 4-byte Folded Spill
+; CHECK-CF-NEXT: sw s6, 2000(sp) # 4-byte Folded Spill
+; CHECK-CF-NEXT: sw s7, 1996(sp) # 4-byte Folded Spill
+; CHECK-CF-NEXT: sw s8, 1992(sp) # 4-byte Folded Spill
+; CHECK-CF-NEXT: sw s9, 1988(sp) # 4-byte Folded Spill
+; CHECK-CF-NEXT: sw s10, 1984(sp) # 4-byte Folded Spill
+; CHECK-CF-NEXT: sw s11, 1980(sp) # 4-byte Folded Spill
+; CHECK-CF-NEXT: .cfi_offset ra, -4
+; CHECK-CF-NEXT: .cfi_offset s0, -8
+; CHECK-CF-NEXT: .cfi_offset s1, -12
+; CHECK-CF-NEXT: .cfi_offset s2, -16
+; CHECK-CF-NEXT: .cfi_offset s3, -20
+; CHECK-CF-NEXT: .cfi_offset s4, -24
+; CHECK-CF-NEXT: .cfi_offset s5, -28
+; CHECK-CF-NEXT: .cfi_offset s6, -32
+; CHECK-CF-NEXT: .cfi_offset s7, -36
+; CHECK-CF-NEXT: .cfi_offset s8, -40
+; CHECK-CF-NEXT: .cfi_offset s9, -44
+; CHECK-CF-NEXT: .cfi_offset s10, -48
+; CHECK-CF-NEXT: .cfi_offset s11, -52
+; CHECK-CF-NEXT: addi s0, sp, 2032
+; CHECK-CF-NEXT: .cfi_def_cfa s0, 0
+; CHECK-CF-NEXT: lui a0, 2
+; CHECK-CF-NEXT: addi a0, a0, -2032
+; CHECK-CF-NEXT: sub sp, sp, a0
+; CHECK-CF-NEXT: srli a0, sp, 12
+; CHECK-CF-NEXT: slli sp, a0, 12
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li ra, 1
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li t0, 5
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li t1, 6
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li t2, 7
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s0, 8
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s1, 9
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li a0, 10
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li a1, 11
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li a2, 12
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li a3, 13
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li a4, 14
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li a5, 15
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li a6, 16
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li a7, 17
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s2, 18
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s3, 19
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s4, 20
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s5, 21
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s6, 22
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s7, 23
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s8, 24
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s9, 25
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s10, 26
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s11, 27
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li t3, 28
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li t4, 29
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li t5, 30
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li t6, 31
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: beq t5, t6, .LBB3_1
+; CHECK-CF-NEXT: # %bb.3:
+; CHECK-CF-NEXT: sw t2, 0(sp) # 4-byte Folded Spill
+; CHECK-CF-NEXT: jump .LBB3_4, t2
+; CHECK-CF-NEXT: .LBB3_1: # %branch_1
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: .zero 1048576
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: j .LBB3_2
+; CHECK-CF-NEXT: .LBB3_4: # %branch_2
+; CHECK-CF-NEXT: lw t2, 0(sp) # 4-byte Folded Reload
+; CHECK-CF-NEXT: .LBB3_2: # %branch_2
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use ra
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use t0
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use t1
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use t2
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s0
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s1
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use a0
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use a1
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use a2
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use a3
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use a4
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use a5
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use a6
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use a7
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s2
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s3
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s4
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s5
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s6
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s7
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s8
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s9
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s10
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s11
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use t3
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use t4
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use t5
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use t6
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: addi sp, s0, -2032
+; CHECK-CF-NEXT: .cfi_def_cfa sp, 2032
+; CHECK-CF-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload
+; CHECK-CF-NEXT: lw s0, 2024(sp) # 4-byte Folded Reload
+; CHECK-CF-NEXT: lw s1, 2020(sp) # 4-byte Folded Reload
+; CHECK-CF-NEXT: lw s2, 2016(sp) # 4-byte Folded Reload
+; CHECK-CF-NEXT: lw s3, 2012(sp) # 4-byte Folded Reload
+; CHECK-CF-NEXT: lw s4, 2008(sp) # 4-byte Folded Reload
+; CHECK-CF-NEXT: lw s5, 2004(sp) # 4-byte Folded Reload
+; CHECK-CF-NEXT: lw s6, 2000(sp) # 4-byte Folded Reload
+; CHECK-CF-NEXT: lw s7, 1996(sp) # 4-byte Folded Reload
+; CHECK-CF-NEXT: lw s8, 1992(sp) # 4-byte Folded Reload
+; CHECK-CF-NEXT: lw s9, 1988(sp) # 4-byte Folded Reload
+; CHECK-CF-NEXT: lw s10, 1984(sp) # 4-byte Folded Reload
+; CHECK-CF-NEXT: lw s11, 1980(sp) # 4-byte Folded Reload
+; CHECK-CF-NEXT: .cfi_restore ra
+; CHECK-CF-NEXT: .cfi_restore s0
+; CHECK-CF-NEXT: .cfi_restore s1
+; CHECK-CF-NEXT: .cfi_restore s2
+; CHECK-CF-NEXT: .cfi_restore s3
+; CHECK-CF-NEXT: .cfi_restore s4
+; CHECK-CF-NEXT: .cfi_restore s5
+; CHECK-CF-NEXT: .cfi_restore s6
+; CHECK-CF-NEXT: .cfi_restore s7
+; CHECK-CF-NEXT: .cfi_restore s8
+; CHECK-CF-NEXT: .cfi_restore s9
+; CHECK-CF-NEXT: .cfi_restore s10
+; CHECK-CF-NEXT: .cfi_restore s11
+; CHECK-CF-NEXT: addi sp, sp, 2032
+; CHECK-CF-NEXT: .cfi_def_cfa_offset 0
+; CHECK-CF-NEXT: ret
%stack_obj = alloca i32, align 4096
%ra = call i32 asm sideeffect "addi ra, x0, 1", "={ra}"()
@@ -1486,263 +1491,264 @@ define void @relax_jal_spill_32_restore_block_correspondence() {
; CHECK-NEXT: sw s11, 0(sp) # 4-byte Folded Spill
; CHECK-NEXT: jump .LBB4_8, s11
;
-; CHECK-ZICFILP-LABEL: relax_jal_spill_32_restore_block_correspondence:
-; CHECK-ZICFILP: # %bb.0: # %entry
-; CHECK-ZICFILP-NEXT: addi sp, sp, -64
-; CHECK-ZICFILP-NEXT: .cfi_def_cfa_offset 64
-; CHECK-ZICFILP-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sw s0, 56(sp) # 4-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sw s1, 52(sp) # 4-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sw s2, 48(sp) # 4-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sw s3, 44(sp) # 4-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sw s4, 40(sp) # 4-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sw s5, 36(sp) # 4-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sw s6, 32(sp) # 4-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sw s7, 28(sp) # 4-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sw s8, 24(sp) # 4-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sw s9, 20(sp) # 4-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sw s10, 16(sp) # 4-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sw s11, 12(sp) # 4-byte Folded Spill
-; CHECK-ZICFILP-NEXT: .cfi_offset ra, -4
-; CHECK-ZICFILP-NEXT: .cfi_offset s0, -8
-; CHECK-ZICFILP-NEXT: .cfi_offset s1, -12
-; CHECK-ZICFILP-NEXT: .cfi_offset s2, -16
-; CHECK-ZICFILP-NEXT: .cfi_offset s3, -20
-; CHECK-ZICFILP-NEXT: .cfi_offset s4, -24
-; CHECK-ZICFILP-NEXT: .cfi_offset s5, -28
-; CHECK-ZICFILP-NEXT: .cfi_offset s6, -32
-; CHECK-ZICFILP-NEXT: .cfi_offset s7, -36
-; CHECK-ZICFILP-NEXT: .cfi_offset s8, -40
-; CHECK-ZICFILP-NEXT: .cfi_offset s9, -44
-; CHECK-ZICFILP-NEXT: .cfi_offset s10, -48
-; CHECK-ZICFILP-NEXT: .cfi_offset s11, -52
-; CHECK-ZICFILP-NEXT: .cfi_remember_state
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li ra, 1
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li t0, 5
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li t1, 6
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li t2, 7
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s0, 8
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s1, 9
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li a0, 10
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li a1, 11
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li a2, 12
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li a3, 13
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li a4, 14
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li a5, 15
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li a6, 16
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li a7, 17
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s2, 18
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s3, 19
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s4, 20
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s5, 21
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s6, 22
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s7, 23
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s8, 24
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s9, 25
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s10, 26
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s11, 27
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li t3, 28
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li t4, 29
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li t5, 30
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li t6, 31
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: bne t5, t6, .LBB4_2
-; CHECK-ZICFILP-NEXT: j .LBB4_1
-; CHECK-ZICFILP-NEXT: .LBB4_8: # %dest_1
-; CHECK-ZICFILP-NEXT: lw s11, 0(sp) # 4-byte Folded Reload
-; CHECK-ZICFILP-NEXT: .LBB4_1: # %dest_1
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # dest 1
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: j .LBB4_3
-; CHECK-ZICFILP-NEXT: .LBB4_2: # %cond_2
-; CHECK-ZICFILP-NEXT: bne t3, t4, .LBB4_5
-; CHECK-ZICFILP-NEXT: .LBB4_3: # %dest_2
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # dest 2
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: .LBB4_4: # %dest_3
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # dest 3
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use ra
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use t0
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use t1
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use t2
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s0
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s1
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use a0
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use a1
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use a2
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use a3
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use a4
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use a5
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use a6
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use a7
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s2
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s3
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s4
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s5
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s6
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s7
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s8
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s9
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s10
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s11
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use t3
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use t4
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use t5
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use t6
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
-; CHECK-ZICFILP-NEXT: lw s0, 56(sp) # 4-byte Folded Reload
-; CHECK-ZICFILP-NEXT: lw s1, 52(sp) # 4-byte Folded Reload
-; CHECK-ZICFILP-NEXT: lw s2, 48(sp) # 4-byte Folded Reload
-; CHECK-ZICFILP-NEXT: lw s3, 44(sp) # 4-byte Folded Reload
-; CHECK-ZICFILP-NEXT: lw s4, 40(sp) # 4-byte Folded Reload
-; CHECK-ZICFILP-NEXT: lw s5, 36(sp) # 4-byte Folded Reload
-; CHECK-ZICFILP-NEXT: lw s6, 32(sp) # 4-byte Folded Reload
-; CHECK-ZICFILP-NEXT: lw s7, 28(sp) # 4-byte Folded Reload
-; CHECK-ZICFILP-NEXT: lw s8, 24(sp) # 4-byte Folded Reload
-; CHECK-ZICFILP-NEXT: lw s9, 20(sp) # 4-byte Folded Reload
-; CHECK-ZICFILP-NEXT: lw s10, 16(sp) # 4-byte Folded Reload
-; CHECK-ZICFILP-NEXT: lw s11, 12(sp) # 4-byte Folded Reload
-; CHECK-ZICFILP-NEXT: .cfi_restore ra
-; CHECK-ZICFILP-NEXT: .cfi_restore s0
-; CHECK-ZICFILP-NEXT: .cfi_restore s1
-; CHECK-ZICFILP-NEXT: .cfi_restore s2
-; CHECK-ZICFILP-NEXT: .cfi_restore s3
-; CHECK-ZICFILP-NEXT: .cfi_restore s4
-; CHECK-ZICFILP-NEXT: .cfi_restore s5
-; CHECK-ZICFILP-NEXT: .cfi_restore s6
-; CHECK-ZICFILP-NEXT: .cfi_restore s7
-; CHECK-ZICFILP-NEXT: .cfi_restore s8
-; CHECK-ZICFILP-NEXT: .cfi_restore s9
-; CHECK-ZICFILP-NEXT: .cfi_restore s10
-; CHECK-ZICFILP-NEXT: .cfi_restore s11
-; CHECK-ZICFILP-NEXT: addi sp, sp, 64
-; CHECK-ZICFILP-NEXT: .cfi_def_cfa_offset 0
-; CHECK-ZICFILP-NEXT: ret
-; CHECK-ZICFILP-NEXT: .LBB4_5: # %cond_3
-; CHECK-ZICFILP-NEXT: .cfi_restore_state
-; CHECK-ZICFILP-NEXT: beq t1, t2, .LBB4_4
-; CHECK-ZICFILP-NEXT: # %bb.6: # %space
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: .zero 1048576
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: # %bb.7: # %space
-; CHECK-ZICFILP-NEXT: sw s11, 0(sp) # 4-byte Folded Spill
-; CHECK-ZICFILP-NEXT: jump .LBB4_8, s11
+; CHECK-CF-LABEL: relax_jal_spill_32_restore_block_correspondence:
+; CHECK-CF: # %bb.0: # %entry
+; CHECK-CF-NEXT: lpad 0
+; CHECK-CF-NEXT: addi sp, sp, -64
+; CHECK-CF-NEXT: .cfi_def_cfa_offset 64
+; CHECK-CF-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
+; CHECK-CF-NEXT: sw s0, 56(sp) # 4-byte Folded Spill
+; CHECK-CF-NEXT: sw s1, 52(sp) # 4-byte Folded Spill
+; CHECK-CF-NEXT: sw s2, 48(sp) # 4-byte Folded Spill
+; CHECK-CF-NEXT: sw s3, 44(sp) # 4-byte Folded Spill
+; CHECK-CF-NEXT: sw s4, 40(sp) # 4-byte Folded Spill
+; CHECK-CF-NEXT: sw s5, 36(sp) # 4-byte Folded Spill
+; CHECK-CF-NEXT: sw s6, 32(sp) # 4-byte Folded Spill
+; CHECK-CF-NEXT: sw s7, 28(sp) # 4-byte Folded Spill
+; CHECK-CF-NEXT: sw s8, 24(sp) # 4-byte Folded Spill
+; CHECK-CF-NEXT: sw s9, 20(sp) # 4-byte Folded Spill
+; CHECK-CF-NEXT: sw s10, 16(sp) # 4-byte Folded Spill
+; CHECK-CF-NEXT: sw s11, 12(sp) # 4-byte Folded Spill
+; CHECK-CF-NEXT: .cfi_offset ra, -4
+; CHECK-CF-NEXT: .cfi_offset s0, -8
+; CHECK-CF-NEXT: .cfi_offset s1, -12
+; CHECK-CF-NEXT: .cfi_offset s2, -16
+; CHECK-CF-NEXT: .cfi_offset s3, -20
+; CHECK-CF-NEXT: .cfi_offset s4, -24
+; CHECK-CF-NEXT: .cfi_offset s5, -28
+; CHECK-CF-NEXT: .cfi_offset s6, -32
+; CHECK-CF-NEXT: .cfi_offset s7, -36
+; CHECK-CF-NEXT: .cfi_offset s8, -40
+; CHECK-CF-NEXT: .cfi_offset s9, -44
+; CHECK-CF-NEXT: .cfi_offset s10, -48
+; CHECK-CF-NEXT: .cfi_offset s11, -52
+; CHECK-CF-NEXT: .cfi_remember_state
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li ra, 1
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li t0, 5
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li t1, 6
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li t2, 7
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s0, 8
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s1, 9
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li a0, 10
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li a1, 11
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li a2, 12
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li a3, 13
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li a4, 14
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li a5, 15
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li a6, 16
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li a7, 17
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s2, 18
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s3, 19
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s4, 20
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s5, 21
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s6, 22
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s7, 23
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s8, 24
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s9, 25
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s10, 26
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s11, 27
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li t3, 28
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li t4, 29
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li t5, 30
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li t6, 31
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: bne t5, t6, .LBB4_2
+; CHECK-CF-NEXT: j .LBB4_1
+; CHECK-CF-NEXT: .LBB4_8: # %dest_1
+; CHECK-CF-NEXT: lw t2, 0(sp) # 4-byte Folded Reload
+; CHECK-CF-NEXT: .LBB4_1: # %dest_1
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # dest 1
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: j .LBB4_3
+; CHECK-CF-NEXT: .LBB4_2: # %cond_2
+; CHECK-CF-NEXT: bne t3, t4, .LBB4_5
+; CHECK-CF-NEXT: .LBB4_3: # %dest_2
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # dest 2
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: .LBB4_4: # %dest_3
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # dest 3
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use ra
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use t0
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use t1
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use t2
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s0
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s1
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use a0
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use a1
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use a2
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use a3
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use a4
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use a5
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use a6
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use a7
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s2
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s3
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s4
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s5
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s6
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s7
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s8
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s9
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s10
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s11
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use t3
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use t4
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use t5
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use t6
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
+; CHECK-CF-NEXT: lw s0, 56(sp) # 4-byte Folded Reload
+; CHECK-CF-NEXT: lw s1, 52(sp) # 4-byte Folded Reload
+; CHECK-CF-NEXT: lw s2, 48(sp) # 4-byte Folded Reload
+; CHECK-CF-NEXT: lw s3, 44(sp) # 4-byte Folded Reload
+; CHECK-CF-NEXT: lw s4, 40(sp) # 4-byte Folded Reload
+; CHECK-CF-NEXT: lw s5, 36(sp) # 4-byte Folded Reload
+; CHECK-CF-NEXT: lw s6, 32(sp) # 4-byte Folded Reload
+; CHECK-CF-NEXT: lw s7, 28(sp) # 4-byte Folded Reload
+; CHECK-CF-NEXT: lw s8, 24(sp) # 4-byte Folded Reload
+; CHECK-CF-NEXT: lw s9, 20(sp) # 4-byte Folded Reload
+; CHECK-CF-NEXT: lw s10, 16(sp) # 4-byte Folded Reload
+; CHECK-CF-NEXT: lw s11, 12(sp) # 4-byte Folded Reload
+; CHECK-CF-NEXT: .cfi_restore ra
+; CHECK-CF-NEXT: .cfi_restore s0
+; CHECK-CF-NEXT: .cfi_restore s1
+; CHECK-CF-NEXT: .cfi_restore s2
+; CHECK-CF-NEXT: .cfi_restore s3
+; CHECK-CF-NEXT: .cfi_restore s4
+; CHECK-CF-NEXT: .cfi_restore s5
+; CHECK-CF-NEXT: .cfi_restore s6
+; CHECK-CF-NEXT: .cfi_restore s7
+; CHECK-CF-NEXT: .cfi_restore s8
+; CHECK-CF-NEXT: .cfi_restore s9
+; CHECK-CF-NEXT: .cfi_restore s10
+; CHECK-CF-NEXT: .cfi_restore s11
+; CHECK-CF-NEXT: addi sp, sp, 64
+; CHECK-CF-NEXT: .cfi_def_cfa_offset 0
+; CHECK-CF-NEXT: ret
+; CHECK-CF-NEXT: .LBB4_5: # %cond_3
+; CHECK-CF-NEXT: .cfi_restore_state
+; CHECK-CF-NEXT: beq t1, t2, .LBB4_4
+; CHECK-CF-NEXT: # %bb.6: # %space
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: .zero 1048576
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: # %bb.7: # %space
+; CHECK-CF-NEXT: sw t2, 0(sp) # 4-byte Folded Spill
+; CHECK-CF-NEXT: jump .LBB4_8, t2
entry:
%ra = call i32 asm sideeffect "addi ra, x0, 1", "={ra}"()
%t0 = call i32 asm sideeffect "addi t0, x0, 5", "={t0}"()
@@ -1835,3 +1841,6 @@ tail:
ret void
}
+
+;CFBRANCH: !llvm.module.flags = !{!0}
+;CFBRANCH: !0 = !{i32 8, !"cf-protection-branch", i32 1}
diff --git a/llvm/test/CodeGen/RISCV/branch-relaxation-rv64-cf-branch.ll b/llvm/test/CodeGen/RISCV/branch-relaxation-rv64-cf-branch.ll
deleted file mode 100644
index f3d87b69aa2a8..0000000000000
--- a/llvm/test/CodeGen/RISCV/branch-relaxation-rv64-cf-branch.ll
+++ /dev/null
@@ -1,96 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -verify-machineinstrs -filetype=obj < %s \
-; RUN: -o /dev/null 2>&1
-; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
-; RUN: | FileCheck %s
-
-; This file contains tests similar to branch-relaxation-rv64.ll but with
-; cf-protection-branch module flag enabled.
-; Software-guarded branches should use t2 (x7) for the target address.
-
-define void @relax_bcc(i1 %a) nounwind {
-; CHECK-LABEL: relax_bcc:
-; CHECK: # %bb.0:
-; CHECK-NEXT: lpad 0
-; CHECK-NEXT: andi a0, a0, 1
-; CHECK-NEXT: bnez a0, .LBB0_1
-; CHECK-NEXT: j .LBB0_2
-; CHECK-NEXT: .LBB0_1: # %iftrue
-; CHECK-NEXT: #APP
-; CHECK-NEXT: .zero 4096
-; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: .LBB0_2: # %tail
-; CHECK-NEXT: ret
- br i1 %a, label %iftrue, label %tail
-
-iftrue:
- call void asm sideeffect ".space 4096", ""()
- br label %tail
-
-tail:
- ret void
-}
-
-define i32 @relax_jal(i1 %a) nounwind {
-; CHECK-LABEL: relax_jal:
-; CHECK: # %bb.0:
-; CHECK-NEXT: lpad 0
-; CHECK-NEXT: andi a0, a0, 1
-; CHECK-NEXT: bnez a0, .LBB1_1
-; CHECK-NEXT: # %bb.3:
-; CHECK-NEXT: jump .LBB1_2, t2
-; CHECK-NEXT: .LBB1_1: # %iftrue
-; CHECK-NEXT: addi sp, sp, -112
-; CHECK-NEXT: sd ra, 104(sp) # 8-byte Folded Spill
-; CHECK-NEXT: sd s0, 96(sp) # 8-byte Folded Spill
-; CHECK-NEXT: sd s1, 88(sp) # 8-byte Folded Spill
-; CHECK-NEXT: sd s2, 80(sp) # 8-byte Folded Spill
-; CHECK-NEXT: sd s3, 72(sp) # 8-byte Folded Spill
-; CHECK-NEXT: sd s4, 64(sp) # 8-byte Folded Spill
-; CHECK-NEXT: sd s5, 56(sp) # 8-byte Folded Spill
-; CHECK-NEXT: sd s6, 48(sp) # 8-byte Folded Spill
-; CHECK-NEXT: sd s7, 40(sp) # 8-byte Folded Spill
-; CHECK-NEXT: sd s8, 32(sp) # 8-byte Folded Spill
-; CHECK-NEXT: sd s9, 24(sp) # 8-byte Folded Spill
-; CHECK-NEXT: sd s10, 16(sp) # 8-byte Folded Spill
-; CHECK-NEXT: sd s11, 8(sp) # 8-byte Folded Spill
-; CHECK-NEXT: #APP
-; CHECK-NEXT: # clobber lots of registers
-; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: #APP
-; CHECK-NEXT: .zero 1048576
-; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: li a0, 1
-; CHECK-NEXT: ld ra, 104(sp) # 8-byte Folded Reload
-; CHECK-NEXT: ld s0, 96(sp) # 8-byte Folded Reload
-; CHECK-NEXT: ld s1, 88(sp) # 8-byte Folded Reload
-; CHECK-NEXT: ld s2, 80(sp) # 8-byte Folded Reload
-; CHECK-NEXT: ld s3, 72(sp) # 8-byte Folded Reload
-; CHECK-NEXT: ld s4, 64(sp) # 8-byte Folded Reload
-; CHECK-NEXT: ld s5, 56(sp) # 8-byte Folded Reload
-; CHECK-NEXT: ld s6, 48(sp) # 8-byte Folded Reload
-; CHECK-NEXT: ld s7, 40(sp) # 8-byte Folded Reload
-; CHECK-NEXT: ld s8, 32(sp) # 8-byte Folded Reload
-; CHECK-NEXT: ld s9, 24(sp) # 8-byte Folded Reload
-; CHECK-NEXT: ld s10, 16(sp) # 8-byte Folded Reload
-; CHECK-NEXT: ld s11, 8(sp) # 8-byte Folded Reload
-; CHECK-NEXT: addi sp, sp, 112
-; CHECK-NEXT: .LBB1_2: # %tail
-; CHECK-NEXT: ret
- br i1 %a, label %iftrue, label %iffalse
-
-iftrue:
- call void asm sideeffect "# clobber lots of registers", "~{x1},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x16},~{x17},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{x29},~{x30},~{x31}"()
- call void asm sideeffect ".space 1048576", ""()
- br label %tail
-
-iffalse:
- br label %tail
-
-tail:
- %val = phi i32 [1, %iftrue], [0, %iffalse]
- ret i32 %val
-}
-
-!llvm.module.flags = !{!0}
-!0 = !{i32 8, !"cf-protection-branch", i32 1}
diff --git a/llvm/test/CodeGen/RISCV/branch-relaxation-rv64.ll b/llvm/test/CodeGen/RISCV/branch-relaxation-rv64.ll
index c21b4fbcc12f7..ddd181496f18d 100644
--- a/llvm/test/CodeGen/RISCV/branch-relaxation-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/branch-relaxation-rv64.ll
@@ -7,8 +7,9 @@
; RUN: | FileCheck %s
; RUN: llc -mtriple=riscv64 -relocation-model=pic -verify-machineinstrs < %s \
; RUN: | FileCheck %s
-; RUN: llc -mtriple=riscv64 -verify-machineinstrs -mattr=+experimental-zicfilp < %s \
-; RUN: | FileCheck %s --check-prefixes=CHECK-ZICFILP
+; RUN: sed 's/^;CFBRANCH: //' %s \
+; RUN: | llc -mtriple=riscv64 -verify-machineinstrs \
+; RUN: | FileCheck %s --check-prefix=CHECK-CF
define void @relax_bcc(i1 %a) nounwind {
; CHECK-LABEL: relax_bcc:
@@ -23,17 +24,18 @@ define void @relax_bcc(i1 %a) nounwind {
; CHECK-NEXT: .LBB0_2: # %tail
; CHECK-NEXT: ret
;
-; CHECK-ZICFILP-LABEL: relax_bcc:
-; CHECK-ZICFILP: # %bb.0:
-; CHECK-ZICFILP-NEXT: andi a0, a0, 1
-; CHECK-ZICFILP-NEXT: bnez a0, .LBB0_1
-; CHECK-ZICFILP-NEXT: j .LBB0_2
-; CHECK-ZICFILP-NEXT: .LBB0_1: # %iftrue
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: .zero 4096
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: .LBB0_2: # %tail
-; CHECK-ZICFILP-NEXT: ret
+; CHECK-CF-LABEL: relax_bcc:
+; CHECK-CF: # %bb.0:
+; CHECK-CF-NEXT: lpad 0
+; CHECK-CF-NEXT: andi a0, a0, 1
+; CHECK-CF-NEXT: bnez a0, .LBB0_1
+; CHECK-CF-NEXT: j .LBB0_2
+; CHECK-CF-NEXT: .LBB0_1: # %iftrue
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: .zero 4096
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: .LBB0_2: # %tail
+; CHECK-CF-NEXT: ret
br i1 %a, label %iftrue, label %tail
iftrue:
@@ -67,27 +69,28 @@ define i32 @relax_jal(i1 %a) nounwind {
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
;
-; CHECK-ZICFILP-LABEL: relax_jal:
-; CHECK-ZICFILP: # %bb.0:
-; CHECK-ZICFILP-NEXT: addi sp, sp, -16
-; CHECK-ZICFILP-NEXT: andi a0, a0, 1
-; CHECK-ZICFILP-NEXT: bnez a0, .LBB1_1
-; CHECK-ZICFILP-NEXT: # %bb.4:
-; CHECK-ZICFILP-NEXT: jump .LBB1_2, a0
-; CHECK-ZICFILP-NEXT: .LBB1_1: # %iftrue
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: .zero 1048576
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: j .LBB1_3
-; CHECK-ZICFILP-NEXT: .LBB1_2: # %jmp
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: .LBB1_3: # %tail
-; CHECK-ZICFILP-NEXT: li a0, 1
-; CHECK-ZICFILP-NEXT: addi sp, sp, 16
-; CHECK-ZICFILP-NEXT: ret
+; CHECK-CF-LABEL: relax_jal:
+; CHECK-CF: # %bb.0:
+; CHECK-CF-NEXT: lpad 0
+; CHECK-CF-NEXT: addi sp, sp, -16
+; CHECK-CF-NEXT: andi a0, a0, 1
+; CHECK-CF-NEXT: bnez a0, .LBB1_1
+; CHECK-CF-NEXT: # %bb.4:
+; CHECK-CF-NEXT: jump .LBB1_2, t2
+; CHECK-CF-NEXT: .LBB1_1: # %iftrue
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: .zero 1048576
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: j .LBB1_3
+; CHECK-CF-NEXT: .LBB1_2: # %jmp
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: .LBB1_3: # %tail
+; CHECK-CF-NEXT: li a0, 1
+; CHECK-CF-NEXT: addi sp, sp, 16
+; CHECK-CF-NEXT: ret
br i1 %a, label %iftrue, label %jmp
jmp:
@@ -349,245 +352,246 @@ define void @relax_jal_spill_64() {
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: ret
;
-; CHECK-ZICFILP-LABEL: relax_jal_spill_64:
-; CHECK-ZICFILP: # %bb.0:
-; CHECK-ZICFILP-NEXT: addi sp, sp, -112
-; CHECK-ZICFILP-NEXT: .cfi_def_cfa_offset 112
-; CHECK-ZICFILP-NEXT: sd ra, 104(sp) # 8-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sd s0, 96(sp) # 8-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sd s1, 88(sp) # 8-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sd s2, 80(sp) # 8-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sd s3, 72(sp) # 8-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sd s4, 64(sp) # 8-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sd s5, 56(sp) # 8-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sd s6, 48(sp) # 8-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sd s7, 40(sp) # 8-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sd s8, 32(sp) # 8-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sd s9, 24(sp) # 8-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sd s10, 16(sp) # 8-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sd s11, 8(sp) # 8-byte Folded Spill
-; CHECK-ZICFILP-NEXT: .cfi_offset ra, -8
-; CHECK-ZICFILP-NEXT: .cfi_offset s0, -16
-; CHECK-ZICFILP-NEXT: .cfi_offset s1, -24
-; CHECK-ZICFILP-NEXT: .cfi_offset s2, -32
-; CHECK-ZICFILP-NEXT: .cfi_offset s3, -40
-; CHECK-ZICFILP-NEXT: .cfi_offset s4, -48
-; CHECK-ZICFILP-NEXT: .cfi_offset s5, -56
-; CHECK-ZICFILP-NEXT: .cfi_offset s6, -64
-; CHECK-ZICFILP-NEXT: .cfi_offset s7, -72
-; CHECK-ZICFILP-NEXT: .cfi_offset s8, -80
-; CHECK-ZICFILP-NEXT: .cfi_offset s9, -88
-; CHECK-ZICFILP-NEXT: .cfi_offset s10, -96
-; CHECK-ZICFILP-NEXT: .cfi_offset s11, -104
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li ra, 1
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li t0, 5
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li t1, 6
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li t2, 7
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s0, 8
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s1, 9
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li a0, 10
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li a1, 11
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li a2, 12
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li a3, 13
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li a4, 14
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li a5, 15
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li a6, 16
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li a7, 17
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s2, 18
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s3, 19
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s4, 20
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s5, 21
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s6, 22
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s7, 23
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s8, 24
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s9, 25
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s10, 26
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s11, 27
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li t3, 28
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li t4, 29
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li t5, 30
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li t6, 31
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: beq t5, t6, .LBB2_1
-; CHECK-ZICFILP-NEXT: # %bb.3:
-; CHECK-ZICFILP-NEXT: sd s11, 0(sp) # 8-byte Folded Spill
-; CHECK-ZICFILP-NEXT: jump .LBB2_4, s11
-; CHECK-ZICFILP-NEXT: .LBB2_1: # %branch_1
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: .zero 1048576
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: j .LBB2_2
-; CHECK-ZICFILP-NEXT: .LBB2_4: # %branch_2
-; CHECK-ZICFILP-NEXT: ld s11, 0(sp) # 8-byte Folded Reload
-; CHECK-ZICFILP-NEXT: .LBB2_2: # %branch_2
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use ra
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use t0
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use t1
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use t2
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s0
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s1
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use a0
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use a1
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use a2
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use a3
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use a4
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use a5
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use a6
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use a7
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s2
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s3
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s4
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s5
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s6
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s7
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s8
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s9
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s10
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s11
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use t3
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use t4
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use t5
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use t6
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: ld ra, 104(sp) # 8-byte Folded Reload
-; CHECK-ZICFILP-NEXT: ld s0, 96(sp) # 8-byte Folded Reload
-; CHECK-ZICFILP-NEXT: ld s1, 88(sp) # 8-byte Folded Reload
-; CHECK-ZICFILP-NEXT: ld s2, 80(sp) # 8-byte Folded Reload
-; CHECK-ZICFILP-NEXT: ld s3, 72(sp) # 8-byte Folded Reload
-; CHECK-ZICFILP-NEXT: ld s4, 64(sp) # 8-byte Folded Reload
-; CHECK-ZICFILP-NEXT: ld s5, 56(sp) # 8-byte Folded Reload
-; CHECK-ZICFILP-NEXT: ld s6, 48(sp) # 8-byte Folded Reload
-; CHECK-ZICFILP-NEXT: ld s7, 40(sp) # 8-byte Folded Reload
-; CHECK-ZICFILP-NEXT: ld s8, 32(sp) # 8-byte Folded Reload
-; CHECK-ZICFILP-NEXT: ld s9, 24(sp) # 8-byte Folded Reload
-; CHECK-ZICFILP-NEXT: ld s10, 16(sp) # 8-byte Folded Reload
-; CHECK-ZICFILP-NEXT: ld s11, 8(sp) # 8-byte Folded Reload
-; CHECK-ZICFILP-NEXT: .cfi_restore ra
-; CHECK-ZICFILP-NEXT: .cfi_restore s0
-; CHECK-ZICFILP-NEXT: .cfi_restore s1
-; CHECK-ZICFILP-NEXT: .cfi_restore s2
-; CHECK-ZICFILP-NEXT: .cfi_restore s3
-; CHECK-ZICFILP-NEXT: .cfi_restore s4
-; CHECK-ZICFILP-NEXT: .cfi_restore s5
-; CHECK-ZICFILP-NEXT: .cfi_restore s6
-; CHECK-ZICFILP-NEXT: .cfi_restore s7
-; CHECK-ZICFILP-NEXT: .cfi_restore s8
-; CHECK-ZICFILP-NEXT: .cfi_restore s9
-; CHECK-ZICFILP-NEXT: .cfi_restore s10
-; CHECK-ZICFILP-NEXT: .cfi_restore s11
-; CHECK-ZICFILP-NEXT: addi sp, sp, 112
-; CHECK-ZICFILP-NEXT: .cfi_def_cfa_offset 0
-; CHECK-ZICFILP-NEXT: ret
+; CHECK-CF-LABEL: relax_jal_spill_64:
+; CHECK-CF: # %bb.0:
+; CHECK-CF-NEXT: lpad 0
+; CHECK-CF-NEXT: addi sp, sp, -112
+; CHECK-CF-NEXT: .cfi_def_cfa_offset 112
+; CHECK-CF-NEXT: sd ra, 104(sp) # 8-byte Folded Spill
+; CHECK-CF-NEXT: sd s0, 96(sp) # 8-byte Folded Spill
+; CHECK-CF-NEXT: sd s1, 88(sp) # 8-byte Folded Spill
+; CHECK-CF-NEXT: sd s2, 80(sp) # 8-byte Folded Spill
+; CHECK-CF-NEXT: sd s3, 72(sp) # 8-byte Folded Spill
+; CHECK-CF-NEXT: sd s4, 64(sp) # 8-byte Folded Spill
+; CHECK-CF-NEXT: sd s5, 56(sp) # 8-byte Folded Spill
+; CHECK-CF-NEXT: sd s6, 48(sp) # 8-byte Folded Spill
+; CHECK-CF-NEXT: sd s7, 40(sp) # 8-byte Folded Spill
+; CHECK-CF-NEXT: sd s8, 32(sp) # 8-byte Folded Spill
+; CHECK-CF-NEXT: sd s9, 24(sp) # 8-byte Folded Spill
+; CHECK-CF-NEXT: sd s10, 16(sp) # 8-byte Folded Spill
+; CHECK-CF-NEXT: sd s11, 8(sp) # 8-byte Folded Spill
+; CHECK-CF-NEXT: .cfi_offset ra, -8
+; CHECK-CF-NEXT: .cfi_offset s0, -16
+; CHECK-CF-NEXT: .cfi_offset s1, -24
+; CHECK-CF-NEXT: .cfi_offset s2, -32
+; CHECK-CF-NEXT: .cfi_offset s3, -40
+; CHECK-CF-NEXT: .cfi_offset s4, -48
+; CHECK-CF-NEXT: .cfi_offset s5, -56
+; CHECK-CF-NEXT: .cfi_offset s6, -64
+; CHECK-CF-NEXT: .cfi_offset s7, -72
+; CHECK-CF-NEXT: .cfi_offset s8, -80
+; CHECK-CF-NEXT: .cfi_offset s9, -88
+; CHECK-CF-NEXT: .cfi_offset s10, -96
+; CHECK-CF-NEXT: .cfi_offset s11, -104
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li ra, 1
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li t0, 5
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li t1, 6
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li t2, 7
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s0, 8
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s1, 9
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li a0, 10
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li a1, 11
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li a2, 12
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li a3, 13
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li a4, 14
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li a5, 15
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li a6, 16
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li a7, 17
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s2, 18
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s3, 19
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s4, 20
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s5, 21
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s6, 22
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s7, 23
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s8, 24
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s9, 25
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s10, 26
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s11, 27
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li t3, 28
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li t4, 29
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li t5, 30
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li t6, 31
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: beq t5, t6, .LBB2_1
+; CHECK-CF-NEXT: # %bb.3:
+; CHECK-CF-NEXT: sd t2, 0(sp) # 8-byte Folded Spill
+; CHECK-CF-NEXT: jump .LBB2_4, t2
+; CHECK-CF-NEXT: .LBB2_1: # %branch_1
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: .zero 1048576
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: j .LBB2_2
+; CHECK-CF-NEXT: .LBB2_4: # %branch_2
+; CHECK-CF-NEXT: ld t2, 0(sp) # 8-byte Folded Reload
+; CHECK-CF-NEXT: .LBB2_2: # %branch_2
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use ra
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use t0
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use t1
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use t2
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s0
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s1
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use a0
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use a1
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use a2
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use a3
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use a4
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use a5
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use a6
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use a7
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s2
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s3
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s4
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s5
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s6
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s7
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s8
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s9
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s10
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s11
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use t3
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use t4
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use t5
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use t6
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: ld ra, 104(sp) # 8-byte Folded Reload
+; CHECK-CF-NEXT: ld s0, 96(sp) # 8-byte Folded Reload
+; CHECK-CF-NEXT: ld s1, 88(sp) # 8-byte Folded Reload
+; CHECK-CF-NEXT: ld s2, 80(sp) # 8-byte Folded Reload
+; CHECK-CF-NEXT: ld s3, 72(sp) # 8-byte Folded Reload
+; CHECK-CF-NEXT: ld s4, 64(sp) # 8-byte Folded Reload
+; CHECK-CF-NEXT: ld s5, 56(sp) # 8-byte Folded Reload
+; CHECK-CF-NEXT: ld s6, 48(sp) # 8-byte Folded Reload
+; CHECK-CF-NEXT: ld s7, 40(sp) # 8-byte Folded Reload
+; CHECK-CF-NEXT: ld s8, 32(sp) # 8-byte Folded Reload
+; CHECK-CF-NEXT: ld s9, 24(sp) # 8-byte Folded Reload
+; CHECK-CF-NEXT: ld s10, 16(sp) # 8-byte Folded Reload
+; CHECK-CF-NEXT: ld s11, 8(sp) # 8-byte Folded Reload
+; CHECK-CF-NEXT: .cfi_restore ra
+; CHECK-CF-NEXT: .cfi_restore s0
+; CHECK-CF-NEXT: .cfi_restore s1
+; CHECK-CF-NEXT: .cfi_restore s2
+; CHECK-CF-NEXT: .cfi_restore s3
+; CHECK-CF-NEXT: .cfi_restore s4
+; CHECK-CF-NEXT: .cfi_restore s5
+; CHECK-CF-NEXT: .cfi_restore s6
+; CHECK-CF-NEXT: .cfi_restore s7
+; CHECK-CF-NEXT: .cfi_restore s8
+; CHECK-CF-NEXT: .cfi_restore s9
+; CHECK-CF-NEXT: .cfi_restore s10
+; CHECK-CF-NEXT: .cfi_restore s11
+; CHECK-CF-NEXT: addi sp, sp, 112
+; CHECK-CF-NEXT: .cfi_def_cfa_offset 0
+; CHECK-CF-NEXT: ret
%ra = call i64 asm sideeffect "addi ra, x0, 1", "={ra}"()
%t0 = call i64 asm sideeffect "addi t0, x0, 5", "={t0}"()
%t1 = call i64 asm sideeffect "addi t1, x0, 6", "={t1}"()
@@ -911,254 +915,255 @@ define void @relax_jal_spill_64_adjust_spill_slot() {
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: ret
;
-; CHECK-ZICFILP-LABEL: relax_jal_spill_64_adjust_spill_slot:
-; CHECK-ZICFILP: # %bb.0:
-; CHECK-ZICFILP-NEXT: addi sp, sp, -2032
-; CHECK-ZICFILP-NEXT: .cfi_def_cfa_offset 2032
-; CHECK-ZICFILP-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sd s0, 2016(sp) # 8-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sd s1, 2008(sp) # 8-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sd s2, 2000(sp) # 8-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sd s3, 1992(sp) # 8-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sd s4, 1984(sp) # 8-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sd s5, 1976(sp) # 8-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sd s6, 1968(sp) # 8-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sd s7, 1960(sp) # 8-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sd s8, 1952(sp) # 8-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sd s9, 1944(sp) # 8-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sd s10, 1936(sp) # 8-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sd s11, 1928(sp) # 8-byte Folded Spill
-; CHECK-ZICFILP-NEXT: .cfi_offset ra, -8
-; CHECK-ZICFILP-NEXT: .cfi_offset s0, -16
-; CHECK-ZICFILP-NEXT: .cfi_offset s1, -24
-; CHECK-ZICFILP-NEXT: .cfi_offset s2, -32
-; CHECK-ZICFILP-NEXT: .cfi_offset s3, -40
-; CHECK-ZICFILP-NEXT: .cfi_offset s4, -48
-; CHECK-ZICFILP-NEXT: .cfi_offset s5, -56
-; CHECK-ZICFILP-NEXT: .cfi_offset s6, -64
-; CHECK-ZICFILP-NEXT: .cfi_offset s7, -72
-; CHECK-ZICFILP-NEXT: .cfi_offset s8, -80
-; CHECK-ZICFILP-NEXT: .cfi_offset s9, -88
-; CHECK-ZICFILP-NEXT: .cfi_offset s10, -96
-; CHECK-ZICFILP-NEXT: .cfi_offset s11, -104
-; CHECK-ZICFILP-NEXT: addi s0, sp, 2032
-; CHECK-ZICFILP-NEXT: .cfi_def_cfa s0, 0
-; CHECK-ZICFILP-NEXT: lui a0, 2
-; CHECK-ZICFILP-NEXT: addi a0, a0, -2032
-; CHECK-ZICFILP-NEXT: sub sp, sp, a0
-; CHECK-ZICFILP-NEXT: srli a0, sp, 12
-; CHECK-ZICFILP-NEXT: slli sp, a0, 12
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li ra, 1
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li t0, 5
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li t1, 6
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li t2, 7
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s0, 8
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s1, 9
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li a0, 10
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li a1, 11
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li a2, 12
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li a3, 13
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li a4, 14
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li a5, 15
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li a6, 16
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li a7, 17
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s2, 18
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s3, 19
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s4, 20
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s5, 21
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s6, 22
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s7, 23
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s8, 24
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s9, 25
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s10, 26
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s11, 27
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li t3, 28
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li t4, 29
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li t5, 30
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li t6, 31
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: beq t5, t6, .LBB3_1
-; CHECK-ZICFILP-NEXT: # %bb.3:
-; CHECK-ZICFILP-NEXT: sd s11, 0(sp) # 8-byte Folded Spill
-; CHECK-ZICFILP-NEXT: jump .LBB3_4, s11
-; CHECK-ZICFILP-NEXT: .LBB3_1: # %branch_1
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: .zero 1048576
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: j .LBB3_2
-; CHECK-ZICFILP-NEXT: .LBB3_4: # %branch_2
-; CHECK-ZICFILP-NEXT: ld s11, 0(sp) # 8-byte Folded Reload
-; CHECK-ZICFILP-NEXT: .LBB3_2: # %branch_2
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use ra
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use t0
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use t1
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use t2
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s0
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s1
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use a0
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use a1
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use a2
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use a3
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use a4
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use a5
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use a6
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use a7
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s2
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s3
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s4
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s5
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s6
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s7
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s8
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s9
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s10
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s11
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use t3
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use t4
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use t5
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use t6
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: addi sp, s0, -2032
-; CHECK-ZICFILP-NEXT: .cfi_def_cfa sp, 2032
-; CHECK-ZICFILP-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload
-; CHECK-ZICFILP-NEXT: ld s0, 2016(sp) # 8-byte Folded Reload
-; CHECK-ZICFILP-NEXT: ld s1, 2008(sp) # 8-byte Folded Reload
-; CHECK-ZICFILP-NEXT: ld s2, 2000(sp) # 8-byte Folded Reload
-; CHECK-ZICFILP-NEXT: ld s3, 1992(sp) # 8-byte Folded Reload
-; CHECK-ZICFILP-NEXT: ld s4, 1984(sp) # 8-byte Folded Reload
-; CHECK-ZICFILP-NEXT: ld s5, 1976(sp) # 8-byte Folded Reload
-; CHECK-ZICFILP-NEXT: ld s6, 1968(sp) # 8-byte Folded Reload
-; CHECK-ZICFILP-NEXT: ld s7, 1960(sp) # 8-byte Folded Reload
-; CHECK-ZICFILP-NEXT: ld s8, 1952(sp) # 8-byte Folded Reload
-; CHECK-ZICFILP-NEXT: ld s9, 1944(sp) # 8-byte Folded Reload
-; CHECK-ZICFILP-NEXT: ld s10, 1936(sp) # 8-byte Folded Reload
-; CHECK-ZICFILP-NEXT: ld s11, 1928(sp) # 8-byte Folded Reload
-; CHECK-ZICFILP-NEXT: .cfi_restore ra
-; CHECK-ZICFILP-NEXT: .cfi_restore s0
-; CHECK-ZICFILP-NEXT: .cfi_restore s1
-; CHECK-ZICFILP-NEXT: .cfi_restore s2
-; CHECK-ZICFILP-NEXT: .cfi_restore s3
-; CHECK-ZICFILP-NEXT: .cfi_restore s4
-; CHECK-ZICFILP-NEXT: .cfi_restore s5
-; CHECK-ZICFILP-NEXT: .cfi_restore s6
-; CHECK-ZICFILP-NEXT: .cfi_restore s7
-; CHECK-ZICFILP-NEXT: .cfi_restore s8
-; CHECK-ZICFILP-NEXT: .cfi_restore s9
-; CHECK-ZICFILP-NEXT: .cfi_restore s10
-; CHECK-ZICFILP-NEXT: .cfi_restore s11
-; CHECK-ZICFILP-NEXT: addi sp, sp, 2032
-; CHECK-ZICFILP-NEXT: .cfi_def_cfa_offset 0
-; CHECK-ZICFILP-NEXT: ret
+; CHECK-CF-LABEL: relax_jal_spill_64_adjust_spill_slot:
+; CHECK-CF: # %bb.0:
+; CHECK-CF-NEXT: lpad 0
+; CHECK-CF-NEXT: addi sp, sp, -2032
+; CHECK-CF-NEXT: .cfi_def_cfa_offset 2032
+; CHECK-CF-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill
+; CHECK-CF-NEXT: sd s0, 2016(sp) # 8-byte Folded Spill
+; CHECK-CF-NEXT: sd s1, 2008(sp) # 8-byte Folded Spill
+; CHECK-CF-NEXT: sd s2, 2000(sp) # 8-byte Folded Spill
+; CHECK-CF-NEXT: sd s3, 1992(sp) # 8-byte Folded Spill
+; CHECK-CF-NEXT: sd s4, 1984(sp) # 8-byte Folded Spill
+; CHECK-CF-NEXT: sd s5, 1976(sp) # 8-byte Folded Spill
+; CHECK-CF-NEXT: sd s6, 1968(sp) # 8-byte Folded Spill
+; CHECK-CF-NEXT: sd s7, 1960(sp) # 8-byte Folded Spill
+; CHECK-CF-NEXT: sd s8, 1952(sp) # 8-byte Folded Spill
+; CHECK-CF-NEXT: sd s9, 1944(sp) # 8-byte Folded Spill
+; CHECK-CF-NEXT: sd s10, 1936(sp) # 8-byte Folded Spill
+; CHECK-CF-NEXT: sd s11, 1928(sp) # 8-byte Folded Spill
+; CHECK-CF-NEXT: .cfi_offset ra, -8
+; CHECK-CF-NEXT: .cfi_offset s0, -16
+; CHECK-CF-NEXT: .cfi_offset s1, -24
+; CHECK-CF-NEXT: .cfi_offset s2, -32
+; CHECK-CF-NEXT: .cfi_offset s3, -40
+; CHECK-CF-NEXT: .cfi_offset s4, -48
+; CHECK-CF-NEXT: .cfi_offset s5, -56
+; CHECK-CF-NEXT: .cfi_offset s6, -64
+; CHECK-CF-NEXT: .cfi_offset s7, -72
+; CHECK-CF-NEXT: .cfi_offset s8, -80
+; CHECK-CF-NEXT: .cfi_offset s9, -88
+; CHECK-CF-NEXT: .cfi_offset s10, -96
+; CHECK-CF-NEXT: .cfi_offset s11, -104
+; CHECK-CF-NEXT: addi s0, sp, 2032
+; CHECK-CF-NEXT: .cfi_def_cfa s0, 0
+; CHECK-CF-NEXT: lui a0, 2
+; CHECK-CF-NEXT: addi a0, a0, -2032
+; CHECK-CF-NEXT: sub sp, sp, a0
+; CHECK-CF-NEXT: srli a0, sp, 12
+; CHECK-CF-NEXT: slli sp, a0, 12
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li ra, 1
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li t0, 5
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li t1, 6
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li t2, 7
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s0, 8
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s1, 9
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li a0, 10
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li a1, 11
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li a2, 12
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li a3, 13
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li a4, 14
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li a5, 15
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li a6, 16
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li a7, 17
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s2, 18
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s3, 19
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s4, 20
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s5, 21
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s6, 22
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s7, 23
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s8, 24
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s9, 25
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s10, 26
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s11, 27
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li t3, 28
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li t4, 29
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li t5, 30
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li t6, 31
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: beq t5, t6, .LBB3_1
+; CHECK-CF-NEXT: # %bb.3:
+; CHECK-CF-NEXT: sd t2, 0(sp) # 8-byte Folded Spill
+; CHECK-CF-NEXT: jump .LBB3_4, t2
+; CHECK-CF-NEXT: .LBB3_1: # %branch_1
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: .zero 1048576
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: j .LBB3_2
+; CHECK-CF-NEXT: .LBB3_4: # %branch_2
+; CHECK-CF-NEXT: ld t2, 0(sp) # 8-byte Folded Reload
+; CHECK-CF-NEXT: .LBB3_2: # %branch_2
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use ra
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use t0
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use t1
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use t2
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s0
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s1
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use a0
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use a1
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use a2
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use a3
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use a4
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use a5
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use a6
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use a7
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s2
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s3
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s4
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s5
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s6
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s7
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s8
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s9
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s10
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s11
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use t3
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use t4
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use t5
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use t6
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: addi sp, s0, -2032
+; CHECK-CF-NEXT: .cfi_def_cfa sp, 2032
+; CHECK-CF-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload
+; CHECK-CF-NEXT: ld s0, 2016(sp) # 8-byte Folded Reload
+; CHECK-CF-NEXT: ld s1, 2008(sp) # 8-byte Folded Reload
+; CHECK-CF-NEXT: ld s2, 2000(sp) # 8-byte Folded Reload
+; CHECK-CF-NEXT: ld s3, 1992(sp) # 8-byte Folded Reload
+; CHECK-CF-NEXT: ld s4, 1984(sp) # 8-byte Folded Reload
+; CHECK-CF-NEXT: ld s5, 1976(sp) # 8-byte Folded Reload
+; CHECK-CF-NEXT: ld s6, 1968(sp) # 8-byte Folded Reload
+; CHECK-CF-NEXT: ld s7, 1960(sp) # 8-byte Folded Reload
+; CHECK-CF-NEXT: ld s8, 1952(sp) # 8-byte Folded Reload
+; CHECK-CF-NEXT: ld s9, 1944(sp) # 8-byte Folded Reload
+; CHECK-CF-NEXT: ld s10, 1936(sp) # 8-byte Folded Reload
+; CHECK-CF-NEXT: ld s11, 1928(sp) # 8-byte Folded Reload
+; CHECK-CF-NEXT: .cfi_restore ra
+; CHECK-CF-NEXT: .cfi_restore s0
+; CHECK-CF-NEXT: .cfi_restore s1
+; CHECK-CF-NEXT: .cfi_restore s2
+; CHECK-CF-NEXT: .cfi_restore s3
+; CHECK-CF-NEXT: .cfi_restore s4
+; CHECK-CF-NEXT: .cfi_restore s5
+; CHECK-CF-NEXT: .cfi_restore s6
+; CHECK-CF-NEXT: .cfi_restore s7
+; CHECK-CF-NEXT: .cfi_restore s8
+; CHECK-CF-NEXT: .cfi_restore s9
+; CHECK-CF-NEXT: .cfi_restore s10
+; CHECK-CF-NEXT: .cfi_restore s11
+; CHECK-CF-NEXT: addi sp, sp, 2032
+; CHECK-CF-NEXT: .cfi_def_cfa_offset 0
+; CHECK-CF-NEXT: ret
%stack_obj = alloca i64, align 4096
%ra = call i64 asm sideeffect "addi ra, x0, 1", "={ra}"()
@@ -1490,263 +1495,264 @@ define void @relax_jal_spill_64_restore_block_correspondence() {
; CHECK-NEXT: sd s11, 0(sp) # 8-byte Folded Spill
; CHECK-NEXT: jump .LBB4_8, s11
;
-; CHECK-ZICFILP-LABEL: relax_jal_spill_64_restore_block_correspondence:
-; CHECK-ZICFILP: # %bb.0: # %entry
-; CHECK-ZICFILP-NEXT: addi sp, sp, -112
-; CHECK-ZICFILP-NEXT: .cfi_def_cfa_offset 112
-; CHECK-ZICFILP-NEXT: sd ra, 104(sp) # 8-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sd s0, 96(sp) # 8-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sd s1, 88(sp) # 8-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sd s2, 80(sp) # 8-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sd s3, 72(sp) # 8-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sd s4, 64(sp) # 8-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sd s5, 56(sp) # 8-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sd s6, 48(sp) # 8-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sd s7, 40(sp) # 8-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sd s8, 32(sp) # 8-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sd s9, 24(sp) # 8-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sd s10, 16(sp) # 8-byte Folded Spill
-; CHECK-ZICFILP-NEXT: sd s11, 8(sp) # 8-byte Folded Spill
-; CHECK-ZICFILP-NEXT: .cfi_offset ra, -8
-; CHECK-ZICFILP-NEXT: .cfi_offset s0, -16
-; CHECK-ZICFILP-NEXT: .cfi_offset s1, -24
-; CHECK-ZICFILP-NEXT: .cfi_offset s2, -32
-; CHECK-ZICFILP-NEXT: .cfi_offset s3, -40
-; CHECK-ZICFILP-NEXT: .cfi_offset s4, -48
-; CHECK-ZICFILP-NEXT: .cfi_offset s5, -56
-; CHECK-ZICFILP-NEXT: .cfi_offset s6, -64
-; CHECK-ZICFILP-NEXT: .cfi_offset s7, -72
-; CHECK-ZICFILP-NEXT: .cfi_offset s8, -80
-; CHECK-ZICFILP-NEXT: .cfi_offset s9, -88
-; CHECK-ZICFILP-NEXT: .cfi_offset s10, -96
-; CHECK-ZICFILP-NEXT: .cfi_offset s11, -104
-; CHECK-ZICFILP-NEXT: .cfi_remember_state
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li ra, 1
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li t0, 5
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li t1, 6
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li t2, 7
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s0, 8
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s1, 9
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li a0, 10
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li a1, 11
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li a2, 12
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li a3, 13
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li a4, 14
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li a5, 15
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li a6, 16
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li a7, 17
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s2, 18
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s3, 19
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s4, 20
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s5, 21
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s6, 22
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s7, 23
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s8, 24
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s9, 25
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s10, 26
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li s11, 27
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li t3, 28
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li t4, 29
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li t5, 30
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: li t6, 31
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: bne t5, t6, .LBB4_2
-; CHECK-ZICFILP-NEXT: j .LBB4_1
-; CHECK-ZICFILP-NEXT: .LBB4_8: # %dest_1
-; CHECK-ZICFILP-NEXT: ld s11, 0(sp) # 8-byte Folded Reload
-; CHECK-ZICFILP-NEXT: .LBB4_1: # %dest_1
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # dest 1
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: j .LBB4_3
-; CHECK-ZICFILP-NEXT: .LBB4_2: # %cond_2
-; CHECK-ZICFILP-NEXT: bne t3, t4, .LBB4_5
-; CHECK-ZICFILP-NEXT: .LBB4_3: # %dest_2
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # dest 2
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: .LBB4_4: # %dest_3
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # dest 3
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use ra
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use t0
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use t1
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use t2
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s0
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s1
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use a0
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use a1
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use a2
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use a3
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use a4
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use a5
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use a6
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use a7
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s2
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s3
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s4
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s5
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s6
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s7
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s8
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s9
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s10
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use s11
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use t3
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use t4
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use t5
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: # reg use t6
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: ld ra, 104(sp) # 8-byte Folded Reload
-; CHECK-ZICFILP-NEXT: ld s0, 96(sp) # 8-byte Folded Reload
-; CHECK-ZICFILP-NEXT: ld s1, 88(sp) # 8-byte Folded Reload
-; CHECK-ZICFILP-NEXT: ld s2, 80(sp) # 8-byte Folded Reload
-; CHECK-ZICFILP-NEXT: ld s3, 72(sp) # 8-byte Folded Reload
-; CHECK-ZICFILP-NEXT: ld s4, 64(sp) # 8-byte Folded Reload
-; CHECK-ZICFILP-NEXT: ld s5, 56(sp) # 8-byte Folded Reload
-; CHECK-ZICFILP-NEXT: ld s6, 48(sp) # 8-byte Folded Reload
-; CHECK-ZICFILP-NEXT: ld s7, 40(sp) # 8-byte Folded Reload
-; CHECK-ZICFILP-NEXT: ld s8, 32(sp) # 8-byte Folded Reload
-; CHECK-ZICFILP-NEXT: ld s9, 24(sp) # 8-byte Folded Reload
-; CHECK-ZICFILP-NEXT: ld s10, 16(sp) # 8-byte Folded Reload
-; CHECK-ZICFILP-NEXT: ld s11, 8(sp) # 8-byte Folded Reload
-; CHECK-ZICFILP-NEXT: .cfi_restore ra
-; CHECK-ZICFILP-NEXT: .cfi_restore s0
-; CHECK-ZICFILP-NEXT: .cfi_restore s1
-; CHECK-ZICFILP-NEXT: .cfi_restore s2
-; CHECK-ZICFILP-NEXT: .cfi_restore s3
-; CHECK-ZICFILP-NEXT: .cfi_restore s4
-; CHECK-ZICFILP-NEXT: .cfi_restore s5
-; CHECK-ZICFILP-NEXT: .cfi_restore s6
-; CHECK-ZICFILP-NEXT: .cfi_restore s7
-; CHECK-ZICFILP-NEXT: .cfi_restore s8
-; CHECK-ZICFILP-NEXT: .cfi_restore s9
-; CHECK-ZICFILP-NEXT: .cfi_restore s10
-; CHECK-ZICFILP-NEXT: .cfi_restore s11
-; CHECK-ZICFILP-NEXT: addi sp, sp, 112
-; CHECK-ZICFILP-NEXT: .cfi_def_cfa_offset 0
-; CHECK-ZICFILP-NEXT: ret
-; CHECK-ZICFILP-NEXT: .LBB4_5: # %cond_3
-; CHECK-ZICFILP-NEXT: .cfi_restore_state
-; CHECK-ZICFILP-NEXT: beq t1, t2, .LBB4_4
-; CHECK-ZICFILP-NEXT: # %bb.6: # %space
-; CHECK-ZICFILP-NEXT: #APP
-; CHECK-ZICFILP-NEXT: .zero 1048576
-; CHECK-ZICFILP-NEXT: #NO_APP
-; CHECK-ZICFILP-NEXT: # %bb.7: # %space
-; CHECK-ZICFILP-NEXT: sd s11, 0(sp) # 8-byte Folded Spill
-; CHECK-ZICFILP-NEXT: jump .LBB4_8, s11
+; CHECK-CF-LABEL: relax_jal_spill_64_restore_block_correspondence:
+; CHECK-CF: # %bb.0: # %entry
+; CHECK-CF-NEXT: lpad 0
+; CHECK-CF-NEXT: addi sp, sp, -112
+; CHECK-CF-NEXT: .cfi_def_cfa_offset 112
+; CHECK-CF-NEXT: sd ra, 104(sp) # 8-byte Folded Spill
+; CHECK-CF-NEXT: sd s0, 96(sp) # 8-byte Folded Spill
+; CHECK-CF-NEXT: sd s1, 88(sp) # 8-byte Folded Spill
+; CHECK-CF-NEXT: sd s2, 80(sp) # 8-byte Folded Spill
+; CHECK-CF-NEXT: sd s3, 72(sp) # 8-byte Folded Spill
+; CHECK-CF-NEXT: sd s4, 64(sp) # 8-byte Folded Spill
+; CHECK-CF-NEXT: sd s5, 56(sp) # 8-byte Folded Spill
+; CHECK-CF-NEXT: sd s6, 48(sp) # 8-byte Folded Spill
+; CHECK-CF-NEXT: sd s7, 40(sp) # 8-byte Folded Spill
+; CHECK-CF-NEXT: sd s8, 32(sp) # 8-byte Folded Spill
+; CHECK-CF-NEXT: sd s9, 24(sp) # 8-byte Folded Spill
+; CHECK-CF-NEXT: sd s10, 16(sp) # 8-byte Folded Spill
+; CHECK-CF-NEXT: sd s11, 8(sp) # 8-byte Folded Spill
+; CHECK-CF-NEXT: .cfi_offset ra, -8
+; CHECK-CF-NEXT: .cfi_offset s0, -16
+; CHECK-CF-NEXT: .cfi_offset s1, -24
+; CHECK-CF-NEXT: .cfi_offset s2, -32
+; CHECK-CF-NEXT: .cfi_offset s3, -40
+; CHECK-CF-NEXT: .cfi_offset s4, -48
+; CHECK-CF-NEXT: .cfi_offset s5, -56
+; CHECK-CF-NEXT: .cfi_offset s6, -64
+; CHECK-CF-NEXT: .cfi_offset s7, -72
+; CHECK-CF-NEXT: .cfi_offset s8, -80
+; CHECK-CF-NEXT: .cfi_offset s9, -88
+; CHECK-CF-NEXT: .cfi_offset s10, -96
+; CHECK-CF-NEXT: .cfi_offset s11, -104
+; CHECK-CF-NEXT: .cfi_remember_state
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li ra, 1
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li t0, 5
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li t1, 6
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li t2, 7
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s0, 8
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s1, 9
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li a0, 10
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li a1, 11
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li a2, 12
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li a3, 13
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li a4, 14
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li a5, 15
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li a6, 16
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li a7, 17
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s2, 18
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s3, 19
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s4, 20
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s5, 21
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s6, 22
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s7, 23
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s8, 24
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s9, 25
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s10, 26
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li s11, 27
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li t3, 28
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li t4, 29
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li t5, 30
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: li t6, 31
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: bne t5, t6, .LBB4_2
+; CHECK-CF-NEXT: j .LBB4_1
+; CHECK-CF-NEXT: .LBB4_8: # %dest_1
+; CHECK-CF-NEXT: ld t2, 0(sp) # 8-byte Folded Reload
+; CHECK-CF-NEXT: .LBB4_1: # %dest_1
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # dest 1
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: j .LBB4_3
+; CHECK-CF-NEXT: .LBB4_2: # %cond_2
+; CHECK-CF-NEXT: bne t3, t4, .LBB4_5
+; CHECK-CF-NEXT: .LBB4_3: # %dest_2
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # dest 2
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: .LBB4_4: # %dest_3
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # dest 3
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use ra
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use t0
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use t1
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use t2
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s0
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s1
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use a0
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use a1
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use a2
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use a3
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use a4
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use a5
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use a6
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use a7
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s2
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s3
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s4
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s5
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s6
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s7
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s8
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s9
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s10
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use s11
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use t3
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use t4
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use t5
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: # reg use t6
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: ld ra, 104(sp) # 8-byte Folded Reload
+; CHECK-CF-NEXT: ld s0, 96(sp) # 8-byte Folded Reload
+; CHECK-CF-NEXT: ld s1, 88(sp) # 8-byte Folded Reload
+; CHECK-CF-NEXT: ld s2, 80(sp) # 8-byte Folded Reload
+; CHECK-CF-NEXT: ld s3, 72(sp) # 8-byte Folded Reload
+; CHECK-CF-NEXT: ld s4, 64(sp) # 8-byte Folded Reload
+; CHECK-CF-NEXT: ld s5, 56(sp) # 8-byte Folded Reload
+; CHECK-CF-NEXT: ld s6, 48(sp) # 8-byte Folded Reload
+; CHECK-CF-NEXT: ld s7, 40(sp) # 8-byte Folded Reload
+; CHECK-CF-NEXT: ld s8, 32(sp) # 8-byte Folded Reload
+; CHECK-CF-NEXT: ld s9, 24(sp) # 8-byte Folded Reload
+; CHECK-CF-NEXT: ld s10, 16(sp) # 8-byte Folded Reload
+; CHECK-CF-NEXT: ld s11, 8(sp) # 8-byte Folded Reload
+; CHECK-CF-NEXT: .cfi_restore ra
+; CHECK-CF-NEXT: .cfi_restore s0
+; CHECK-CF-NEXT: .cfi_restore s1
+; CHECK-CF-NEXT: .cfi_restore s2
+; CHECK-CF-NEXT: .cfi_restore s3
+; CHECK-CF-NEXT: .cfi_restore s4
+; CHECK-CF-NEXT: .cfi_restore s5
+; CHECK-CF-NEXT: .cfi_restore s6
+; CHECK-CF-NEXT: .cfi_restore s7
+; CHECK-CF-NEXT: .cfi_restore s8
+; CHECK-CF-NEXT: .cfi_restore s9
+; CHECK-CF-NEXT: .cfi_restore s10
+; CHECK-CF-NEXT: .cfi_restore s11
+; CHECK-CF-NEXT: addi sp, sp, 112
+; CHECK-CF-NEXT: .cfi_def_cfa_offset 0
+; CHECK-CF-NEXT: ret
+; CHECK-CF-NEXT: .LBB4_5: # %cond_3
+; CHECK-CF-NEXT: .cfi_restore_state
+; CHECK-CF-NEXT: beq t1, t2, .LBB4_4
+; CHECK-CF-NEXT: # %bb.6: # %space
+; CHECK-CF-NEXT: #APP
+; CHECK-CF-NEXT: .zero 1048576
+; CHECK-CF-NEXT: #NO_APP
+; CHECK-CF-NEXT: # %bb.7: # %space
+; CHECK-CF-NEXT: sd t2, 0(sp) # 8-byte Folded Spill
+; CHECK-CF-NEXT: jump .LBB4_8, t2
entry:
%ra = call i64 asm sideeffect "addi ra, x0, 1", "={ra}"()
%t0 = call i64 asm sideeffect "addi t0, x0, 5", "={t0}"()
@@ -1839,3 +1845,6 @@ tail:
ret void
}
+
+;CFBRANCH: !llvm.module.flags = !{!0}
+;CFBRANCH: !0 = !{i32 8, !"cf-protection-branch", i32 1}
diff --git a/llvm/test/CodeGen/RISCV/tail-calls.ll b/llvm/test/CodeGen/RISCV/tail-calls.ll
index 367e79930520e..81ebac3f3a6fb 100644
--- a/llvm/test/CodeGen/RISCV/tail-calls.ll
+++ b/llvm/test/CodeGen/RISCV/tail-calls.ll
@@ -1,9 +1,16 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple riscv32-unknown-linux-gnu -o - %s | FileCheck %s
-; RUN: llc -mtriple riscv32-unknown-linux-gnu -mattr=experimental-zicfilp \
-; RUN: -code-model=large -o - %s \
-; RUN: | FileCheck %s -check-prefix=CHECK-LARGE-ZICFILP
; RUN: llc -mtriple riscv32-unknown-elf -o - %s | FileCheck %s
+; DEFINE: %{sed} = sed -e 's/!llvm.module.flags = !{!0}/!llvm.module.flags = !{!0, !15}/' \
+; DEFINE: -e 's/^;CF: //' %s
+; RUN: %{sed} | llc -mtriple=riscv32 -verify-machineinstrs \
+; RUN: | FileCheck -check-prefix=CHECK-CF-RV32 %s
+; RUN: %{sed} | llc -mtriple=riscv64 -verify-machineinstrs \
+; RUN: | FileCheck -check-prefix=CHECK-CF-RV64 %s
+; RUN: %{sed} | llc -code-model=large -mtriple=riscv32 -verify-machineinstrs \
+; RUN: | FileCheck -check-prefix=CHECK-CF-RV32-LARGE %s
+; RUN: %{sed} | llc -code-model=large -mtriple=riscv64 -verify-machineinstrs \
+; RUN: | FileCheck -check-prefix=CHECK-CF-RV64-LARGE %s
; Perform tail call optimization for global address.
declare i32 @callee_tail(i32 %i)
@@ -12,12 +19,31 @@ define i32 @caller_tail(i32 %i) nounwind {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: tail callee_tail
;
-; CHECK-LARGE-ZICFILP-LABEL: caller_tail:
-; CHECK-LARGE-ZICFILP: # %bb.0: # %entry
-; CHECK-LARGE-ZICFILP-NEXT: .Lpcrel_hi0:
-; CHECK-LARGE-ZICFILP-NEXT: auipc a1, %pcrel_hi(.LCPI0_0)
-; CHECK-LARGE-ZICFILP-NEXT: lw t1, %pcrel_lo(.Lpcrel_hi0)(a1)
-; CHECK-LARGE-ZICFILP-NEXT: jr t1
+; CHECK-CF-RV32-LABEL: caller_tail:
+; CHECK-CF-RV32: # %bb.0: # %entry
+; CHECK-CF-RV32-NEXT: lpad 0
+; CHECK-CF-RV32-NEXT: tail callee_tail
+;
+; CHECK-CF-RV64-LABEL: caller_tail:
+; CHECK-CF-RV64: # %bb.0: # %entry
+; CHECK-CF-RV64-NEXT: lpad 0
+; CHECK-CF-RV64-NEXT: tail callee_tail
+;
+; CHECK-CF-RV32-LARGE-LABEL: caller_tail:
+; CHECK-CF-RV32-LARGE: # %bb.0: # %entry
+; CHECK-CF-RV32-LARGE-NEXT: lpad 0
+; CHECK-CF-RV32-LARGE-NEXT: .Lpcrel_hi0:
+; CHECK-CF-RV32-LARGE-NEXT: auipc a1, %pcrel_hi(.LCPI0_0)
+; CHECK-CF-RV32-LARGE-NEXT: lw t2, %pcrel_lo(.Lpcrel_hi0)(a1)
+; CHECK-CF-RV32-LARGE-NEXT: jr t2
+;
+; CHECK-CF-RV64-LARGE-LABEL: caller_tail:
+; CHECK-CF-RV64-LARGE: # %bb.0: # %entry
+; CHECK-CF-RV64-LARGE-NEXT: lpad 0
+; CHECK-CF-RV64-LARGE-NEXT: .Lpcrel_hi0:
+; CHECK-CF-RV64-LARGE-NEXT: auipc a1, %pcrel_hi(.LCPI0_0)
+; CHECK-CF-RV64-LARGE-NEXT: ld t2, %pcrel_lo(.Lpcrel_hi0)(a1)
+; CHECK-CF-RV64-LARGE-NEXT: jr t2
entry:
%r = tail call i32 @callee_tail(i32 %i)
ret i32 %r
@@ -36,19 +62,57 @@ define void @caller_extern(ptr %src) optsize {
; CHECK-NEXT: mv a1, a3
; CHECK-NEXT: tail memcpy
;
-; CHECK-LARGE-ZICFILP-LABEL: caller_extern:
-; CHECK-LARGE-ZICFILP: # %bb.0: # %entry
-; CHECK-LARGE-ZICFILP-NEXT: .Lpcrel_hi1:
-; CHECK-LARGE-ZICFILP-NEXT: auipc a1, %pcrel_hi(.LCPI1_0)
-; CHECK-LARGE-ZICFILP-NEXT: .Lpcrel_hi2:
-; CHECK-LARGE-ZICFILP-NEXT: auipc a2, %pcrel_hi(.LCPI1_1)
-; CHECK-LARGE-ZICFILP-NEXT: lw a1, %pcrel_lo(.Lpcrel_hi1)(a1)
-; CHECK-LARGE-ZICFILP-NEXT: lw t1, %pcrel_lo(.Lpcrel_hi2)(a2)
-; CHECK-LARGE-ZICFILP-NEXT: li a2, 7
-; CHECK-LARGE-ZICFILP-NEXT: mv a3, a0
-; CHECK-LARGE-ZICFILP-NEXT: mv a0, a1
-; CHECK-LARGE-ZICFILP-NEXT: mv a1, a3
-; CHECK-LARGE-ZICFILP-NEXT: jr t1
+; CHECK-CF-RV32-LABEL: caller_extern:
+; CHECK-CF-RV32: # %bb.0: # %entry
+; CHECK-CF-RV32-NEXT: lpad 0
+; CHECK-CF-RV32-NEXT: lui a1, %hi(dest)
+; CHECK-CF-RV32-NEXT: addi a1, a1, %lo(dest)
+; CHECK-CF-RV32-NEXT: li a2, 7
+; CHECK-CF-RV32-NEXT: mv a3, a0
+; CHECK-CF-RV32-NEXT: mv a0, a1
+; CHECK-CF-RV32-NEXT: mv a1, a3
+; CHECK-CF-RV32-NEXT: tail memcpy
+;
+; CHECK-CF-RV64-LABEL: caller_extern:
+; CHECK-CF-RV64: # %bb.0: # %entry
+; CHECK-CF-RV64-NEXT: lpad 0
+; CHECK-CF-RV64-NEXT: lui a1, %hi(dest)
+; CHECK-CF-RV64-NEXT: addi a1, a1, %lo(dest)
+; CHECK-CF-RV64-NEXT: li a2, 7
+; CHECK-CF-RV64-NEXT: mv a3, a0
+; CHECK-CF-RV64-NEXT: mv a0, a1
+; CHECK-CF-RV64-NEXT: mv a1, a3
+; CHECK-CF-RV64-NEXT: tail memcpy
+;
+; CHECK-CF-RV32-LARGE-LABEL: caller_extern:
+; CHECK-CF-RV32-LARGE: # %bb.0: # %entry
+; CHECK-CF-RV32-LARGE-NEXT: lpad 0
+; CHECK-CF-RV32-LARGE-NEXT: .Lpcrel_hi1:
+; CHECK-CF-RV32-LARGE-NEXT: auipc a1, %pcrel_hi(.LCPI1_0)
+; CHECK-CF-RV32-LARGE-NEXT: .Lpcrel_hi2:
+; CHECK-CF-RV32-LARGE-NEXT: auipc a2, %pcrel_hi(.LCPI1_1)
+; CHECK-CF-RV32-LARGE-NEXT: lw a1, %pcrel_lo(.Lpcrel_hi1)(a1)
+; CHECK-CF-RV32-LARGE-NEXT: lw t2, %pcrel_lo(.Lpcrel_hi2)(a2)
+; CHECK-CF-RV32-LARGE-NEXT: li a2, 7
+; CHECK-CF-RV32-LARGE-NEXT: mv a3, a0
+; CHECK-CF-RV32-LARGE-NEXT: mv a0, a1
+; CHECK-CF-RV32-LARGE-NEXT: mv a1, a3
+; CHECK-CF-RV32-LARGE-NEXT: jr t2
+;
+; CHECK-CF-RV64-LARGE-LABEL: caller_extern:
+; CHECK-CF-RV64-LARGE: # %bb.0: # %entry
+; CHECK-CF-RV64-LARGE-NEXT: lpad 0
+; CHECK-CF-RV64-LARGE-NEXT: .Lpcrel_hi1:
+; CHECK-CF-RV64-LARGE-NEXT: auipc a1, %pcrel_hi(.LCPI1_0)
+; CHECK-CF-RV64-LARGE-NEXT: .Lpcrel_hi2:
+; CHECK-CF-RV64-LARGE-NEXT: auipc a2, %pcrel_hi(.LCPI1_1)
+; CHECK-CF-RV64-LARGE-NEXT: ld a1, %pcrel_lo(.Lpcrel_hi1)(a1)
+; CHECK-CF-RV64-LARGE-NEXT: ld t2, %pcrel_lo(.Lpcrel_hi2)(a2)
+; CHECK-CF-RV64-LARGE-NEXT: li a2, 7
+; CHECK-CF-RV64-LARGE-NEXT: mv a3, a0
+; CHECK-CF-RV64-LARGE-NEXT: mv a0, a1
+; CHECK-CF-RV64-LARGE-NEXT: mv a1, a3
+; CHECK-CF-RV64-LARGE-NEXT: jr t2
entry:
tail call void @llvm.memcpy.p0.p0.i32(ptr @dest, ptr %src, i32 7, i1 false)
ret void
@@ -67,19 +131,57 @@ define void @caller_extern_pgso(ptr %src) !prof !14 {
; CHECK-NEXT: mv a1, a3
; CHECK-NEXT: tail memcpy
;
-; CHECK-LARGE-ZICFILP-LABEL: caller_extern_pgso:
-; CHECK-LARGE-ZICFILP: # %bb.0: # %entry
-; CHECK-LARGE-ZICFILP-NEXT: .Lpcrel_hi3:
-; CHECK-LARGE-ZICFILP-NEXT: auipc a1, %pcrel_hi(.LCPI2_0)
-; CHECK-LARGE-ZICFILP-NEXT: .Lpcrel_hi4:
-; CHECK-LARGE-ZICFILP-NEXT: auipc a2, %pcrel_hi(.LCPI2_1)
-; CHECK-LARGE-ZICFILP-NEXT: lw a1, %pcrel_lo(.Lpcrel_hi3)(a1)
-; CHECK-LARGE-ZICFILP-NEXT: lw t1, %pcrel_lo(.Lpcrel_hi4)(a2)
-; CHECK-LARGE-ZICFILP-NEXT: li a2, 7
-; CHECK-LARGE-ZICFILP-NEXT: mv a3, a0
-; CHECK-LARGE-ZICFILP-NEXT: mv a0, a1
-; CHECK-LARGE-ZICFILP-NEXT: mv a1, a3
-; CHECK-LARGE-ZICFILP-NEXT: jr t1
+; CHECK-CF-RV32-LABEL: caller_extern_pgso:
+; CHECK-CF-RV32: # %bb.0: # %entry
+; CHECK-CF-RV32-NEXT: lpad 0
+; CHECK-CF-RV32-NEXT: lui a1, %hi(dest_pgso)
+; CHECK-CF-RV32-NEXT: addi a1, a1, %lo(dest_pgso)
+; CHECK-CF-RV32-NEXT: li a2, 7
+; CHECK-CF-RV32-NEXT: mv a3, a0
+; CHECK-CF-RV32-NEXT: mv a0, a1
+; CHECK-CF-RV32-NEXT: mv a1, a3
+; CHECK-CF-RV32-NEXT: tail memcpy
+;
+; CHECK-CF-RV64-LABEL: caller_extern_pgso:
+; CHECK-CF-RV64: # %bb.0: # %entry
+; CHECK-CF-RV64-NEXT: lpad 0
+; CHECK-CF-RV64-NEXT: lui a1, %hi(dest_pgso)
+; CHECK-CF-RV64-NEXT: addi a1, a1, %lo(dest_pgso)
+; CHECK-CF-RV64-NEXT: li a2, 7
+; CHECK-CF-RV64-NEXT: mv a3, a0
+; CHECK-CF-RV64-NEXT: mv a0, a1
+; CHECK-CF-RV64-NEXT: mv a1, a3
+; CHECK-CF-RV64-NEXT: tail memcpy
+;
+; CHECK-CF-RV32-LARGE-LABEL: caller_extern_pgso:
+; CHECK-CF-RV32-LARGE: # %bb.0: # %entry
+; CHECK-CF-RV32-LARGE-NEXT: lpad 0
+; CHECK-CF-RV32-LARGE-NEXT: .Lpcrel_hi3:
+; CHECK-CF-RV32-LARGE-NEXT: auipc a1, %pcrel_hi(.LCPI2_0)
+; CHECK-CF-RV32-LARGE-NEXT: .Lpcrel_hi4:
+; CHECK-CF-RV32-LARGE-NEXT: auipc a2, %pcrel_hi(.LCPI2_1)
+; CHECK-CF-RV32-LARGE-NEXT: lw a1, %pcrel_lo(.Lpcrel_hi3)(a1)
+; CHECK-CF-RV32-LARGE-NEXT: lw t2, %pcrel_lo(.Lpcrel_hi4)(a2)
+; CHECK-CF-RV32-LARGE-NEXT: li a2, 7
+; CHECK-CF-RV32-LARGE-NEXT: mv a3, a0
+; CHECK-CF-RV32-LARGE-NEXT: mv a0, a1
+; CHECK-CF-RV32-LARGE-NEXT: mv a1, a3
+; CHECK-CF-RV32-LARGE-NEXT: jr t2
+;
+; CHECK-CF-RV64-LARGE-LABEL: caller_extern_pgso:
+; CHECK-CF-RV64-LARGE: # %bb.0: # %entry
+; CHECK-CF-RV64-LARGE-NEXT: lpad 0
+; CHECK-CF-RV64-LARGE-NEXT: .Lpcrel_hi3:
+; CHECK-CF-RV64-LARGE-NEXT: auipc a1, %pcrel_hi(.LCPI2_0)
+; CHECK-CF-RV64-LARGE-NEXT: .Lpcrel_hi4:
+; CHECK-CF-RV64-LARGE-NEXT: auipc a2, %pcrel_hi(.LCPI2_1)
+; CHECK-CF-RV64-LARGE-NEXT: ld a1, %pcrel_lo(.Lpcrel_hi3)(a1)
+; CHECK-CF-RV64-LARGE-NEXT: ld t2, %pcrel_lo(.Lpcrel_hi4)(a2)
+; CHECK-CF-RV64-LARGE-NEXT: li a2, 7
+; CHECK-CF-RV64-LARGE-NEXT: mv a3, a0
+; CHECK-CF-RV64-LARGE-NEXT: mv a0, a1
+; CHECK-CF-RV64-LARGE-NEXT: mv a1, a3
+; CHECK-CF-RV64-LARGE-NEXT: jr t2
entry:
tail call void @llvm.memcpy.p0.p0.i32(ptr @dest_pgso, ptr %src, i32 7, i1 false)
ret void
@@ -101,19 +203,63 @@ define void @caller_indirect_tail(i32 %a) nounwind {
; CHECK-NEXT: addi t1, t1, %lo(callee_indirect1)
; CHECK-NEXT: jr t1
;
-; CHECK-LARGE-ZICFILP-LABEL: caller_indirect_tail:
-; CHECK-LARGE-ZICFILP: # %bb.0: # %entry
-; CHECK-LARGE-ZICFILP-NEXT: beqz a0, .LBB3_2
-; CHECK-LARGE-ZICFILP-NEXT: # %bb.1: # %entry
-; CHECK-LARGE-ZICFILP-NEXT: .Lpcrel_hi6:
-; CHECK-LARGE-ZICFILP-NEXT: auipc a0, %pcrel_hi(.LCPI3_0)
-; CHECK-LARGE-ZICFILP-NEXT: lw t1, %pcrel_lo(.Lpcrel_hi6)(a0)
-; CHECK-LARGE-ZICFILP-NEXT: jr t1
-; CHECK-LARGE-ZICFILP-NEXT: .LBB3_2:
-; CHECK-LARGE-ZICFILP-NEXT: .Lpcrel_hi5:
-; CHECK-LARGE-ZICFILP-NEXT: auipc a0, %pcrel_hi(.LCPI3_1)
-; CHECK-LARGE-ZICFILP-NEXT: lw t1, %pcrel_lo(.Lpcrel_hi5)(a0)
-; CHECK-LARGE-ZICFILP-NEXT: jr t1
+; CHECK-CF-RV32-LABEL: caller_indirect_tail:
+; CHECK-CF-RV32: # %bb.0: # %entry
+; CHECK-CF-RV32-NEXT: lpad 0
+; CHECK-CF-RV32-NEXT: beqz a0, .LBB3_2
+; CHECK-CF-RV32-NEXT: # %bb.1: # %entry
+; CHECK-CF-RV32-NEXT: lui t1, %hi(callee_indirect2)
+; CHECK-CF-RV32-NEXT: addi t1, t1, %lo(callee_indirect2)
+; CHECK-CF-RV32-NEXT: jr t1
+; CHECK-CF-RV32-NEXT: .LBB3_2:
+; CHECK-CF-RV32-NEXT: lui t1, %hi(callee_indirect1)
+; CHECK-CF-RV32-NEXT: addi t1, t1, %lo(callee_indirect1)
+; CHECK-CF-RV32-NEXT: jr t1
+;
+; CHECK-CF-RV64-LABEL: caller_indirect_tail:
+; CHECK-CF-RV64: # %bb.0: # %entry
+; CHECK-CF-RV64-NEXT: lpad 0
+; CHECK-CF-RV64-NEXT: sext.w a0, a0
+; CHECK-CF-RV64-NEXT: beqz a0, .LBB3_2
+; CHECK-CF-RV64-NEXT: # %bb.1: # %entry
+; CHECK-CF-RV64-NEXT: lui t1, %hi(callee_indirect2)
+; CHECK-CF-RV64-NEXT: addi t1, t1, %lo(callee_indirect2)
+; CHECK-CF-RV64-NEXT: jr t1
+; CHECK-CF-RV64-NEXT: .LBB3_2:
+; CHECK-CF-RV64-NEXT: lui t1, %hi(callee_indirect1)
+; CHECK-CF-RV64-NEXT: addi t1, t1, %lo(callee_indirect1)
+; CHECK-CF-RV64-NEXT: jr t1
+;
+; CHECK-CF-RV32-LARGE-LABEL: caller_indirect_tail:
+; CHECK-CF-RV32-LARGE: # %bb.0: # %entry
+; CHECK-CF-RV32-LARGE-NEXT: lpad 0
+; CHECK-CF-RV32-LARGE-NEXT: beqz a0, .LBB3_2
+; CHECK-CF-RV32-LARGE-NEXT: # %bb.1: # %entry
+; CHECK-CF-RV32-LARGE-NEXT: .Lpcrel_hi6:
+; CHECK-CF-RV32-LARGE-NEXT: auipc a0, %pcrel_hi(.LCPI3_0)
+; CHECK-CF-RV32-LARGE-NEXT: lw t1, %pcrel_lo(.Lpcrel_hi6)(a0)
+; CHECK-CF-RV32-LARGE-NEXT: jr t1
+; CHECK-CF-RV32-LARGE-NEXT: .LBB3_2:
+; CHECK-CF-RV32-LARGE-NEXT: .Lpcrel_hi5:
+; CHECK-CF-RV32-LARGE-NEXT: auipc a0, %pcrel_hi(.LCPI3_1)
+; CHECK-CF-RV32-LARGE-NEXT: lw t1, %pcrel_lo(.Lpcrel_hi5)(a0)
+; CHECK-CF-RV32-LARGE-NEXT: jr t1
+;
+; CHECK-CF-RV64-LARGE-LABEL: caller_indirect_tail:
+; CHECK-CF-RV64-LARGE: # %bb.0: # %entry
+; CHECK-CF-RV64-LARGE-NEXT: lpad 0
+; CHECK-CF-RV64-LARGE-NEXT: sext.w a0, a0
+; CHECK-CF-RV64-LARGE-NEXT: beqz a0, .LBB3_2
+; CHECK-CF-RV64-LARGE-NEXT: # %bb.1: # %entry
+; CHECK-CF-RV64-LARGE-NEXT: .Lpcrel_hi6:
+; CHECK-CF-RV64-LARGE-NEXT: auipc a0, %pcrel_hi(.LCPI3_0)
+; CHECK-CF-RV64-LARGE-NEXT: ld t1, %pcrel_lo(.Lpcrel_hi6)(a0)
+; CHECK-CF-RV64-LARGE-NEXT: jr t1
+; CHECK-CF-RV64-LARGE-NEXT: .LBB3_2:
+; CHECK-CF-RV64-LARGE-NEXT: .Lpcrel_hi5:
+; CHECK-CF-RV64-LARGE-NEXT: auipc a0, %pcrel_hi(.LCPI3_1)
+; CHECK-CF-RV64-LARGE-NEXT: ld t1, %pcrel_lo(.Lpcrel_hi5)(a0)
+; CHECK-CF-RV64-LARGE-NEXT: jr t1
entry:
%tobool = icmp eq i32 %a, 0
%callee = select i1 %tobool, ptr @callee_indirect1, ptr @callee_indirect2
@@ -136,17 +282,57 @@ define i32 @caller_indirect_no_t0(ptr %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5
; CHECK-NEXT: mv a6, a7
; CHECK-NEXT: jr t1
;
-; CHECK-LARGE-ZICFILP-LABEL: caller_indirect_no_t0:
-; CHECK-LARGE-ZICFILP: # %bb.0:
-; CHECK-LARGE-ZICFILP-NEXT: mv t1, a0
-; CHECK-LARGE-ZICFILP-NEXT: mv a0, a1
-; CHECK-LARGE-ZICFILP-NEXT: mv a1, a2
-; CHECK-LARGE-ZICFILP-NEXT: mv a2, a3
-; CHECK-LARGE-ZICFILP-NEXT: mv a3, a4
-; CHECK-LARGE-ZICFILP-NEXT: mv a4, a5
-; CHECK-LARGE-ZICFILP-NEXT: mv a5, a6
-; CHECK-LARGE-ZICFILP-NEXT: mv a6, a7
-; CHECK-LARGE-ZICFILP-NEXT: jr t1
+; CHECK-CF-RV32-LABEL: caller_indirect_no_t0:
+; CHECK-CF-RV32: # %bb.0:
+; CHECK-CF-RV32-NEXT: lpad 0
+; CHECK-CF-RV32-NEXT: mv t1, a0
+; CHECK-CF-RV32-NEXT: mv a0, a1
+; CHECK-CF-RV32-NEXT: mv a1, a2
+; CHECK-CF-RV32-NEXT: mv a2, a3
+; CHECK-CF-RV32-NEXT: mv a3, a4
+; CHECK-CF-RV32-NEXT: mv a4, a5
+; CHECK-CF-RV32-NEXT: mv a5, a6
+; CHECK-CF-RV32-NEXT: mv a6, a7
+; CHECK-CF-RV32-NEXT: jr t1
+;
+; CHECK-CF-RV64-LABEL: caller_indirect_no_t0:
+; CHECK-CF-RV64: # %bb.0:
+; CHECK-CF-RV64-NEXT: lpad 0
+; CHECK-CF-RV64-NEXT: mv t1, a0
+; CHECK-CF-RV64-NEXT: mv a0, a1
+; CHECK-CF-RV64-NEXT: mv a1, a2
+; CHECK-CF-RV64-NEXT: mv a2, a3
+; CHECK-CF-RV64-NEXT: mv a3, a4
+; CHECK-CF-RV64-NEXT: mv a4, a5
+; CHECK-CF-RV64-NEXT: mv a5, a6
+; CHECK-CF-RV64-NEXT: mv a6, a7
+; CHECK-CF-RV64-NEXT: jr t1
+;
+; CHECK-CF-RV32-LARGE-LABEL: caller_indirect_no_t0:
+; CHECK-CF-RV32-LARGE: # %bb.0:
+; CHECK-CF-RV32-LARGE-NEXT: lpad 0
+; CHECK-CF-RV32-LARGE-NEXT: mv t1, a0
+; CHECK-CF-RV32-LARGE-NEXT: mv a0, a1
+; CHECK-CF-RV32-LARGE-NEXT: mv a1, a2
+; CHECK-CF-RV32-LARGE-NEXT: mv a2, a3
+; CHECK-CF-RV32-LARGE-NEXT: mv a3, a4
+; CHECK-CF-RV32-LARGE-NEXT: mv a4, a5
+; CHECK-CF-RV32-LARGE-NEXT: mv a5, a6
+; CHECK-CF-RV32-LARGE-NEXT: mv a6, a7
+; CHECK-CF-RV32-LARGE-NEXT: jr t1
+;
+; CHECK-CF-RV64-LARGE-LABEL: caller_indirect_no_t0:
+; CHECK-CF-RV64-LARGE: # %bb.0:
+; CHECK-CF-RV64-LARGE-NEXT: lpad 0
+; CHECK-CF-RV64-LARGE-NEXT: mv t1, a0
+; CHECK-CF-RV64-LARGE-NEXT: mv a0, a1
+; CHECK-CF-RV64-LARGE-NEXT: mv a1, a2
+; CHECK-CF-RV64-LARGE-NEXT: mv a2, a3
+; CHECK-CF-RV64-LARGE-NEXT: mv a3, a4
+; CHECK-CF-RV64-LARGE-NEXT: mv a4, a5
+; CHECK-CF-RV64-LARGE-NEXT: mv a5, a6
+; CHECK-CF-RV64-LARGE-NEXT: mv a6, a7
+; CHECK-CF-RV64-LARGE-NEXT: jr t1
%9 = tail call i32 %0(i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6, i32 %7)
ret i32 %9
}
@@ -170,24 +356,79 @@ define void @caller_varargs(i32 %a, i32 %b) nounwind {
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
;
-; CHECK-LARGE-ZICFILP-LABEL: caller_varargs:
-; CHECK-LARGE-ZICFILP: # %bb.0: # %entry
-; CHECK-LARGE-ZICFILP-NEXT: addi sp, sp, -16
-; CHECK-LARGE-ZICFILP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; CHECK-LARGE-ZICFILP-NEXT: .Lpcrel_hi7:
-; CHECK-LARGE-ZICFILP-NEXT: auipc a2, %pcrel_hi(.LCPI5_0)
-; CHECK-LARGE-ZICFILP-NEXT: lw t1, %pcrel_lo(.Lpcrel_hi7)(a2)
-; CHECK-LARGE-ZICFILP-NEXT: sw a0, 0(sp)
-; CHECK-LARGE-ZICFILP-NEXT: mv a2, a1
-; CHECK-LARGE-ZICFILP-NEXT: mv a3, a0
-; CHECK-LARGE-ZICFILP-NEXT: mv a4, a0
-; CHECK-LARGE-ZICFILP-NEXT: mv a5, a1
-; CHECK-LARGE-ZICFILP-NEXT: mv a6, a1
-; CHECK-LARGE-ZICFILP-NEXT: mv a7, a0
-; CHECK-LARGE-ZICFILP-NEXT: jalr t1
-; CHECK-LARGE-ZICFILP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; CHECK-LARGE-ZICFILP-NEXT: addi sp, sp, 16
-; CHECK-LARGE-ZICFILP-NEXT: ret
+; CHECK-CF-RV32-LABEL: caller_varargs:
+; CHECK-CF-RV32: # %bb.0: # %entry
+; CHECK-CF-RV32-NEXT: lpad 0
+; CHECK-CF-RV32-NEXT: addi sp, sp, -16
+; CHECK-CF-RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; CHECK-CF-RV32-NEXT: sw a0, 0(sp)
+; CHECK-CF-RV32-NEXT: mv a2, a1
+; CHECK-CF-RV32-NEXT: mv a3, a0
+; CHECK-CF-RV32-NEXT: mv a4, a0
+; CHECK-CF-RV32-NEXT: mv a5, a1
+; CHECK-CF-RV32-NEXT: mv a6, a1
+; CHECK-CF-RV32-NEXT: mv a7, a0
+; CHECK-CF-RV32-NEXT: call callee_varargs
+; CHECK-CF-RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; CHECK-CF-RV32-NEXT: addi sp, sp, 16
+; CHECK-CF-RV32-NEXT: ret
+;
+; CHECK-CF-RV64-LABEL: caller_varargs:
+; CHECK-CF-RV64: # %bb.0: # %entry
+; CHECK-CF-RV64-NEXT: lpad 0
+; CHECK-CF-RV64-NEXT: addi sp, sp, -16
+; CHECK-CF-RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; CHECK-CF-RV64-NEXT: sd a0, 0(sp)
+; CHECK-CF-RV64-NEXT: mv a2, a1
+; CHECK-CF-RV64-NEXT: mv a3, a0
+; CHECK-CF-RV64-NEXT: mv a4, a0
+; CHECK-CF-RV64-NEXT: mv a5, a1
+; CHECK-CF-RV64-NEXT: mv a6, a1
+; CHECK-CF-RV64-NEXT: mv a7, a0
+; CHECK-CF-RV64-NEXT: call callee_varargs
+; CHECK-CF-RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; CHECK-CF-RV64-NEXT: addi sp, sp, 16
+; CHECK-CF-RV64-NEXT: ret
+;
+; CHECK-CF-RV32-LARGE-LABEL: caller_varargs:
+; CHECK-CF-RV32-LARGE: # %bb.0: # %entry
+; CHECK-CF-RV32-LARGE-NEXT: lpad 0
+; CHECK-CF-RV32-LARGE-NEXT: addi sp, sp, -16
+; CHECK-CF-RV32-LARGE-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; CHECK-CF-RV32-LARGE-NEXT: .Lpcrel_hi7:
+; CHECK-CF-RV32-LARGE-NEXT: auipc a2, %pcrel_hi(.LCPI5_0)
+; CHECK-CF-RV32-LARGE-NEXT: lw t2, %pcrel_lo(.Lpcrel_hi7)(a2)
+; CHECK-CF-RV32-LARGE-NEXT: sw a0, 0(sp)
+; CHECK-CF-RV32-LARGE-NEXT: mv a2, a1
+; CHECK-CF-RV32-LARGE-NEXT: mv a3, a0
+; CHECK-CF-RV32-LARGE-NEXT: mv a4, a0
+; CHECK-CF-RV32-LARGE-NEXT: mv a5, a1
+; CHECK-CF-RV32-LARGE-NEXT: mv a6, a1
+; CHECK-CF-RV32-LARGE-NEXT: mv a7, a0
+; CHECK-CF-RV32-LARGE-NEXT: jalr t2
+; CHECK-CF-RV32-LARGE-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; CHECK-CF-RV32-LARGE-NEXT: addi sp, sp, 16
+; CHECK-CF-RV32-LARGE-NEXT: ret
+;
+; CHECK-CF-RV64-LARGE-LABEL: caller_varargs:
+; CHECK-CF-RV64-LARGE: # %bb.0: # %entry
+; CHECK-CF-RV64-LARGE-NEXT: lpad 0
+; CHECK-CF-RV64-LARGE-NEXT: addi sp, sp, -16
+; CHECK-CF-RV64-LARGE-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; CHECK-CF-RV64-LARGE-NEXT: .Lpcrel_hi7:
+; CHECK-CF-RV64-LARGE-NEXT: auipc a2, %pcrel_hi(.LCPI5_0)
+; CHECK-CF-RV64-LARGE-NEXT: ld t2, %pcrel_lo(.Lpcrel_hi7)(a2)
+; CHECK-CF-RV64-LARGE-NEXT: sd a0, 0(sp)
+; CHECK-CF-RV64-LARGE-NEXT: mv a2, a1
+; CHECK-CF-RV64-LARGE-NEXT: mv a3, a0
+; CHECK-CF-RV64-LARGE-NEXT: mv a4, a0
+; CHECK-CF-RV64-LARGE-NEXT: mv a5, a1
+; CHECK-CF-RV64-LARGE-NEXT: mv a6, a1
+; CHECK-CF-RV64-LARGE-NEXT: mv a7, a0
+; CHECK-CF-RV64-LARGE-NEXT: jalr t2
+; CHECK-CF-RV64-LARGE-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; CHECK-CF-RV64-LARGE-NEXT: addi sp, sp, 16
+; CHECK-CF-RV64-LARGE-NEXT: ret
entry:
%call = tail call i32 (i32, ...) @callee_varargs(i32 %a, i32 %b, i32 %b, i32 %a, i32 %a, i32 %b, i32 %b, i32 %a, i32 %a)
ret void
@@ -217,29 +458,99 @@ define i32 @caller_args(i32 %a, i32 %b, i32 %c, i32 %dd, i32 %e, i32 %ff, i32 %g
; CHECK-NEXT: addi sp, sp, 32
; CHECK-NEXT: ret
;
-; CHECK-LARGE-ZICFILP-LABEL: caller_args:
-; CHECK-LARGE-ZICFILP: # %bb.0: # %entry
-; CHECK-LARGE-ZICFILP-NEXT: addi sp, sp, -32
-; CHECK-LARGE-ZICFILP-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
-; CHECK-LARGE-ZICFILP-NEXT: lw t0, 32(sp)
-; CHECK-LARGE-ZICFILP-NEXT: lw t1, 36(sp)
-; CHECK-LARGE-ZICFILP-NEXT: lw t2, 40(sp)
-; CHECK-LARGE-ZICFILP-NEXT: lw t3, 44(sp)
-; CHECK-LARGE-ZICFILP-NEXT: lw t4, 48(sp)
-; CHECK-LARGE-ZICFILP-NEXT: lw t5, 52(sp)
-; CHECK-LARGE-ZICFILP-NEXT: sw t4, 16(sp)
-; CHECK-LARGE-ZICFILP-NEXT: sw t5, 20(sp)
-; CHECK-LARGE-ZICFILP-NEXT: .Lpcrel_hi8:
-; CHECK-LARGE-ZICFILP-NEXT: auipc t4, %pcrel_hi(.LCPI6_0)
-; CHECK-LARGE-ZICFILP-NEXT: lw t4, %pcrel_lo(.Lpcrel_hi8)(t4)
-; CHECK-LARGE-ZICFILP-NEXT: sw t0, 0(sp)
-; CHECK-LARGE-ZICFILP-NEXT: sw t1, 4(sp)
-; CHECK-LARGE-ZICFILP-NEXT: sw t2, 8(sp)
-; CHECK-LARGE-ZICFILP-NEXT: sw t3, 12(sp)
-; CHECK-LARGE-ZICFILP-NEXT: jalr t4
-; CHECK-LARGE-ZICFILP-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; CHECK-LARGE-ZICFILP-NEXT: addi sp, sp, 32
-; CHECK-LARGE-ZICFILP-NEXT: ret
+; CHECK-CF-RV32-LABEL: caller_args:
+; CHECK-CF-RV32: # %bb.0: # %entry
+; CHECK-CF-RV32-NEXT: lpad 0
+; CHECK-CF-RV32-NEXT: addi sp, sp, -32
+; CHECK-CF-RV32-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; CHECK-CF-RV32-NEXT: lw t0, 32(sp)
+; CHECK-CF-RV32-NEXT: lw t1, 36(sp)
+; CHECK-CF-RV32-NEXT: lw t2, 40(sp)
+; CHECK-CF-RV32-NEXT: lw t3, 44(sp)
+; CHECK-CF-RV32-NEXT: lw t4, 48(sp)
+; CHECK-CF-RV32-NEXT: lw t5, 52(sp)
+; CHECK-CF-RV32-NEXT: sw t4, 16(sp)
+; CHECK-CF-RV32-NEXT: sw t5, 20(sp)
+; CHECK-CF-RV32-NEXT: sw t0, 0(sp)
+; CHECK-CF-RV32-NEXT: sw t1, 4(sp)
+; CHECK-CF-RV32-NEXT: sw t2, 8(sp)
+; CHECK-CF-RV32-NEXT: sw t3, 12(sp)
+; CHECK-CF-RV32-NEXT: call callee_args
+; CHECK-CF-RV32-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; CHECK-CF-RV32-NEXT: addi sp, sp, 32
+; CHECK-CF-RV32-NEXT: ret
+;
+; CHECK-CF-RV64-LABEL: caller_args:
+; CHECK-CF-RV64: # %bb.0: # %entry
+; CHECK-CF-RV64-NEXT: lpad 0
+; CHECK-CF-RV64-NEXT: addi sp, sp, -64
+; CHECK-CF-RV64-NEXT: sd ra, 56(sp) # 8-byte Folded Spill
+; CHECK-CF-RV64-NEXT: ld t0, 64(sp)
+; CHECK-CF-RV64-NEXT: ld t1, 72(sp)
+; CHECK-CF-RV64-NEXT: ld t2, 80(sp)
+; CHECK-CF-RV64-NEXT: ld t3, 88(sp)
+; CHECK-CF-RV64-NEXT: ld t4, 96(sp)
+; CHECK-CF-RV64-NEXT: ld t5, 104(sp)
+; CHECK-CF-RV64-NEXT: sd t4, 32(sp)
+; CHECK-CF-RV64-NEXT: sd t5, 40(sp)
+; CHECK-CF-RV64-NEXT: sd t0, 0(sp)
+; CHECK-CF-RV64-NEXT: sd t1, 8(sp)
+; CHECK-CF-RV64-NEXT: sd t2, 16(sp)
+; CHECK-CF-RV64-NEXT: sd t3, 24(sp)
+; CHECK-CF-RV64-NEXT: call callee_args
+; CHECK-CF-RV64-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
+; CHECK-CF-RV64-NEXT: addi sp, sp, 64
+; CHECK-CF-RV64-NEXT: ret
+;
+; CHECK-CF-RV32-LARGE-LABEL: caller_args:
+; CHECK-CF-RV32-LARGE: # %bb.0: # %entry
+; CHECK-CF-RV32-LARGE-NEXT: lpad 0
+; CHECK-CF-RV32-LARGE-NEXT: addi sp, sp, -32
+; CHECK-CF-RV32-LARGE-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; CHECK-CF-RV32-LARGE-NEXT: lw t0, 32(sp)
+; CHECK-CF-RV32-LARGE-NEXT: lw t1, 36(sp)
+; CHECK-CF-RV32-LARGE-NEXT: lw t3, 40(sp)
+; CHECK-CF-RV32-LARGE-NEXT: lw t4, 44(sp)
+; CHECK-CF-RV32-LARGE-NEXT: lw t2, 48(sp)
+; CHECK-CF-RV32-LARGE-NEXT: lw t5, 52(sp)
+; CHECK-CF-RV32-LARGE-NEXT: sw t2, 16(sp)
+; CHECK-CF-RV32-LARGE-NEXT: sw t5, 20(sp)
+; CHECK-CF-RV32-LARGE-NEXT: .Lpcrel_hi8:
+; CHECK-CF-RV32-LARGE-NEXT: auipc t2, %pcrel_hi(.LCPI6_0)
+; CHECK-CF-RV32-LARGE-NEXT: lw t2, %pcrel_lo(.Lpcrel_hi8)(t2)
+; CHECK-CF-RV32-LARGE-NEXT: sw t0, 0(sp)
+; CHECK-CF-RV32-LARGE-NEXT: sw t1, 4(sp)
+; CHECK-CF-RV32-LARGE-NEXT: sw t3, 8(sp)
+; CHECK-CF-RV32-LARGE-NEXT: sw t4, 12(sp)
+; CHECK-CF-RV32-LARGE-NEXT: jalr t2
+; CHECK-CF-RV32-LARGE-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; CHECK-CF-RV32-LARGE-NEXT: addi sp, sp, 32
+; CHECK-CF-RV32-LARGE-NEXT: ret
+;
+; CHECK-CF-RV64-LARGE-LABEL: caller_args:
+; CHECK-CF-RV64-LARGE: # %bb.0: # %entry
+; CHECK-CF-RV64-LARGE-NEXT: lpad 0
+; CHECK-CF-RV64-LARGE-NEXT: addi sp, sp, -64
+; CHECK-CF-RV64-LARGE-NEXT: sd ra, 56(sp) # 8-byte Folded Spill
+; CHECK-CF-RV64-LARGE-NEXT: ld t0, 64(sp)
+; CHECK-CF-RV64-LARGE-NEXT: ld t1, 72(sp)
+; CHECK-CF-RV64-LARGE-NEXT: ld t3, 80(sp)
+; CHECK-CF-RV64-LARGE-NEXT: ld t4, 88(sp)
+; CHECK-CF-RV64-LARGE-NEXT: ld t2, 96(sp)
+; CHECK-CF-RV64-LARGE-NEXT: ld t5, 104(sp)
+; CHECK-CF-RV64-LARGE-NEXT: sd t2, 32(sp)
+; CHECK-CF-RV64-LARGE-NEXT: sd t5, 40(sp)
+; CHECK-CF-RV64-LARGE-NEXT: .Lpcrel_hi8:
+; CHECK-CF-RV64-LARGE-NEXT: auipc t2, %pcrel_hi(.LCPI6_0)
+; CHECK-CF-RV64-LARGE-NEXT: ld t2, %pcrel_lo(.Lpcrel_hi8)(t2)
+; CHECK-CF-RV64-LARGE-NEXT: sd t0, 0(sp)
+; CHECK-CF-RV64-LARGE-NEXT: sd t1, 8(sp)
+; CHECK-CF-RV64-LARGE-NEXT: sd t3, 16(sp)
+; CHECK-CF-RV64-LARGE-NEXT: sd t4, 24(sp)
+; CHECK-CF-RV64-LARGE-NEXT: jalr t2
+; CHECK-CF-RV64-LARGE-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
+; CHECK-CF-RV64-LARGE-NEXT: addi sp, sp, 64
+; CHECK-CF-RV64-LARGE-NEXT: ret
entry:
%r = tail call i32 @callee_args(i32 %a, i32 %b, i32 %c, i32 %dd, i32 %e, i32 %ff, i32 %g, i32 %h, i32 %i, i32 %j, i32 %k, i32 %l, i32 %m, i32 %n)
ret i32 %r
@@ -263,23 +574,59 @@ define void @caller_indirect_args() nounwind {
; CHECK-NEXT: addi sp, sp, 32
; CHECK-NEXT: ret
;
-; CHECK-LARGE-ZICFILP-LABEL: caller_indirect_args:
-; CHECK-LARGE-ZICFILP: # %bb.0: # %entry
-; CHECK-LARGE-ZICFILP-NEXT: addi sp, sp, -32
-; CHECK-LARGE-ZICFILP-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
-; CHECK-LARGE-ZICFILP-NEXT: lui a1, 262128
-; CHECK-LARGE-ZICFILP-NEXT: .Lpcrel_hi9:
-; CHECK-LARGE-ZICFILP-NEXT: auipc a0, %pcrel_hi(.LCPI7_0)
-; CHECK-LARGE-ZICFILP-NEXT: lw a2, %pcrel_lo(.Lpcrel_hi9)(a0)
-; CHECK-LARGE-ZICFILP-NEXT: mv a0, sp
-; CHECK-LARGE-ZICFILP-NEXT: sw zero, 0(sp)
-; CHECK-LARGE-ZICFILP-NEXT: sw zero, 4(sp)
-; CHECK-LARGE-ZICFILP-NEXT: sw zero, 8(sp)
-; CHECK-LARGE-ZICFILP-NEXT: sw a1, 12(sp)
-; CHECK-LARGE-ZICFILP-NEXT: jalr a2
-; CHECK-LARGE-ZICFILP-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; CHECK-LARGE-ZICFILP-NEXT: addi sp, sp, 32
-; CHECK-LARGE-ZICFILP-NEXT: ret
+; CHECK-CF-RV32-LABEL: caller_indirect_args:
+; CHECK-CF-RV32: # %bb.0: # %entry
+; CHECK-CF-RV32-NEXT: lpad 0
+; CHECK-CF-RV32-NEXT: addi sp, sp, -32
+; CHECK-CF-RV32-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; CHECK-CF-RV32-NEXT: lui a1, 262128
+; CHECK-CF-RV32-NEXT: mv a0, sp
+; CHECK-CF-RV32-NEXT: sw zero, 0(sp)
+; CHECK-CF-RV32-NEXT: sw zero, 4(sp)
+; CHECK-CF-RV32-NEXT: sw zero, 8(sp)
+; CHECK-CF-RV32-NEXT: sw a1, 12(sp)
+; CHECK-CF-RV32-NEXT: call callee_indirect_args
+; CHECK-CF-RV32-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; CHECK-CF-RV32-NEXT: addi sp, sp, 32
+; CHECK-CF-RV32-NEXT: ret
+;
+; CHECK-CF-RV64-LABEL: caller_indirect_args:
+; CHECK-CF-RV64: # %bb.0: # %entry
+; CHECK-CF-RV64-NEXT: lpad 0
+; CHECK-CF-RV64-NEXT: lui a1, 16383
+; CHECK-CF-RV64-NEXT: slli a1, a1, 36
+; CHECK-CF-RV64-NEXT: li a0, 0
+; CHECK-CF-RV64-NEXT: tail callee_indirect_args
+;
+; CHECK-CF-RV32-LARGE-LABEL: caller_indirect_args:
+; CHECK-CF-RV32-LARGE: # %bb.0: # %entry
+; CHECK-CF-RV32-LARGE-NEXT: lpad 0
+; CHECK-CF-RV32-LARGE-NEXT: addi sp, sp, -32
+; CHECK-CF-RV32-LARGE-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; CHECK-CF-RV32-LARGE-NEXT: lui a1, 262128
+; CHECK-CF-RV32-LARGE-NEXT: .Lpcrel_hi9:
+; CHECK-CF-RV32-LARGE-NEXT: auipc a0, %pcrel_hi(.LCPI7_0)
+; CHECK-CF-RV32-LARGE-NEXT: lw t2, %pcrel_lo(.Lpcrel_hi9)(a0)
+; CHECK-CF-RV32-LARGE-NEXT: mv a0, sp
+; CHECK-CF-RV32-LARGE-NEXT: sw zero, 0(sp)
+; CHECK-CF-RV32-LARGE-NEXT: sw zero, 4(sp)
+; CHECK-CF-RV32-LARGE-NEXT: sw zero, 8(sp)
+; CHECK-CF-RV32-LARGE-NEXT: sw a1, 12(sp)
+; CHECK-CF-RV32-LARGE-NEXT: jalr t2
+; CHECK-CF-RV32-LARGE-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; CHECK-CF-RV32-LARGE-NEXT: addi sp, sp, 32
+; CHECK-CF-RV32-LARGE-NEXT: ret
+;
+; CHECK-CF-RV64-LARGE-LABEL: caller_indirect_args:
+; CHECK-CF-RV64-LARGE: # %bb.0: # %entry
+; CHECK-CF-RV64-LARGE-NEXT: lpad 0
+; CHECK-CF-RV64-LARGE-NEXT: .Lpcrel_hi9:
+; CHECK-CF-RV64-LARGE-NEXT: auipc a0, %pcrel_hi(.LCPI7_0)
+; CHECK-CF-RV64-LARGE-NEXT: ld t2, %pcrel_lo(.Lpcrel_hi9)(a0)
+; CHECK-CF-RV64-LARGE-NEXT: lui a1, 16383
+; CHECK-CF-RV64-LARGE-NEXT: slli a1, a1, 36
+; CHECK-CF-RV64-LARGE-NEXT: li a0, 0
+; CHECK-CF-RV64-LARGE-NEXT: jr t2
entry:
%call = tail call i32 @callee_indirect_args(fp128 0xL00000000000000003FFF000000000000)
ret void
@@ -292,12 +639,31 @@ define void @caller_weak() nounwind {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: tail callee_weak
;
-; CHECK-LARGE-ZICFILP-LABEL: caller_weak:
-; CHECK-LARGE-ZICFILP: # %bb.0: # %entry
-; CHECK-LARGE-ZICFILP-NEXT: .Lpcrel_hi10:
-; CHECK-LARGE-ZICFILP-NEXT: auipc a0, %pcrel_hi(.LCPI8_0)
-; CHECK-LARGE-ZICFILP-NEXT: lw t1, %pcrel_lo(.Lpcrel_hi10)(a0)
-; CHECK-LARGE-ZICFILP-NEXT: jr t1
+; CHECK-CF-RV32-LABEL: caller_weak:
+; CHECK-CF-RV32: # %bb.0: # %entry
+; CHECK-CF-RV32-NEXT: lpad 0
+; CHECK-CF-RV32-NEXT: tail callee_weak
+;
+; CHECK-CF-RV64-LABEL: caller_weak:
+; CHECK-CF-RV64: # %bb.0: # %entry
+; CHECK-CF-RV64-NEXT: lpad 0
+; CHECK-CF-RV64-NEXT: tail callee_weak
+;
+; CHECK-CF-RV32-LARGE-LABEL: caller_weak:
+; CHECK-CF-RV32-LARGE: # %bb.0: # %entry
+; CHECK-CF-RV32-LARGE-NEXT: lpad 0
+; CHECK-CF-RV32-LARGE-NEXT: .Lpcrel_hi10:
+; CHECK-CF-RV32-LARGE-NEXT: auipc a0, %pcrel_hi(.LCPI8_0)
+; CHECK-CF-RV32-LARGE-NEXT: lw t2, %pcrel_lo(.Lpcrel_hi10)(a0)
+; CHECK-CF-RV32-LARGE-NEXT: jr t2
+;
+; CHECK-CF-RV64-LARGE-LABEL: caller_weak:
+; CHECK-CF-RV64-LARGE: # %bb.0: # %entry
+; CHECK-CF-RV64-LARGE-NEXT: lpad 0
+; CHECK-CF-RV64-LARGE-NEXT: .Lpcrel_hi10:
+; CHECK-CF-RV64-LARGE-NEXT: auipc a0, %pcrel_hi(.LCPI8_0)
+; CHECK-CF-RV64-LARGE-NEXT: ld t2, %pcrel_lo(.Lpcrel_hi10)(a0)
+; CHECK-CF-RV64-LARGE-NEXT: jr t2
entry:
tail call void @callee_weak()
ret void
@@ -347,47 +713,167 @@ define void @caller_irq() nounwind "interrupt"="machine" {
; CHECK-NEXT: addi sp, sp, 64
; CHECK-NEXT: mret
;
-; CHECK-LARGE-ZICFILP-LABEL: caller_irq:
-; CHECK-LARGE-ZICFILP: # %bb.0: # %entry
-; CHECK-LARGE-ZICFILP-NEXT: addi sp, sp, -64
-; CHECK-LARGE-ZICFILP-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
-; CHECK-LARGE-ZICFILP-NEXT: sw t0, 56(sp) # 4-byte Folded Spill
-; CHECK-LARGE-ZICFILP-NEXT: sw t1, 52(sp) # 4-byte Folded Spill
-; CHECK-LARGE-ZICFILP-NEXT: sw t2, 48(sp) # 4-byte Folded Spill
-; CHECK-LARGE-ZICFILP-NEXT: sw a0, 44(sp) # 4-byte Folded Spill
-; CHECK-LARGE-ZICFILP-NEXT: sw a1, 40(sp) # 4-byte Folded Spill
-; CHECK-LARGE-ZICFILP-NEXT: sw a2, 36(sp) # 4-byte Folded Spill
-; CHECK-LARGE-ZICFILP-NEXT: sw a3, 32(sp) # 4-byte Folded Spill
-; CHECK-LARGE-ZICFILP-NEXT: sw a4, 28(sp) # 4-byte Folded Spill
-; CHECK-LARGE-ZICFILP-NEXT: sw a5, 24(sp) # 4-byte Folded Spill
-; CHECK-LARGE-ZICFILP-NEXT: sw a6, 20(sp) # 4-byte Folded Spill
-; CHECK-LARGE-ZICFILP-NEXT: sw a7, 16(sp) # 4-byte Folded Spill
-; CHECK-LARGE-ZICFILP-NEXT: sw t3, 12(sp) # 4-byte Folded Spill
-; CHECK-LARGE-ZICFILP-NEXT: sw t4, 8(sp) # 4-byte Folded Spill
-; CHECK-LARGE-ZICFILP-NEXT: sw t5, 4(sp) # 4-byte Folded Spill
-; CHECK-LARGE-ZICFILP-NEXT: sw t6, 0(sp) # 4-byte Folded Spill
-; CHECK-LARGE-ZICFILP-NEXT: .Lpcrel_hi11:
-; CHECK-LARGE-ZICFILP-NEXT: auipc a0, %pcrel_hi(.LCPI9_0)
-; CHECK-LARGE-ZICFILP-NEXT: lw a0, %pcrel_lo(.Lpcrel_hi11)(a0)
-; CHECK-LARGE-ZICFILP-NEXT: jalr a0
-; CHECK-LARGE-ZICFILP-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
-; CHECK-LARGE-ZICFILP-NEXT: lw t0, 56(sp) # 4-byte Folded Reload
-; CHECK-LARGE-ZICFILP-NEXT: lw t1, 52(sp) # 4-byte Folded Reload
-; CHECK-LARGE-ZICFILP-NEXT: lw t2, 48(sp) # 4-byte Folded Reload
-; CHECK-LARGE-ZICFILP-NEXT: lw a0, 44(sp) # 4-byte Folded Reload
-; CHECK-LARGE-ZICFILP-NEXT: lw a1, 40(sp) # 4-byte Folded Reload
-; CHECK-LARGE-ZICFILP-NEXT: lw a2, 36(sp) # 4-byte Folded Reload
-; CHECK-LARGE-ZICFILP-NEXT: lw a3, 32(sp) # 4-byte Folded Reload
-; CHECK-LARGE-ZICFILP-NEXT: lw a4, 28(sp) # 4-byte Folded Reload
-; CHECK-LARGE-ZICFILP-NEXT: lw a5, 24(sp) # 4-byte Folded Reload
-; CHECK-LARGE-ZICFILP-NEXT: lw a6, 20(sp) # 4-byte Folded Reload
-; CHECK-LARGE-ZICFILP-NEXT: lw a7, 16(sp) # 4-byte Folded Reload
-; CHECK-LARGE-ZICFILP-NEXT: lw t3, 12(sp) # 4-byte Folded Reload
-; CHECK-LARGE-ZICFILP-NEXT: lw t4, 8(sp) # 4-byte Folded Reload
-; CHECK-LARGE-ZICFILP-NEXT: lw t5, 4(sp) # 4-byte Folded Reload
-; CHECK-LARGE-ZICFILP-NEXT: lw t6, 0(sp) # 4-byte Folded Reload
-; CHECK-LARGE-ZICFILP-NEXT: addi sp, sp, 64
-; CHECK-LARGE-ZICFILP-NEXT: mret
+; CHECK-CF-RV32-LABEL: caller_irq:
+; CHECK-CF-RV32: # %bb.0: # %entry
+; CHECK-CF-RV32-NEXT: addi sp, sp, -64
+; CHECK-CF-RV32-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
+; CHECK-CF-RV32-NEXT: sw t0, 56(sp) # 4-byte Folded Spill
+; CHECK-CF-RV32-NEXT: sw t1, 52(sp) # 4-byte Folded Spill
+; CHECK-CF-RV32-NEXT: sw t2, 48(sp) # 4-byte Folded Spill
+; CHECK-CF-RV32-NEXT: sw a0, 44(sp) # 4-byte Folded Spill
+; CHECK-CF-RV32-NEXT: sw a1, 40(sp) # 4-byte Folded Spill
+; CHECK-CF-RV32-NEXT: sw a2, 36(sp) # 4-byte Folded Spill
+; CHECK-CF-RV32-NEXT: sw a3, 32(sp) # 4-byte Folded Spill
+; CHECK-CF-RV32-NEXT: sw a4, 28(sp) # 4-byte Folded Spill
+; CHECK-CF-RV32-NEXT: sw a5, 24(sp) # 4-byte Folded Spill
+; CHECK-CF-RV32-NEXT: sw a6, 20(sp) # 4-byte Folded Spill
+; CHECK-CF-RV32-NEXT: sw a7, 16(sp) # 4-byte Folded Spill
+; CHECK-CF-RV32-NEXT: sw t3, 12(sp) # 4-byte Folded Spill
+; CHECK-CF-RV32-NEXT: sw t4, 8(sp) # 4-byte Folded Spill
+; CHECK-CF-RV32-NEXT: sw t5, 4(sp) # 4-byte Folded Spill
+; CHECK-CF-RV32-NEXT: sw t6, 0(sp) # 4-byte Folded Spill
+; CHECK-CF-RV32-NEXT: call callee_irq
+; CHECK-CF-RV32-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
+; CHECK-CF-RV32-NEXT: lw t0, 56(sp) # 4-byte Folded Reload
+; CHECK-CF-RV32-NEXT: lw t1, 52(sp) # 4-byte Folded Reload
+; CHECK-CF-RV32-NEXT: lw t2, 48(sp) # 4-byte Folded Reload
+; CHECK-CF-RV32-NEXT: lw a0, 44(sp) # 4-byte Folded Reload
+; CHECK-CF-RV32-NEXT: lw a1, 40(sp) # 4-byte Folded Reload
+; CHECK-CF-RV32-NEXT: lw a2, 36(sp) # 4-byte Folded Reload
+; CHECK-CF-RV32-NEXT: lw a3, 32(sp) # 4-byte Folded Reload
+; CHECK-CF-RV32-NEXT: lw a4, 28(sp) # 4-byte Folded Reload
+; CHECK-CF-RV32-NEXT: lw a5, 24(sp) # 4-byte Folded Reload
+; CHECK-CF-RV32-NEXT: lw a6, 20(sp) # 4-byte Folded Reload
+; CHECK-CF-RV32-NEXT: lw a7, 16(sp) # 4-byte Folded Reload
+; CHECK-CF-RV32-NEXT: lw t3, 12(sp) # 4-byte Folded Reload
+; CHECK-CF-RV32-NEXT: lw t4, 8(sp) # 4-byte Folded Reload
+; CHECK-CF-RV32-NEXT: lw t5, 4(sp) # 4-byte Folded Reload
+; CHECK-CF-RV32-NEXT: lw t6, 0(sp) # 4-byte Folded Reload
+; CHECK-CF-RV32-NEXT: addi sp, sp, 64
+; CHECK-CF-RV32-NEXT: mret
+;
+; CHECK-CF-RV64-LABEL: caller_irq:
+; CHECK-CF-RV64: # %bb.0: # %entry
+; CHECK-CF-RV64-NEXT: addi sp, sp, -128
+; CHECK-CF-RV64-NEXT: sd ra, 120(sp) # 8-byte Folded Spill
+; CHECK-CF-RV64-NEXT: sd t0, 112(sp) # 8-byte Folded Spill
+; CHECK-CF-RV64-NEXT: sd t1, 104(sp) # 8-byte Folded Spill
+; CHECK-CF-RV64-NEXT: sd t2, 96(sp) # 8-byte Folded Spill
+; CHECK-CF-RV64-NEXT: sd a0, 88(sp) # 8-byte Folded Spill
+; CHECK-CF-RV64-NEXT: sd a1, 80(sp) # 8-byte Folded Spill
+; CHECK-CF-RV64-NEXT: sd a2, 72(sp) # 8-byte Folded Spill
+; CHECK-CF-RV64-NEXT: sd a3, 64(sp) # 8-byte Folded Spill
+; CHECK-CF-RV64-NEXT: sd a4, 56(sp) # 8-byte Folded Spill
+; CHECK-CF-RV64-NEXT: sd a5, 48(sp) # 8-byte Folded Spill
+; CHECK-CF-RV64-NEXT: sd a6, 40(sp) # 8-byte Folded Spill
+; CHECK-CF-RV64-NEXT: sd a7, 32(sp) # 8-byte Folded Spill
+; CHECK-CF-RV64-NEXT: sd t3, 24(sp) # 8-byte Folded Spill
+; CHECK-CF-RV64-NEXT: sd t4, 16(sp) # 8-byte Folded Spill
+; CHECK-CF-RV64-NEXT: sd t5, 8(sp) # 8-byte Folded Spill
+; CHECK-CF-RV64-NEXT: sd t6, 0(sp) # 8-byte Folded Spill
+; CHECK-CF-RV64-NEXT: call callee_irq
+; CHECK-CF-RV64-NEXT: ld ra, 120(sp) # 8-byte Folded Reload
+; CHECK-CF-RV64-NEXT: ld t0, 112(sp) # 8-byte Folded Reload
+; CHECK-CF-RV64-NEXT: ld t1, 104(sp) # 8-byte Folded Reload
+; CHECK-CF-RV64-NEXT: ld t2, 96(sp) # 8-byte Folded Reload
+; CHECK-CF-RV64-NEXT: ld a0, 88(sp) # 8-byte Folded Reload
+; CHECK-CF-RV64-NEXT: ld a1, 80(sp) # 8-byte Folded Reload
+; CHECK-CF-RV64-NEXT: ld a2, 72(sp) # 8-byte Folded Reload
+; CHECK-CF-RV64-NEXT: ld a3, 64(sp) # 8-byte Folded Reload
+; CHECK-CF-RV64-NEXT: ld a4, 56(sp) # 8-byte Folded Reload
+; CHECK-CF-RV64-NEXT: ld a5, 48(sp) # 8-byte Folded Reload
+; CHECK-CF-RV64-NEXT: ld a6, 40(sp) # 8-byte Folded Reload
+; CHECK-CF-RV64-NEXT: ld a7, 32(sp) # 8-byte Folded Reload
+; CHECK-CF-RV64-NEXT: ld t3, 24(sp) # 8-byte Folded Reload
+; CHECK-CF-RV64-NEXT: ld t4, 16(sp) # 8-byte Folded Reload
+; CHECK-CF-RV64-NEXT: ld t5, 8(sp) # 8-byte Folded Reload
+; CHECK-CF-RV64-NEXT: ld t6, 0(sp) # 8-byte Folded Reload
+; CHECK-CF-RV64-NEXT: addi sp, sp, 128
+; CHECK-CF-RV64-NEXT: mret
+;
+; CHECK-CF-RV32-LARGE-LABEL: caller_irq:
+; CHECK-CF-RV32-LARGE: # %bb.0: # %entry
+; CHECK-CF-RV32-LARGE-NEXT: addi sp, sp, -64
+; CHECK-CF-RV32-LARGE-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
+; CHECK-CF-RV32-LARGE-NEXT: sw t0, 56(sp) # 4-byte Folded Spill
+; CHECK-CF-RV32-LARGE-NEXT: sw t1, 52(sp) # 4-byte Folded Spill
+; CHECK-CF-RV32-LARGE-NEXT: sw t2, 48(sp) # 4-byte Folded Spill
+; CHECK-CF-RV32-LARGE-NEXT: sw a0, 44(sp) # 4-byte Folded Spill
+; CHECK-CF-RV32-LARGE-NEXT: sw a1, 40(sp) # 4-byte Folded Spill
+; CHECK-CF-RV32-LARGE-NEXT: sw a2, 36(sp) # 4-byte Folded Spill
+; CHECK-CF-RV32-LARGE-NEXT: sw a3, 32(sp) # 4-byte Folded Spill
+; CHECK-CF-RV32-LARGE-NEXT: sw a4, 28(sp) # 4-byte Folded Spill
+; CHECK-CF-RV32-LARGE-NEXT: sw a5, 24(sp) # 4-byte Folded Spill
+; CHECK-CF-RV32-LARGE-NEXT: sw a6, 20(sp) # 4-byte Folded Spill
+; CHECK-CF-RV32-LARGE-NEXT: sw a7, 16(sp) # 4-byte Folded Spill
+; CHECK-CF-RV32-LARGE-NEXT: sw t3, 12(sp) # 4-byte Folded Spill
+; CHECK-CF-RV32-LARGE-NEXT: sw t4, 8(sp) # 4-byte Folded Spill
+; CHECK-CF-RV32-LARGE-NEXT: sw t5, 4(sp) # 4-byte Folded Spill
+; CHECK-CF-RV32-LARGE-NEXT: sw t6, 0(sp) # 4-byte Folded Spill
+; CHECK-CF-RV32-LARGE-NEXT: .Lpcrel_hi11:
+; CHECK-CF-RV32-LARGE-NEXT: auipc a0, %pcrel_hi(.LCPI9_0)
+; CHECK-CF-RV32-LARGE-NEXT: lw t2, %pcrel_lo(.Lpcrel_hi11)(a0)
+; CHECK-CF-RV32-LARGE-NEXT: jalr t2
+; CHECK-CF-RV32-LARGE-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
+; CHECK-CF-RV32-LARGE-NEXT: lw t0, 56(sp) # 4-byte Folded Reload
+; CHECK-CF-RV32-LARGE-NEXT: lw t1, 52(sp) # 4-byte Folded Reload
+; CHECK-CF-RV32-LARGE-NEXT: lw t2, 48(sp) # 4-byte Folded Reload
+; CHECK-CF-RV32-LARGE-NEXT: lw a0, 44(sp) # 4-byte Folded Reload
+; CHECK-CF-RV32-LARGE-NEXT: lw a1, 40(sp) # 4-byte Folded Reload
+; CHECK-CF-RV32-LARGE-NEXT: lw a2, 36(sp) # 4-byte Folded Reload
+; CHECK-CF-RV32-LARGE-NEXT: lw a3, 32(sp) # 4-byte Folded Reload
+; CHECK-CF-RV32-LARGE-NEXT: lw a4, 28(sp) # 4-byte Folded Reload
+; CHECK-CF-RV32-LARGE-NEXT: lw a5, 24(sp) # 4-byte Folded Reload
+; CHECK-CF-RV32-LARGE-NEXT: lw a6, 20(sp) # 4-byte Folded Reload
+; CHECK-CF-RV32-LARGE-NEXT: lw a7, 16(sp) # 4-byte Folded Reload
+; CHECK-CF-RV32-LARGE-NEXT: lw t3, 12(sp) # 4-byte Folded Reload
+; CHECK-CF-RV32-LARGE-NEXT: lw t4, 8(sp) # 4-byte Folded Reload
+; CHECK-CF-RV32-LARGE-NEXT: lw t5, 4(sp) # 4-byte Folded Reload
+; CHECK-CF-RV32-LARGE-NEXT: lw t6, 0(sp) # 4-byte Folded Reload
+; CHECK-CF-RV32-LARGE-NEXT: addi sp, sp, 64
+; CHECK-CF-RV32-LARGE-NEXT: mret
+;
+; CHECK-CF-RV64-LARGE-LABEL: caller_irq:
+; CHECK-CF-RV64-LARGE: # %bb.0: # %entry
+; CHECK-CF-RV64-LARGE-NEXT: addi sp, sp, -128
+; CHECK-CF-RV64-LARGE-NEXT: sd ra, 120(sp) # 8-byte Folded Spill
+; CHECK-CF-RV64-LARGE-NEXT: sd t0, 112(sp) # 8-byte Folded Spill
+; CHECK-CF-RV64-LARGE-NEXT: sd t1, 104(sp) # 8-byte Folded Spill
+; CHECK-CF-RV64-LARGE-NEXT: sd t2, 96(sp) # 8-byte Folded Spill
+; CHECK-CF-RV64-LARGE-NEXT: sd a0, 88(sp) # 8-byte Folded Spill
+; CHECK-CF-RV64-LARGE-NEXT: sd a1, 80(sp) # 8-byte Folded Spill
+; CHECK-CF-RV64-LARGE-NEXT: sd a2, 72(sp) # 8-byte Folded Spill
+; CHECK-CF-RV64-LARGE-NEXT: sd a3, 64(sp) # 8-byte Folded Spill
+; CHECK-CF-RV64-LARGE-NEXT: sd a4, 56(sp) # 8-byte Folded Spill
+; CHECK-CF-RV64-LARGE-NEXT: sd a5, 48(sp) # 8-byte Folded Spill
+; CHECK-CF-RV64-LARGE-NEXT: sd a6, 40(sp) # 8-byte Folded Spill
+; CHECK-CF-RV64-LARGE-NEXT: sd a7, 32(sp) # 8-byte Folded Spill
+; CHECK-CF-RV64-LARGE-NEXT: sd t3, 24(sp) # 8-byte Folded Spill
+; CHECK-CF-RV64-LARGE-NEXT: sd t4, 16(sp) # 8-byte Folded Spill
+; CHECK-CF-RV64-LARGE-NEXT: sd t5, 8(sp) # 8-byte Folded Spill
+; CHECK-CF-RV64-LARGE-NEXT: sd t6, 0(sp) # 8-byte Folded Spill
+; CHECK-CF-RV64-LARGE-NEXT: .Lpcrel_hi11:
+; CHECK-CF-RV64-LARGE-NEXT: auipc a0, %pcrel_hi(.LCPI9_0)
+; CHECK-CF-RV64-LARGE-NEXT: ld t2, %pcrel_lo(.Lpcrel_hi11)(a0)
+; CHECK-CF-RV64-LARGE-NEXT: jalr t2
+; CHECK-CF-RV64-LARGE-NEXT: ld ra, 120(sp) # 8-byte Folded Reload
+; CHECK-CF-RV64-LARGE-NEXT: ld t0, 112(sp) # 8-byte Folded Reload
+; CHECK-CF-RV64-LARGE-NEXT: ld t1, 104(sp) # 8-byte Folded Reload
+; CHECK-CF-RV64-LARGE-NEXT: ld t2, 96(sp) # 8-byte Folded Reload
+; CHECK-CF-RV64-LARGE-NEXT: ld a0, 88(sp) # 8-byte Folded Reload
+; CHECK-CF-RV64-LARGE-NEXT: ld a1, 80(sp) # 8-byte Folded Reload
+; CHECK-CF-RV64-LARGE-NEXT: ld a2, 72(sp) # 8-byte Folded Reload
+; CHECK-CF-RV64-LARGE-NEXT: ld a3, 64(sp) # 8-byte Folded Reload
+; CHECK-CF-RV64-LARGE-NEXT: ld a4, 56(sp) # 8-byte Folded Reload
+; CHECK-CF-RV64-LARGE-NEXT: ld a5, 48(sp) # 8-byte Folded Reload
+; CHECK-CF-RV64-LARGE-NEXT: ld a6, 40(sp) # 8-byte Folded Reload
+; CHECK-CF-RV64-LARGE-NEXT: ld a7, 32(sp) # 8-byte Folded Reload
+; CHECK-CF-RV64-LARGE-NEXT: ld t3, 24(sp) # 8-byte Folded Reload
+; CHECK-CF-RV64-LARGE-NEXT: ld t4, 16(sp) # 8-byte Folded Reload
+; CHECK-CF-RV64-LARGE-NEXT: ld t5, 8(sp) # 8-byte Folded Reload
+; CHECK-CF-RV64-LARGE-NEXT: ld t6, 0(sp) # 8-byte Folded Reload
+; CHECK-CF-RV64-LARGE-NEXT: addi sp, sp, 128
+; CHECK-CF-RV64-LARGE-NEXT: mret
entry:
tail call void @callee_irq()
ret void
@@ -410,20 +896,63 @@ define i32 @caller_byval() nounwind {
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
;
-; CHECK-LARGE-ZICFILP-LABEL: caller_byval:
-; CHECK-LARGE-ZICFILP: # %bb.0: # %entry
-; CHECK-LARGE-ZICFILP-NEXT: addi sp, sp, -16
-; CHECK-LARGE-ZICFILP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; CHECK-LARGE-ZICFILP-NEXT: lw a0, 8(sp)
-; CHECK-LARGE-ZICFILP-NEXT: sw a0, 4(sp)
-; CHECK-LARGE-ZICFILP-NEXT: .Lpcrel_hi12:
-; CHECK-LARGE-ZICFILP-NEXT: auipc a0, %pcrel_hi(.LCPI10_0)
-; CHECK-LARGE-ZICFILP-NEXT: lw a1, %pcrel_lo(.Lpcrel_hi12)(a0)
-; CHECK-LARGE-ZICFILP-NEXT: addi a0, sp, 4
-; CHECK-LARGE-ZICFILP-NEXT: jalr a1
-; CHECK-LARGE-ZICFILP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; CHECK-LARGE-ZICFILP-NEXT: addi sp, sp, 16
-; CHECK-LARGE-ZICFILP-NEXT: ret
+; CHECK-CF-RV32-LABEL: caller_byval:
+; CHECK-CF-RV32: # %bb.0: # %entry
+; CHECK-CF-RV32-NEXT: lpad 0
+; CHECK-CF-RV32-NEXT: addi sp, sp, -16
+; CHECK-CF-RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; CHECK-CF-RV32-NEXT: lw a0, 8(sp)
+; CHECK-CF-RV32-NEXT: sw a0, 4(sp)
+; CHECK-CF-RV32-NEXT: addi a0, sp, 4
+; CHECK-CF-RV32-NEXT: call callee_byval
+; CHECK-CF-RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; CHECK-CF-RV32-NEXT: addi sp, sp, 16
+; CHECK-CF-RV32-NEXT: ret
+;
+; CHECK-CF-RV64-LABEL: caller_byval:
+; CHECK-CF-RV64: # %bb.0: # %entry
+; CHECK-CF-RV64-NEXT: lpad 0
+; CHECK-CF-RV64-NEXT: addi sp, sp, -32
+; CHECK-CF-RV64-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; CHECK-CF-RV64-NEXT: ld a0, 16(sp)
+; CHECK-CF-RV64-NEXT: sd a0, 8(sp)
+; CHECK-CF-RV64-NEXT: addi a0, sp, 8
+; CHECK-CF-RV64-NEXT: call callee_byval
+; CHECK-CF-RV64-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; CHECK-CF-RV64-NEXT: addi sp, sp, 32
+; CHECK-CF-RV64-NEXT: ret
+;
+; CHECK-CF-RV32-LARGE-LABEL: caller_byval:
+; CHECK-CF-RV32-LARGE: # %bb.0: # %entry
+; CHECK-CF-RV32-LARGE-NEXT: lpad 0
+; CHECK-CF-RV32-LARGE-NEXT: addi sp, sp, -16
+; CHECK-CF-RV32-LARGE-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; CHECK-CF-RV32-LARGE-NEXT: lw a0, 8(sp)
+; CHECK-CF-RV32-LARGE-NEXT: sw a0, 4(sp)
+; CHECK-CF-RV32-LARGE-NEXT: .Lpcrel_hi12:
+; CHECK-CF-RV32-LARGE-NEXT: auipc a0, %pcrel_hi(.LCPI10_0)
+; CHECK-CF-RV32-LARGE-NEXT: lw t2, %pcrel_lo(.Lpcrel_hi12)(a0)
+; CHECK-CF-RV32-LARGE-NEXT: addi a0, sp, 4
+; CHECK-CF-RV32-LARGE-NEXT: jalr t2
+; CHECK-CF-RV32-LARGE-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; CHECK-CF-RV32-LARGE-NEXT: addi sp, sp, 16
+; CHECK-CF-RV32-LARGE-NEXT: ret
+;
+; CHECK-CF-RV64-LARGE-LABEL: caller_byval:
+; CHECK-CF-RV64-LARGE: # %bb.0: # %entry
+; CHECK-CF-RV64-LARGE-NEXT: lpad 0
+; CHECK-CF-RV64-LARGE-NEXT: addi sp, sp, -32
+; CHECK-CF-RV64-LARGE-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; CHECK-CF-RV64-LARGE-NEXT: ld a0, 16(sp)
+; CHECK-CF-RV64-LARGE-NEXT: sd a0, 8(sp)
+; CHECK-CF-RV64-LARGE-NEXT: .Lpcrel_hi12:
+; CHECK-CF-RV64-LARGE-NEXT: auipc a0, %pcrel_hi(.LCPI10_0)
+; CHECK-CF-RV64-LARGE-NEXT: ld t2, %pcrel_lo(.Lpcrel_hi12)(a0)
+; CHECK-CF-RV64-LARGE-NEXT: addi a0, sp, 8
+; CHECK-CF-RV64-LARGE-NEXT: jalr t2
+; CHECK-CF-RV64-LARGE-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; CHECK-CF-RV64-LARGE-NEXT: addi sp, sp, 32
+; CHECK-CF-RV64-LARGE-NEXT: ret
entry:
%a = alloca ptr
%r = tail call i32 @callee_byval(ptr byval(ptr) %a)
@@ -447,20 +976,61 @@ define void @caller_nostruct() nounwind {
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
;
-; CHECK-LARGE-ZICFILP-LABEL: caller_nostruct:
-; CHECK-LARGE-ZICFILP: # %bb.0: # %entry
-; CHECK-LARGE-ZICFILP-NEXT: addi sp, sp, -16
-; CHECK-LARGE-ZICFILP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; CHECK-LARGE-ZICFILP-NEXT: .Lpcrel_hi13:
-; CHECK-LARGE-ZICFILP-NEXT: auipc a0, %pcrel_hi(.LCPI11_0)
-; CHECK-LARGE-ZICFILP-NEXT: .Lpcrel_hi14:
-; CHECK-LARGE-ZICFILP-NEXT: auipc a1, %pcrel_hi(.LCPI11_1)
-; CHECK-LARGE-ZICFILP-NEXT: lw a0, %pcrel_lo(.Lpcrel_hi13)(a0)
-; CHECK-LARGE-ZICFILP-NEXT: lw a1, %pcrel_lo(.Lpcrel_hi14)(a1)
-; CHECK-LARGE-ZICFILP-NEXT: jalr a1
-; CHECK-LARGE-ZICFILP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; CHECK-LARGE-ZICFILP-NEXT: addi sp, sp, 16
-; CHECK-LARGE-ZICFILP-NEXT: ret
+; CHECK-CF-RV32-LABEL: caller_nostruct:
+; CHECK-CF-RV32: # %bb.0: # %entry
+; CHECK-CF-RV32-NEXT: lpad 0
+; CHECK-CF-RV32-NEXT: addi sp, sp, -16
+; CHECK-CF-RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; CHECK-CF-RV32-NEXT: lui a0, %hi(a)
+; CHECK-CF-RV32-NEXT: addi a0, a0, %lo(a)
+; CHECK-CF-RV32-NEXT: call callee_struct
+; CHECK-CF-RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; CHECK-CF-RV32-NEXT: addi sp, sp, 16
+; CHECK-CF-RV32-NEXT: ret
+;
+; CHECK-CF-RV64-LABEL: caller_nostruct:
+; CHECK-CF-RV64: # %bb.0: # %entry
+; CHECK-CF-RV64-NEXT: lpad 0
+; CHECK-CF-RV64-NEXT: addi sp, sp, -16
+; CHECK-CF-RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; CHECK-CF-RV64-NEXT: lui a0, %hi(a)
+; CHECK-CF-RV64-NEXT: addi a0, a0, %lo(a)
+; CHECK-CF-RV64-NEXT: call callee_struct
+; CHECK-CF-RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; CHECK-CF-RV64-NEXT: addi sp, sp, 16
+; CHECK-CF-RV64-NEXT: ret
+;
+; CHECK-CF-RV32-LARGE-LABEL: caller_nostruct:
+; CHECK-CF-RV32-LARGE: # %bb.0: # %entry
+; CHECK-CF-RV32-LARGE-NEXT: lpad 0
+; CHECK-CF-RV32-LARGE-NEXT: addi sp, sp, -16
+; CHECK-CF-RV32-LARGE-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; CHECK-CF-RV32-LARGE-NEXT: .Lpcrel_hi13:
+; CHECK-CF-RV32-LARGE-NEXT: auipc a0, %pcrel_hi(.LCPI11_0)
+; CHECK-CF-RV32-LARGE-NEXT: .Lpcrel_hi14:
+; CHECK-CF-RV32-LARGE-NEXT: auipc a1, %pcrel_hi(.LCPI11_1)
+; CHECK-CF-RV32-LARGE-NEXT: lw a0, %pcrel_lo(.Lpcrel_hi13)(a0)
+; CHECK-CF-RV32-LARGE-NEXT: lw t2, %pcrel_lo(.Lpcrel_hi14)(a1)
+; CHECK-CF-RV32-LARGE-NEXT: jalr t2
+; CHECK-CF-RV32-LARGE-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; CHECK-CF-RV32-LARGE-NEXT: addi sp, sp, 16
+; CHECK-CF-RV32-LARGE-NEXT: ret
+;
+; CHECK-CF-RV64-LARGE-LABEL: caller_nostruct:
+; CHECK-CF-RV64-LARGE: # %bb.0: # %entry
+; CHECK-CF-RV64-LARGE-NEXT: lpad 0
+; CHECK-CF-RV64-LARGE-NEXT: addi sp, sp, -16
+; CHECK-CF-RV64-LARGE-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; CHECK-CF-RV64-LARGE-NEXT: .Lpcrel_hi13:
+; CHECK-CF-RV64-LARGE-NEXT: auipc a0, %pcrel_hi(.LCPI11_0)
+; CHECK-CF-RV64-LARGE-NEXT: .Lpcrel_hi14:
+; CHECK-CF-RV64-LARGE-NEXT: auipc a1, %pcrel_hi(.LCPI11_1)
+; CHECK-CF-RV64-LARGE-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi13)(a0)
+; CHECK-CF-RV64-LARGE-NEXT: ld t2, %pcrel_lo(.Lpcrel_hi14)(a1)
+; CHECK-CF-RV64-LARGE-NEXT: jalr t2
+; CHECK-CF-RV64-LARGE-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; CHECK-CF-RV64-LARGE-NEXT: addi sp, sp, 16
+; CHECK-CF-RV64-LARGE-NEXT: ret
entry:
tail call void @callee_struct(ptr sret(%struct.A) @a)
ret void
@@ -478,17 +1048,51 @@ define void @caller_struct(ptr sret(%struct.A) %a) nounwind {
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
;
-; CHECK-LARGE-ZICFILP-LABEL: caller_struct:
-; CHECK-LARGE-ZICFILP: # %bb.0: # %entry
-; CHECK-LARGE-ZICFILP-NEXT: addi sp, sp, -16
-; CHECK-LARGE-ZICFILP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; CHECK-LARGE-ZICFILP-NEXT: .Lpcrel_hi15:
-; CHECK-LARGE-ZICFILP-NEXT: auipc a0, %pcrel_hi(.LCPI12_0)
-; CHECK-LARGE-ZICFILP-NEXT: lw a0, %pcrel_lo(.Lpcrel_hi15)(a0)
-; CHECK-LARGE-ZICFILP-NEXT: jalr a0
-; CHECK-LARGE-ZICFILP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; CHECK-LARGE-ZICFILP-NEXT: addi sp, sp, 16
-; CHECK-LARGE-ZICFILP-NEXT: ret
+; CHECK-CF-RV32-LABEL: caller_struct:
+; CHECK-CF-RV32: # %bb.0: # %entry
+; CHECK-CF-RV32-NEXT: lpad 0
+; CHECK-CF-RV32-NEXT: addi sp, sp, -16
+; CHECK-CF-RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; CHECK-CF-RV32-NEXT: call callee_nostruct
+; CHECK-CF-RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; CHECK-CF-RV32-NEXT: addi sp, sp, 16
+; CHECK-CF-RV32-NEXT: ret
+;
+; CHECK-CF-RV64-LABEL: caller_struct:
+; CHECK-CF-RV64: # %bb.0: # %entry
+; CHECK-CF-RV64-NEXT: lpad 0
+; CHECK-CF-RV64-NEXT: addi sp, sp, -16
+; CHECK-CF-RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; CHECK-CF-RV64-NEXT: call callee_nostruct
+; CHECK-CF-RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; CHECK-CF-RV64-NEXT: addi sp, sp, 16
+; CHECK-CF-RV64-NEXT: ret
+;
+; CHECK-CF-RV32-LARGE-LABEL: caller_struct:
+; CHECK-CF-RV32-LARGE: # %bb.0: # %entry
+; CHECK-CF-RV32-LARGE-NEXT: lpad 0
+; CHECK-CF-RV32-LARGE-NEXT: addi sp, sp, -16
+; CHECK-CF-RV32-LARGE-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; CHECK-CF-RV32-LARGE-NEXT: .Lpcrel_hi15:
+; CHECK-CF-RV32-LARGE-NEXT: auipc a0, %pcrel_hi(.LCPI12_0)
+; CHECK-CF-RV32-LARGE-NEXT: lw t2, %pcrel_lo(.Lpcrel_hi15)(a0)
+; CHECK-CF-RV32-LARGE-NEXT: jalr t2
+; CHECK-CF-RV32-LARGE-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; CHECK-CF-RV32-LARGE-NEXT: addi sp, sp, 16
+; CHECK-CF-RV32-LARGE-NEXT: ret
+;
+; CHECK-CF-RV64-LARGE-LABEL: caller_struct:
+; CHECK-CF-RV64-LARGE: # %bb.0: # %entry
+; CHECK-CF-RV64-LARGE-NEXT: lpad 0
+; CHECK-CF-RV64-LARGE-NEXT: addi sp, sp, -16
+; CHECK-CF-RV64-LARGE-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; CHECK-CF-RV64-LARGE-NEXT: .Lpcrel_hi15:
+; CHECK-CF-RV64-LARGE-NEXT: auipc a0, %pcrel_hi(.LCPI12_0)
+; CHECK-CF-RV64-LARGE-NEXT: ld t2, %pcrel_lo(.Lpcrel_hi15)(a0)
+; CHECK-CF-RV64-LARGE-NEXT: jalr t2
+; CHECK-CF-RV64-LARGE-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; CHECK-CF-RV64-LARGE-NEXT: addi sp, sp, 16
+; CHECK-CF-RV64-LARGE-NEXT: ret
entry:
tail call void @callee_nostruct()
ret void
@@ -505,17 +1109,51 @@ define i32 @disable_tail_calls(i32 %i) nounwind "disable-tail-calls"="true" {
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
;
-; CHECK-LARGE-ZICFILP-LABEL: disable_tail_calls:
-; CHECK-LARGE-ZICFILP: # %bb.0: # %entry
-; CHECK-LARGE-ZICFILP-NEXT: addi sp, sp, -16
-; CHECK-LARGE-ZICFILP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; CHECK-LARGE-ZICFILP-NEXT: .Lpcrel_hi16:
-; CHECK-LARGE-ZICFILP-NEXT: auipc a1, %pcrel_hi(.LCPI13_0)
-; CHECK-LARGE-ZICFILP-NEXT: lw a1, %pcrel_lo(.Lpcrel_hi16)(a1)
-; CHECK-LARGE-ZICFILP-NEXT: jalr a1
-; CHECK-LARGE-ZICFILP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; CHECK-LARGE-ZICFILP-NEXT: addi sp, sp, 16
-; CHECK-LARGE-ZICFILP-NEXT: ret
+; CHECK-CF-RV32-LABEL: disable_tail_calls:
+; CHECK-CF-RV32: # %bb.0: # %entry
+; CHECK-CF-RV32-NEXT: lpad 0
+; CHECK-CF-RV32-NEXT: addi sp, sp, -16
+; CHECK-CF-RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; CHECK-CF-RV32-NEXT: call callee_tail
+; CHECK-CF-RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; CHECK-CF-RV32-NEXT: addi sp, sp, 16
+; CHECK-CF-RV32-NEXT: ret
+;
+; CHECK-CF-RV64-LABEL: disable_tail_calls:
+; CHECK-CF-RV64: # %bb.0: # %entry
+; CHECK-CF-RV64-NEXT: lpad 0
+; CHECK-CF-RV64-NEXT: addi sp, sp, -16
+; CHECK-CF-RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; CHECK-CF-RV64-NEXT: call callee_tail
+; CHECK-CF-RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; CHECK-CF-RV64-NEXT: addi sp, sp, 16
+; CHECK-CF-RV64-NEXT: ret
+;
+; CHECK-CF-RV32-LARGE-LABEL: disable_tail_calls:
+; CHECK-CF-RV32-LARGE: # %bb.0: # %entry
+; CHECK-CF-RV32-LARGE-NEXT: lpad 0
+; CHECK-CF-RV32-LARGE-NEXT: addi sp, sp, -16
+; CHECK-CF-RV32-LARGE-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; CHECK-CF-RV32-LARGE-NEXT: .Lpcrel_hi16:
+; CHECK-CF-RV32-LARGE-NEXT: auipc a1, %pcrel_hi(.LCPI13_0)
+; CHECK-CF-RV32-LARGE-NEXT: lw t2, %pcrel_lo(.Lpcrel_hi16)(a1)
+; CHECK-CF-RV32-LARGE-NEXT: jalr t2
+; CHECK-CF-RV32-LARGE-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; CHECK-CF-RV32-LARGE-NEXT: addi sp, sp, 16
+; CHECK-CF-RV32-LARGE-NEXT: ret
+;
+; CHECK-CF-RV64-LARGE-LABEL: disable_tail_calls:
+; CHECK-CF-RV64-LARGE: # %bb.0: # %entry
+; CHECK-CF-RV64-LARGE-NEXT: lpad 0
+; CHECK-CF-RV64-LARGE-NEXT: addi sp, sp, -16
+; CHECK-CF-RV64-LARGE-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; CHECK-CF-RV64-LARGE-NEXT: .Lpcrel_hi16:
+; CHECK-CF-RV64-LARGE-NEXT: auipc a1, %pcrel_hi(.LCPI13_0)
+; CHECK-CF-RV64-LARGE-NEXT: ld t2, %pcrel_lo(.Lpcrel_hi16)(a1)
+; CHECK-CF-RV64-LARGE-NEXT: jalr t2
+; CHECK-CF-RV64-LARGE-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; CHECK-CF-RV64-LARGE-NEXT: addi sp, sp, 16
+; CHECK-CF-RV64-LARGE-NEXT: ret
entry:
%rv = tail call i32 @callee_tail(i32 %i)
ret i32 %rv
@@ -543,33 +1181,101 @@ define i32 @duplicate_returns(i32 %a, i32 %b) nounwind {
; CHECK-NEXT: .LBB14_6: # %if.else8
; CHECK-NEXT: tail test3
;
-; CHECK-LARGE-ZICFILP-LABEL: duplicate_returns:
-; CHECK-LARGE-ZICFILP: # %bb.0: # %entry
-; CHECK-LARGE-ZICFILP-NEXT: beqz a0, .LBB14_4
-; CHECK-LARGE-ZICFILP-NEXT: # %bb.1: # %if.else
-; CHECK-LARGE-ZICFILP-NEXT: beqz a1, .LBB14_5
-; CHECK-LARGE-ZICFILP-NEXT: # %bb.2: # %if.else4
-; CHECK-LARGE-ZICFILP-NEXT: bge a1, a0, .LBB14_6
-; CHECK-LARGE-ZICFILP-NEXT: # %bb.3: # %if.then6
-; CHECK-LARGE-ZICFILP-NEXT: .Lpcrel_hi19:
-; CHECK-LARGE-ZICFILP-NEXT: auipc a0, %pcrel_hi(.LCPI14_1)
-; CHECK-LARGE-ZICFILP-NEXT: lw t1, %pcrel_lo(.Lpcrel_hi19)(a0)
-; CHECK-LARGE-ZICFILP-NEXT: jr t1
-; CHECK-LARGE-ZICFILP-NEXT: .LBB14_4: # %if.then
-; CHECK-LARGE-ZICFILP-NEXT: .Lpcrel_hi17:
-; CHECK-LARGE-ZICFILP-NEXT: auipc a0, %pcrel_hi(.LCPI14_3)
-; CHECK-LARGE-ZICFILP-NEXT: lw t1, %pcrel_lo(.Lpcrel_hi17)(a0)
-; CHECK-LARGE-ZICFILP-NEXT: jr t1
-; CHECK-LARGE-ZICFILP-NEXT: .LBB14_5: # %if.then2
-; CHECK-LARGE-ZICFILP-NEXT: .Lpcrel_hi18:
-; CHECK-LARGE-ZICFILP-NEXT: auipc a0, %pcrel_hi(.LCPI14_2)
-; CHECK-LARGE-ZICFILP-NEXT: lw t1, %pcrel_lo(.Lpcrel_hi18)(a0)
-; CHECK-LARGE-ZICFILP-NEXT: jr t1
-; CHECK-LARGE-ZICFILP-NEXT: .LBB14_6: # %if.else8
-; CHECK-LARGE-ZICFILP-NEXT: .Lpcrel_hi20:
-; CHECK-LARGE-ZICFILP-NEXT: auipc a0, %pcrel_hi(.LCPI14_0)
-; CHECK-LARGE-ZICFILP-NEXT: lw t1, %pcrel_lo(.Lpcrel_hi20)(a0)
-; CHECK-LARGE-ZICFILP-NEXT: jr t1
+; CHECK-CF-RV32-LABEL: duplicate_returns:
+; CHECK-CF-RV32: # %bb.0: # %entry
+; CHECK-CF-RV32-NEXT: lpad 0
+; CHECK-CF-RV32-NEXT: beqz a0, .LBB14_4
+; CHECK-CF-RV32-NEXT: # %bb.1: # %if.else
+; CHECK-CF-RV32-NEXT: beqz a1, .LBB14_5
+; CHECK-CF-RV32-NEXT: # %bb.2: # %if.else4
+; CHECK-CF-RV32-NEXT: bge a1, a0, .LBB14_6
+; CHECK-CF-RV32-NEXT: # %bb.3: # %if.then6
+; CHECK-CF-RV32-NEXT: tail test2
+; CHECK-CF-RV32-NEXT: .LBB14_4: # %if.then
+; CHECK-CF-RV32-NEXT: tail test
+; CHECK-CF-RV32-NEXT: .LBB14_5: # %if.then2
+; CHECK-CF-RV32-NEXT: tail test1
+; CHECK-CF-RV32-NEXT: .LBB14_6: # %if.else8
+; CHECK-CF-RV32-NEXT: tail test3
+;
+; CHECK-CF-RV64-LABEL: duplicate_returns:
+; CHECK-CF-RV64: # %bb.0: # %entry
+; CHECK-CF-RV64-NEXT: lpad 0
+; CHECK-CF-RV64-NEXT: sext.w a0, a0
+; CHECK-CF-RV64-NEXT: beqz a0, .LBB14_4
+; CHECK-CF-RV64-NEXT: # %bb.1: # %if.else
+; CHECK-CF-RV64-NEXT: sext.w a1, a1
+; CHECK-CF-RV64-NEXT: beqz a1, .LBB14_5
+; CHECK-CF-RV64-NEXT: # %bb.2: # %if.else4
+; CHECK-CF-RV64-NEXT: bge a1, a0, .LBB14_6
+; CHECK-CF-RV64-NEXT: # %bb.3: # %if.then6
+; CHECK-CF-RV64-NEXT: tail test2
+; CHECK-CF-RV64-NEXT: .LBB14_4: # %if.then
+; CHECK-CF-RV64-NEXT: tail test
+; CHECK-CF-RV64-NEXT: .LBB14_5: # %if.then2
+; CHECK-CF-RV64-NEXT: tail test1
+; CHECK-CF-RV64-NEXT: .LBB14_6: # %if.else8
+; CHECK-CF-RV64-NEXT: tail test3
+;
+; CHECK-CF-RV32-LARGE-LABEL: duplicate_returns:
+; CHECK-CF-RV32-LARGE: # %bb.0: # %entry
+; CHECK-CF-RV32-LARGE-NEXT: lpad 0
+; CHECK-CF-RV32-LARGE-NEXT: beqz a0, .LBB14_4
+; CHECK-CF-RV32-LARGE-NEXT: # %bb.1: # %if.else
+; CHECK-CF-RV32-LARGE-NEXT: beqz a1, .LBB14_5
+; CHECK-CF-RV32-LARGE-NEXT: # %bb.2: # %if.else4
+; CHECK-CF-RV32-LARGE-NEXT: bge a1, a0, .LBB14_6
+; CHECK-CF-RV32-LARGE-NEXT: # %bb.3: # %if.then6
+; CHECK-CF-RV32-LARGE-NEXT: .Lpcrel_hi19:
+; CHECK-CF-RV32-LARGE-NEXT: auipc a0, %pcrel_hi(.LCPI14_1)
+; CHECK-CF-RV32-LARGE-NEXT: lw t2, %pcrel_lo(.Lpcrel_hi19)(a0)
+; CHECK-CF-RV32-LARGE-NEXT: jr t2
+; CHECK-CF-RV32-LARGE-NEXT: .LBB14_4: # %if.then
+; CHECK-CF-RV32-LARGE-NEXT: .Lpcrel_hi17:
+; CHECK-CF-RV32-LARGE-NEXT: auipc a0, %pcrel_hi(.LCPI14_3)
+; CHECK-CF-RV32-LARGE-NEXT: lw t2, %pcrel_lo(.Lpcrel_hi17)(a0)
+; CHECK-CF-RV32-LARGE-NEXT: jr t2
+; CHECK-CF-RV32-LARGE-NEXT: .LBB14_5: # %if.then2
+; CHECK-CF-RV32-LARGE-NEXT: .Lpcrel_hi18:
+; CHECK-CF-RV32-LARGE-NEXT: auipc a0, %pcrel_hi(.LCPI14_2)
+; CHECK-CF-RV32-LARGE-NEXT: lw t2, %pcrel_lo(.Lpcrel_hi18)(a0)
+; CHECK-CF-RV32-LARGE-NEXT: jr t2
+; CHECK-CF-RV32-LARGE-NEXT: .LBB14_6: # %if.else8
+; CHECK-CF-RV32-LARGE-NEXT: .Lpcrel_hi20:
+; CHECK-CF-RV32-LARGE-NEXT: auipc a0, %pcrel_hi(.LCPI14_0)
+; CHECK-CF-RV32-LARGE-NEXT: lw t2, %pcrel_lo(.Lpcrel_hi20)(a0)
+; CHECK-CF-RV32-LARGE-NEXT: jr t2
+;
+; CHECK-CF-RV64-LARGE-LABEL: duplicate_returns:
+; CHECK-CF-RV64-LARGE: # %bb.0: # %entry
+; CHECK-CF-RV64-LARGE-NEXT: lpad 0
+; CHECK-CF-RV64-LARGE-NEXT: sext.w a0, a0
+; CHECK-CF-RV64-LARGE-NEXT: beqz a0, .LBB14_4
+; CHECK-CF-RV64-LARGE-NEXT: # %bb.1: # %if.else
+; CHECK-CF-RV64-LARGE-NEXT: sext.w a1, a1
+; CHECK-CF-RV64-LARGE-NEXT: beqz a1, .LBB14_5
+; CHECK-CF-RV64-LARGE-NEXT: # %bb.2: # %if.else4
+; CHECK-CF-RV64-LARGE-NEXT: bge a1, a0, .LBB14_6
+; CHECK-CF-RV64-LARGE-NEXT: # %bb.3: # %if.then6
+; CHECK-CF-RV64-LARGE-NEXT: .Lpcrel_hi19:
+; CHECK-CF-RV64-LARGE-NEXT: auipc a0, %pcrel_hi(.LCPI14_1)
+; CHECK-CF-RV64-LARGE-NEXT: ld t2, %pcrel_lo(.Lpcrel_hi19)(a0)
+; CHECK-CF-RV64-LARGE-NEXT: jr t2
+; CHECK-CF-RV64-LARGE-NEXT: .LBB14_4: # %if.then
+; CHECK-CF-RV64-LARGE-NEXT: .Lpcrel_hi17:
+; CHECK-CF-RV64-LARGE-NEXT: auipc a0, %pcrel_hi(.LCPI14_3)
+; CHECK-CF-RV64-LARGE-NEXT: ld t2, %pcrel_lo(.Lpcrel_hi17)(a0)
+; CHECK-CF-RV64-LARGE-NEXT: jr t2
+; CHECK-CF-RV64-LARGE-NEXT: .LBB14_5: # %if.then2
+; CHECK-CF-RV64-LARGE-NEXT: .Lpcrel_hi18:
+; CHECK-CF-RV64-LARGE-NEXT: auipc a0, %pcrel_hi(.LCPI14_2)
+; CHECK-CF-RV64-LARGE-NEXT: ld t2, %pcrel_lo(.Lpcrel_hi18)(a0)
+; CHECK-CF-RV64-LARGE-NEXT: jr t2
+; CHECK-CF-RV64-LARGE-NEXT: .LBB14_6: # %if.else8
+; CHECK-CF-RV64-LARGE-NEXT: .Lpcrel_hi20:
+; CHECK-CF-RV64-LARGE-NEXT: auipc a0, %pcrel_hi(.LCPI14_0)
+; CHECK-CF-RV64-LARGE-NEXT: ld t2, %pcrel_lo(.Lpcrel_hi20)(a0)
+; CHECK-CF-RV64-LARGE-NEXT: jr t2
entry:
%cmp = icmp eq i32 %a, 0
br i1 %cmp, label %if.then, label %if.else
@@ -619,3 +1325,4 @@ return: ; preds = %if.else8, %if.then6
!12 = !{i32 999000, i64 100, i32 1}
!13 = !{i32 999999, i64 1, i32 2}
!14 = !{!"function_entry_count", i64 0}
+;CF: !15 = !{i32 8, !"cf-protection-branch", i32 1}
diff --git a/llvm/test/CodeGen/RISCV/tail-cf-branch.ll b/llvm/test/CodeGen/RISCV/tail-cf-branch.ll
deleted file mode 100644
index 9e87493f97cdd..0000000000000
--- a/llvm/test/CodeGen/RISCV/tail-cf-branch.ll
+++ /dev/null
@@ -1,240 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefix=RV32I %s
-; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefix=RV64I %s
-; RUN: llc -code-model=large -mtriple=riscv32 -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefix=RV32I-LARGE %s
-; RUN: llc -code-model=large -mtriple=riscv64 -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefix=RV64I-LARGE %s
-
-; This file contains tests similar to tail-calls.ll but with cf-protection-branch
-; module flag enabled. It tests landing pad generation and NonX7 variants for
-; indirect tail calls.
-
-; Test tail call generation with cf-protection-branch enabled.
-; This tests landing pad generation and NonX7 variants for indirect tail calls.
-
-declare i32 @callee_tail(i32 %i)
-
-define i32 @caller_tail(i32 %i) nounwind {
-; RV32I-LABEL: caller_tail:
-; RV32I: # %bb.0: # %entry
-; RV32I-NEXT: lpad 0
-; RV32I-NEXT: tail callee_tail
-;
-; RV64I-LABEL: caller_tail:
-; RV64I: # %bb.0: # %entry
-; RV64I-NEXT: lpad 0
-; RV64I-NEXT: tail callee_tail
-;
-; RV32I-LARGE-LABEL: caller_tail:
-; RV32I-LARGE: # %bb.0: # %entry
-; RV32I-LARGE-NEXT: lpad 0
-; RV32I-LARGE-NEXT: .Lpcrel_hi0:
-; RV32I-LARGE-NEXT: auipc a1, %pcrel_hi(.LCPI0_0)
-; RV32I-LARGE-NEXT: lw t2, %pcrel_lo(.Lpcrel_hi0)(a1)
-; RV32I-LARGE-NEXT: jr t2
-;
-; RV64I-LARGE-LABEL: caller_tail:
-; RV64I-LARGE: # %bb.0: # %entry
-; RV64I-LARGE-NEXT: lpad 0
-; RV64I-LARGE-NEXT: .Lpcrel_hi0:
-; RV64I-LARGE-NEXT: auipc a1, %pcrel_hi(.LCPI0_0)
-; RV64I-LARGE-NEXT: ld t2, %pcrel_lo(.Lpcrel_hi0)(a1)
-; RV64I-LARGE-NEXT: jr t2
-entry:
- %r = tail call i32 @callee_tail(i32 %i)
- ret i32 %r
-}
-
- at dest = global [2 x i8] zeroinitializer
-
-define void @caller_extern(ptr %src) optsize {
-; RV32I-LABEL: caller_extern:
-; RV32I: # %bb.0: # %entry
-; RV32I-NEXT: lpad 0
-; RV32I-NEXT: lui a1, %hi(dest)
-; RV32I-NEXT: addi a1, a1, %lo(dest)
-; RV32I-NEXT: li a2, 7
-; RV32I-NEXT: mv a3, a0
-; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: mv a1, a3
-; RV32I-NEXT: tail memcpy
-;
-; RV64I-LABEL: caller_extern:
-; RV64I: # %bb.0: # %entry
-; RV64I-NEXT: lpad 0
-; RV64I-NEXT: lui a1, %hi(dest)
-; RV64I-NEXT: addi a1, a1, %lo(dest)
-; RV64I-NEXT: li a2, 7
-; RV64I-NEXT: mv a3, a0
-; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: mv a1, a3
-; RV64I-NEXT: tail memcpy
-;
-; RV32I-LARGE-LABEL: caller_extern:
-; RV32I-LARGE: # %bb.0: # %entry
-; RV32I-LARGE-NEXT: lpad 0
-; RV32I-LARGE-NEXT: .Lpcrel_hi1:
-; RV32I-LARGE-NEXT: auipc a1, %pcrel_hi(.LCPI1_0)
-; RV32I-LARGE-NEXT: .Lpcrel_hi2:
-; RV32I-LARGE-NEXT: auipc a2, %pcrel_hi(.LCPI1_1)
-; RV32I-LARGE-NEXT: lw a1, %pcrel_lo(.Lpcrel_hi1)(a1)
-; RV32I-LARGE-NEXT: lw t2, %pcrel_lo(.Lpcrel_hi2)(a2)
-; RV32I-LARGE-NEXT: li a2, 7
-; RV32I-LARGE-NEXT: mv a3, a0
-; RV32I-LARGE-NEXT: mv a0, a1
-; RV32I-LARGE-NEXT: mv a1, a3
-; RV32I-LARGE-NEXT: jr t2
-;
-; RV64I-LARGE-LABEL: caller_extern:
-; RV64I-LARGE: # %bb.0: # %entry
-; RV64I-LARGE-NEXT: lpad 0
-; RV64I-LARGE-NEXT: .Lpcrel_hi1:
-; RV64I-LARGE-NEXT: auipc a1, %pcrel_hi(.LCPI1_0)
-; RV64I-LARGE-NEXT: .Lpcrel_hi2:
-; RV64I-LARGE-NEXT: auipc a2, %pcrel_hi(.LCPI1_1)
-; RV64I-LARGE-NEXT: ld a1, %pcrel_lo(.Lpcrel_hi1)(a1)
-; RV64I-LARGE-NEXT: ld t2, %pcrel_lo(.Lpcrel_hi2)(a2)
-; RV64I-LARGE-NEXT: li a2, 7
-; RV64I-LARGE-NEXT: mv a3, a0
-; RV64I-LARGE-NEXT: mv a0, a1
-; RV64I-LARGE-NEXT: mv a1, a3
-; RV64I-LARGE-NEXT: jr t2
-entry:
- tail call void @llvm.memcpy.p0.p0.i32(ptr @dest, ptr %src, i32 7, i1 false)
- ret void
-}
-
-declare void @llvm.memcpy.p0.p0.i32(ptr, ptr, i32, i1)
-
-; Indirect tail call
-declare void @callee_indirect1()
-declare void @callee_indirect2()
-
-define void @caller_indirect_tail(i32 %a) nounwind {
-; RV32I-LABEL: caller_indirect_tail:
-; RV32I: # %bb.0: # %entry
-; RV32I-NEXT: lpad 0
-; RV32I-NEXT: beqz a0, .LBB2_2
-; RV32I-NEXT: # %bb.1: # %entry
-; RV32I-NEXT: lui t1, %hi(callee_indirect2)
-; RV32I-NEXT: addi t1, t1, %lo(callee_indirect2)
-; RV32I-NEXT: jr t1
-; RV32I-NEXT: .LBB2_2:
-; RV32I-NEXT: lui t1, %hi(callee_indirect1)
-; RV32I-NEXT: addi t1, t1, %lo(callee_indirect1)
-; RV32I-NEXT: jr t1
-;
-; RV64I-LABEL: caller_indirect_tail:
-; RV64I: # %bb.0: # %entry
-; RV64I-NEXT: lpad 0
-; RV64I-NEXT: sext.w a0, a0
-; RV64I-NEXT: beqz a0, .LBB2_2
-; RV64I-NEXT: # %bb.1: # %entry
-; RV64I-NEXT: lui t1, %hi(callee_indirect2)
-; RV64I-NEXT: addi t1, t1, %lo(callee_indirect2)
-; RV64I-NEXT: jr t1
-; RV64I-NEXT: .LBB2_2:
-; RV64I-NEXT: lui t1, %hi(callee_indirect1)
-; RV64I-NEXT: addi t1, t1, %lo(callee_indirect1)
-; RV64I-NEXT: jr t1
-;
-; RV32I-LARGE-LABEL: caller_indirect_tail:
-; RV32I-LARGE: # %bb.0: # %entry
-; RV32I-LARGE-NEXT: lpad 0
-; RV32I-LARGE-NEXT: beqz a0, .LBB2_2
-; RV32I-LARGE-NEXT: # %bb.1: # %entry
-; RV32I-LARGE-NEXT: .Lpcrel_hi4:
-; RV32I-LARGE-NEXT: auipc a0, %pcrel_hi(.LCPI2_0)
-; RV32I-LARGE-NEXT: lw t1, %pcrel_lo(.Lpcrel_hi4)(a0)
-; RV32I-LARGE-NEXT: jr t1
-; RV32I-LARGE-NEXT: .LBB2_2:
-; RV32I-LARGE-NEXT: .Lpcrel_hi3:
-; RV32I-LARGE-NEXT: auipc a0, %pcrel_hi(.LCPI2_1)
-; RV32I-LARGE-NEXT: lw t1, %pcrel_lo(.Lpcrel_hi3)(a0)
-; RV32I-LARGE-NEXT: jr t1
-;
-; RV64I-LARGE-LABEL: caller_indirect_tail:
-; RV64I-LARGE: # %bb.0: # %entry
-; RV64I-LARGE-NEXT: lpad 0
-; RV64I-LARGE-NEXT: sext.w a0, a0
-; RV64I-LARGE-NEXT: beqz a0, .LBB2_2
-; RV64I-LARGE-NEXT: # %bb.1: # %entry
-; RV64I-LARGE-NEXT: .Lpcrel_hi4:
-; RV64I-LARGE-NEXT: auipc a0, %pcrel_hi(.LCPI2_0)
-; RV64I-LARGE-NEXT: ld t1, %pcrel_lo(.Lpcrel_hi4)(a0)
-; RV64I-LARGE-NEXT: jr t1
-; RV64I-LARGE-NEXT: .LBB2_2:
-; RV64I-LARGE-NEXT: .Lpcrel_hi3:
-; RV64I-LARGE-NEXT: auipc a0, %pcrel_hi(.LCPI2_1)
-; RV64I-LARGE-NEXT: ld t1, %pcrel_lo(.Lpcrel_hi3)(a0)
-; RV64I-LARGE-NEXT: jr t1
-entry:
- %tobool = icmp eq i32 %a, 0
- %callee = select i1 %tobool, ptr @callee_indirect1, ptr @callee_indirect2
- tail call void %callee()
- ret void
-}
-
-; Make sure we don't use t0 as the source for jr as that is a hint to pop the
-; return address stack on some microarchitectures.
-define i32 @caller_indirect_no_t0(ptr %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6, i32 %7) nounwind {
-; RV32I-LABEL: caller_indirect_no_t0:
-; RV32I: # %bb.0:
-; RV32I-NEXT: lpad 0
-; RV32I-NEXT: mv t1, a0
-; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: mv a1, a2
-; RV32I-NEXT: mv a2, a3
-; RV32I-NEXT: mv a3, a4
-; RV32I-NEXT: mv a4, a5
-; RV32I-NEXT: mv a5, a6
-; RV32I-NEXT: mv a6, a7
-; RV32I-NEXT: jr t1
-;
-; RV64I-LABEL: caller_indirect_no_t0:
-; RV64I: # %bb.0:
-; RV64I-NEXT: lpad 0
-; RV64I-NEXT: mv t1, a0
-; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: mv a1, a2
-; RV64I-NEXT: mv a2, a3
-; RV64I-NEXT: mv a3, a4
-; RV64I-NEXT: mv a4, a5
-; RV64I-NEXT: mv a5, a6
-; RV64I-NEXT: mv a6, a7
-; RV64I-NEXT: jr t1
-;
-; RV32I-LARGE-LABEL: caller_indirect_no_t0:
-; RV32I-LARGE: # %bb.0:
-; RV32I-LARGE-NEXT: lpad 0
-; RV32I-LARGE-NEXT: mv t1, a0
-; RV32I-LARGE-NEXT: mv a0, a1
-; RV32I-LARGE-NEXT: mv a1, a2
-; RV32I-LARGE-NEXT: mv a2, a3
-; RV32I-LARGE-NEXT: mv a3, a4
-; RV32I-LARGE-NEXT: mv a4, a5
-; RV32I-LARGE-NEXT: mv a5, a6
-; RV32I-LARGE-NEXT: mv a6, a7
-; RV32I-LARGE-NEXT: jr t1
-;
-; RV64I-LARGE-LABEL: caller_indirect_no_t0:
-; RV64I-LARGE: # %bb.0:
-; RV64I-LARGE-NEXT: lpad 0
-; RV64I-LARGE-NEXT: mv t1, a0
-; RV64I-LARGE-NEXT: mv a0, a1
-; RV64I-LARGE-NEXT: mv a1, a2
-; RV64I-LARGE-NEXT: mv a2, a3
-; RV64I-LARGE-NEXT: mv a3, a4
-; RV64I-LARGE-NEXT: mv a4, a5
-; RV64I-LARGE-NEXT: mv a5, a6
-; RV64I-LARGE-NEXT: mv a6, a7
-; RV64I-LARGE-NEXT: jr t1
- %9 = tail call i32 %0(i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6, i32 %7)
- ret i32 %9
-}
-
-!llvm.module.flags = !{!0}
-!0 = !{i32 8, !"cf-protection-branch", i32 1}
>From 6a8de6301c4ad68feca5141bada8265a5ddfa363 Mon Sep 17 00:00:00 2001
From: Kito Cheng <kito.cheng at sifive.com>
Date: Thu, 26 Feb 2026 11:44:52 +0800
Subject: [PATCH 4/7] !fixup do not use defined
---
llvm/test/CodeGen/RISCV/tail-calls.ll | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/llvm/test/CodeGen/RISCV/tail-calls.ll b/llvm/test/CodeGen/RISCV/tail-calls.ll
index 81ebac3f3a6fb..b9ae9616df1f7 100644
--- a/llvm/test/CodeGen/RISCV/tail-calls.ll
+++ b/llvm/test/CodeGen/RISCV/tail-calls.ll
@@ -1,15 +1,17 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple riscv32-unknown-linux-gnu -o - %s | FileCheck %s
; RUN: llc -mtriple riscv32-unknown-elf -o - %s | FileCheck %s
-; DEFINE: %{sed} = sed -e 's/!llvm.module.flags = !{!0}/!llvm.module.flags = !{!0, !15}/' \
-; DEFINE: -e 's/^;CF: //' %s
-; RUN: %{sed} | llc -mtriple=riscv32 -verify-machineinstrs \
+; RUN: sed -e 's/!llvm.module.flags = !{!0}/!llvm.module.flags = !{!0, !15}/' -e 's/^;CF: //' %s \
+; RUN: | llc -mtriple=riscv32 -verify-machineinstrs \
; RUN: | FileCheck -check-prefix=CHECK-CF-RV32 %s
-; RUN: %{sed} | llc -mtriple=riscv64 -verify-machineinstrs \
+; RUN: sed -e 's/!llvm.module.flags = !{!0}/!llvm.module.flags = !{!0, !15}/' -e 's/^;CF: //' %s \
+; RUN: | llc -mtriple=riscv64 -verify-machineinstrs \
; RUN: | FileCheck -check-prefix=CHECK-CF-RV64 %s
-; RUN: %{sed} | llc -code-model=large -mtriple=riscv32 -verify-machineinstrs \
+; RUN: sed -e 's/!llvm.module.flags = !{!0}/!llvm.module.flags = !{!0, !15}/' -e 's/^;CF: //' %s \
+; RUN: | llc -code-model=large -mtriple=riscv32 -verify-machineinstrs \
; RUN: | FileCheck -check-prefix=CHECK-CF-RV32-LARGE %s
-; RUN: %{sed} | llc -code-model=large -mtriple=riscv64 -verify-machineinstrs \
+; RUN: sed -e 's/!llvm.module.flags = !{!0}/!llvm.module.flags = !{!0, !15}/' -e 's/^;CF: //' %s \
+; RUN: | llc -code-model=large -mtriple=riscv64 -verify-machineinstrs \
; RUN: | FileCheck -check-prefix=CHECK-CF-RV64-LARGE %s
; Perform tail call optimization for global address.
>From d8b16429ee2148b597c5e60730f7c79ef196326f Mon Sep 17 00:00:00 2001
From: Kito Cheng <kito.cheng at sifive.com>
Date: Thu, 26 Feb 2026 15:01:20 +0800
Subject: [PATCH 5/7] !fixup update tail-calls.ll
---
llvm/test/CodeGen/RISCV/tail-calls.ll | 182 +++++++++++---------------
1 file changed, 74 insertions(+), 108 deletions(-)
diff --git a/llvm/test/CodeGen/RISCV/tail-calls.ll b/llvm/test/CodeGen/RISCV/tail-calls.ll
index b9ae9616df1f7..7500990410386 100644
--- a/llvm/test/CodeGen/RISCV/tail-calls.ll
+++ b/llvm/test/CodeGen/RISCV/tail-calls.ll
@@ -441,118 +441,93 @@ declare i32 @callee_args(i32 %a, i32 %b, i32 %c, i32 %dd, i32 %e, i32 %ff, i32 %
define i32 @caller_args(i32 %a, i32 %b, i32 %c, i32 %dd, i32 %e, i32 %ff, i32 %g, i32 %h, i32 %i, i32 %j, i32 %k, i32 %l, i32 %m, i32 %n) nounwind {
; CHECK-LABEL: caller_args:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -32
-; CHECK-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
-; CHECK-NEXT: lw t0, 32(sp)
-; CHECK-NEXT: lw t1, 36(sp)
-; CHECK-NEXT: lw t2, 40(sp)
-; CHECK-NEXT: lw t3, 44(sp)
-; CHECK-NEXT: lw t4, 48(sp)
-; CHECK-NEXT: lw t5, 52(sp)
-; CHECK-NEXT: sw t4, 16(sp)
-; CHECK-NEXT: sw t5, 20(sp)
-; CHECK-NEXT: sw t0, 0(sp)
-; CHECK-NEXT: sw t1, 4(sp)
-; CHECK-NEXT: sw t2, 8(sp)
-; CHECK-NEXT: sw t3, 12(sp)
-; CHECK-NEXT: call callee_args
-; CHECK-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; CHECK-NEXT: addi sp, sp, 32
-; CHECK-NEXT: ret
+; CHECK-NEXT: lw t0, 20(sp)
+; CHECK-NEXT: lw t1, 16(sp)
+; CHECK-NEXT: lw t2, 0(sp)
+; CHECK-NEXT: lw t3, 4(sp)
+; CHECK-NEXT: lw t4, 8(sp)
+; CHECK-NEXT: lw t5, 12(sp)
+; CHECK-NEXT: sw t2, 0(sp)
+; CHECK-NEXT: sw t3, 4(sp)
+; CHECK-NEXT: sw t4, 8(sp)
+; CHECK-NEXT: sw t5, 12(sp)
+; CHECK-NEXT: sw t1, 16(sp)
+; CHECK-NEXT: sw t0, 20(sp)
+; CHECK-NEXT: tail callee_args
;
; CHECK-CF-RV32-LABEL: caller_args:
; CHECK-CF-RV32: # %bb.0: # %entry
; CHECK-CF-RV32-NEXT: lpad 0
-; CHECK-CF-RV32-NEXT: addi sp, sp, -32
-; CHECK-CF-RV32-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
-; CHECK-CF-RV32-NEXT: lw t0, 32(sp)
-; CHECK-CF-RV32-NEXT: lw t1, 36(sp)
-; CHECK-CF-RV32-NEXT: lw t2, 40(sp)
-; CHECK-CF-RV32-NEXT: lw t3, 44(sp)
-; CHECK-CF-RV32-NEXT: lw t4, 48(sp)
-; CHECK-CF-RV32-NEXT: lw t5, 52(sp)
-; CHECK-CF-RV32-NEXT: sw t4, 16(sp)
-; CHECK-CF-RV32-NEXT: sw t5, 20(sp)
-; CHECK-CF-RV32-NEXT: sw t0, 0(sp)
-; CHECK-CF-RV32-NEXT: sw t1, 4(sp)
-; CHECK-CF-RV32-NEXT: sw t2, 8(sp)
-; CHECK-CF-RV32-NEXT: sw t3, 12(sp)
-; CHECK-CF-RV32-NEXT: call callee_args
-; CHECK-CF-RV32-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; CHECK-CF-RV32-NEXT: addi sp, sp, 32
-; CHECK-CF-RV32-NEXT: ret
+; CHECK-CF-RV32-NEXT: lw t0, 20(sp)
+; CHECK-CF-RV32-NEXT: lw t1, 16(sp)
+; CHECK-CF-RV32-NEXT: lw t2, 0(sp)
+; CHECK-CF-RV32-NEXT: lw t3, 4(sp)
+; CHECK-CF-RV32-NEXT: lw t4, 8(sp)
+; CHECK-CF-RV32-NEXT: lw t5, 12(sp)
+; CHECK-CF-RV32-NEXT: sw t2, 0(sp)
+; CHECK-CF-RV32-NEXT: sw t3, 4(sp)
+; CHECK-CF-RV32-NEXT: sw t4, 8(sp)
+; CHECK-CF-RV32-NEXT: sw t5, 12(sp)
+; CHECK-CF-RV32-NEXT: sw t1, 16(sp)
+; CHECK-CF-RV32-NEXT: sw t0, 20(sp)
+; CHECK-CF-RV32-NEXT: tail callee_args
;
; CHECK-CF-RV64-LABEL: caller_args:
; CHECK-CF-RV64: # %bb.0: # %entry
; CHECK-CF-RV64-NEXT: lpad 0
-; CHECK-CF-RV64-NEXT: addi sp, sp, -64
-; CHECK-CF-RV64-NEXT: sd ra, 56(sp) # 8-byte Folded Spill
-; CHECK-CF-RV64-NEXT: ld t0, 64(sp)
-; CHECK-CF-RV64-NEXT: ld t1, 72(sp)
-; CHECK-CF-RV64-NEXT: ld t2, 80(sp)
-; CHECK-CF-RV64-NEXT: ld t3, 88(sp)
-; CHECK-CF-RV64-NEXT: ld t4, 96(sp)
-; CHECK-CF-RV64-NEXT: ld t5, 104(sp)
-; CHECK-CF-RV64-NEXT: sd t4, 32(sp)
-; CHECK-CF-RV64-NEXT: sd t5, 40(sp)
-; CHECK-CF-RV64-NEXT: sd t0, 0(sp)
-; CHECK-CF-RV64-NEXT: sd t1, 8(sp)
-; CHECK-CF-RV64-NEXT: sd t2, 16(sp)
-; CHECK-CF-RV64-NEXT: sd t3, 24(sp)
-; CHECK-CF-RV64-NEXT: call callee_args
-; CHECK-CF-RV64-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
-; CHECK-CF-RV64-NEXT: addi sp, sp, 64
-; CHECK-CF-RV64-NEXT: ret
+; CHECK-CF-RV64-NEXT: ld t0, 40(sp)
+; CHECK-CF-RV64-NEXT: ld t1, 32(sp)
+; CHECK-CF-RV64-NEXT: ld t2, 0(sp)
+; CHECK-CF-RV64-NEXT: ld t3, 8(sp)
+; CHECK-CF-RV64-NEXT: ld t4, 16(sp)
+; CHECK-CF-RV64-NEXT: ld t5, 24(sp)
+; CHECK-CF-RV64-NEXT: sd t2, 0(sp)
+; CHECK-CF-RV64-NEXT: sd t3, 8(sp)
+; CHECK-CF-RV64-NEXT: sd t4, 16(sp)
+; CHECK-CF-RV64-NEXT: sd t5, 24(sp)
+; CHECK-CF-RV64-NEXT: sd t1, 32(sp)
+; CHECK-CF-RV64-NEXT: sd t0, 40(sp)
+; CHECK-CF-RV64-NEXT: tail callee_args
;
; CHECK-CF-RV32-LARGE-LABEL: caller_args:
; CHECK-CF-RV32-LARGE: # %bb.0: # %entry
; CHECK-CF-RV32-LARGE-NEXT: lpad 0
-; CHECK-CF-RV32-LARGE-NEXT: addi sp, sp, -32
-; CHECK-CF-RV32-LARGE-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
-; CHECK-CF-RV32-LARGE-NEXT: lw t0, 32(sp)
-; CHECK-CF-RV32-LARGE-NEXT: lw t1, 36(sp)
-; CHECK-CF-RV32-LARGE-NEXT: lw t3, 40(sp)
-; CHECK-CF-RV32-LARGE-NEXT: lw t4, 44(sp)
-; CHECK-CF-RV32-LARGE-NEXT: lw t2, 48(sp)
-; CHECK-CF-RV32-LARGE-NEXT: lw t5, 52(sp)
-; CHECK-CF-RV32-LARGE-NEXT: sw t2, 16(sp)
-; CHECK-CF-RV32-LARGE-NEXT: sw t5, 20(sp)
+; CHECK-CF-RV32-LARGE-NEXT: lw t0, 20(sp)
+; CHECK-CF-RV32-LARGE-NEXT: lw t1, 16(sp)
+; CHECK-CF-RV32-LARGE-NEXT: lw t2, 0(sp)
+; CHECK-CF-RV32-LARGE-NEXT: lw t3, 12(sp)
+; CHECK-CF-RV32-LARGE-NEXT: lw t4, 8(sp)
+; CHECK-CF-RV32-LARGE-NEXT: lw t5, 4(sp)
+; CHECK-CF-RV32-LARGE-NEXT: sw t2, 0(sp)
; CHECK-CF-RV32-LARGE-NEXT: .Lpcrel_hi8:
; CHECK-CF-RV32-LARGE-NEXT: auipc t2, %pcrel_hi(.LCPI6_0)
; CHECK-CF-RV32-LARGE-NEXT: lw t2, %pcrel_lo(.Lpcrel_hi8)(t2)
-; CHECK-CF-RV32-LARGE-NEXT: sw t0, 0(sp)
-; CHECK-CF-RV32-LARGE-NEXT: sw t1, 4(sp)
-; CHECK-CF-RV32-LARGE-NEXT: sw t3, 8(sp)
-; CHECK-CF-RV32-LARGE-NEXT: sw t4, 12(sp)
-; CHECK-CF-RV32-LARGE-NEXT: jalr t2
-; CHECK-CF-RV32-LARGE-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; CHECK-CF-RV32-LARGE-NEXT: addi sp, sp, 32
-; CHECK-CF-RV32-LARGE-NEXT: ret
+; CHECK-CF-RV32-LARGE-NEXT: sw t5, 4(sp)
+; CHECK-CF-RV32-LARGE-NEXT: sw t4, 8(sp)
+; CHECK-CF-RV32-LARGE-NEXT: sw t3, 12(sp)
+; CHECK-CF-RV32-LARGE-NEXT: sw t1, 16(sp)
+; CHECK-CF-RV32-LARGE-NEXT: sw t0, 20(sp)
+; CHECK-CF-RV32-LARGE-NEXT: jr t2
;
; CHECK-CF-RV64-LARGE-LABEL: caller_args:
; CHECK-CF-RV64-LARGE: # %bb.0: # %entry
; CHECK-CF-RV64-LARGE-NEXT: lpad 0
-; CHECK-CF-RV64-LARGE-NEXT: addi sp, sp, -64
-; CHECK-CF-RV64-LARGE-NEXT: sd ra, 56(sp) # 8-byte Folded Spill
-; CHECK-CF-RV64-LARGE-NEXT: ld t0, 64(sp)
-; CHECK-CF-RV64-LARGE-NEXT: ld t1, 72(sp)
-; CHECK-CF-RV64-LARGE-NEXT: ld t3, 80(sp)
-; CHECK-CF-RV64-LARGE-NEXT: ld t4, 88(sp)
-; CHECK-CF-RV64-LARGE-NEXT: ld t2, 96(sp)
-; CHECK-CF-RV64-LARGE-NEXT: ld t5, 104(sp)
-; CHECK-CF-RV64-LARGE-NEXT: sd t2, 32(sp)
-; CHECK-CF-RV64-LARGE-NEXT: sd t5, 40(sp)
+; CHECK-CF-RV64-LARGE-NEXT: ld t0, 40(sp)
+; CHECK-CF-RV64-LARGE-NEXT: ld t1, 32(sp)
+; CHECK-CF-RV64-LARGE-NEXT: ld t2, 0(sp)
+; CHECK-CF-RV64-LARGE-NEXT: ld t3, 24(sp)
+; CHECK-CF-RV64-LARGE-NEXT: ld t4, 16(sp)
+; CHECK-CF-RV64-LARGE-NEXT: ld t5, 8(sp)
+; CHECK-CF-RV64-LARGE-NEXT: sd t2, 0(sp)
; CHECK-CF-RV64-LARGE-NEXT: .Lpcrel_hi8:
; CHECK-CF-RV64-LARGE-NEXT: auipc t2, %pcrel_hi(.LCPI6_0)
; CHECK-CF-RV64-LARGE-NEXT: ld t2, %pcrel_lo(.Lpcrel_hi8)(t2)
-; CHECK-CF-RV64-LARGE-NEXT: sd t0, 0(sp)
-; CHECK-CF-RV64-LARGE-NEXT: sd t1, 8(sp)
-; CHECK-CF-RV64-LARGE-NEXT: sd t3, 16(sp)
-; CHECK-CF-RV64-LARGE-NEXT: sd t4, 24(sp)
-; CHECK-CF-RV64-LARGE-NEXT: jalr t2
-; CHECK-CF-RV64-LARGE-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
-; CHECK-CF-RV64-LARGE-NEXT: addi sp, sp, 64
-; CHECK-CF-RV64-LARGE-NEXT: ret
+; CHECK-CF-RV64-LARGE-NEXT: sd t5, 8(sp)
+; CHECK-CF-RV64-LARGE-NEXT: sd t4, 16(sp)
+; CHECK-CF-RV64-LARGE-NEXT: sd t3, 24(sp)
+; CHECK-CF-RV64-LARGE-NEXT: sd t1, 32(sp)
+; CHECK-CF-RV64-LARGE-NEXT: sd t0, 40(sp)
+; CHECK-CF-RV64-LARGE-NEXT: jr t2
entry:
%r = tail call i32 @callee_args(i32 %a, i32 %b, i32 %c, i32 %dd, i32 %e, i32 %ff, i32 %g, i32 %h, i32 %i, i32 %j, i32 %k, i32 %l, i32 %m, i32 %n)
ret i32 %r
@@ -563,34 +538,28 @@ declare i32 @callee_indirect_args(fp128 %a)
define void @caller_indirect_args() nounwind {
; CHECK-LABEL: caller_indirect_args:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -32
-; CHECK-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: lui a1, 262128
; CHECK-NEXT: mv a0, sp
; CHECK-NEXT: sw zero, 0(sp)
; CHECK-NEXT: sw zero, 4(sp)
; CHECK-NEXT: sw zero, 8(sp)
; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: call callee_indirect_args
-; CHECK-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; CHECK-NEXT: addi sp, sp, 32
-; CHECK-NEXT: ret
+; CHECK-NEXT: addi sp, sp, 16
+; CHECK-NEXT: tail callee_indirect_args
;
; CHECK-CF-RV32-LABEL: caller_indirect_args:
; CHECK-CF-RV32: # %bb.0: # %entry
; CHECK-CF-RV32-NEXT: lpad 0
-; CHECK-CF-RV32-NEXT: addi sp, sp, -32
-; CHECK-CF-RV32-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; CHECK-CF-RV32-NEXT: addi sp, sp, -16
; CHECK-CF-RV32-NEXT: lui a1, 262128
; CHECK-CF-RV32-NEXT: mv a0, sp
; CHECK-CF-RV32-NEXT: sw zero, 0(sp)
; CHECK-CF-RV32-NEXT: sw zero, 4(sp)
; CHECK-CF-RV32-NEXT: sw zero, 8(sp)
; CHECK-CF-RV32-NEXT: sw a1, 12(sp)
-; CHECK-CF-RV32-NEXT: call callee_indirect_args
-; CHECK-CF-RV32-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; CHECK-CF-RV32-NEXT: addi sp, sp, 32
-; CHECK-CF-RV32-NEXT: ret
+; CHECK-CF-RV32-NEXT: addi sp, sp, 16
+; CHECK-CF-RV32-NEXT: tail callee_indirect_args
;
; CHECK-CF-RV64-LABEL: caller_indirect_args:
; CHECK-CF-RV64: # %bb.0: # %entry
@@ -603,8 +572,7 @@ define void @caller_indirect_args() nounwind {
; CHECK-CF-RV32-LARGE-LABEL: caller_indirect_args:
; CHECK-CF-RV32-LARGE: # %bb.0: # %entry
; CHECK-CF-RV32-LARGE-NEXT: lpad 0
-; CHECK-CF-RV32-LARGE-NEXT: addi sp, sp, -32
-; CHECK-CF-RV32-LARGE-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; CHECK-CF-RV32-LARGE-NEXT: addi sp, sp, -16
; CHECK-CF-RV32-LARGE-NEXT: lui a1, 262128
; CHECK-CF-RV32-LARGE-NEXT: .Lpcrel_hi9:
; CHECK-CF-RV32-LARGE-NEXT: auipc a0, %pcrel_hi(.LCPI7_0)
@@ -614,10 +582,8 @@ define void @caller_indirect_args() nounwind {
; CHECK-CF-RV32-LARGE-NEXT: sw zero, 4(sp)
; CHECK-CF-RV32-LARGE-NEXT: sw zero, 8(sp)
; CHECK-CF-RV32-LARGE-NEXT: sw a1, 12(sp)
-; CHECK-CF-RV32-LARGE-NEXT: jalr t2
-; CHECK-CF-RV32-LARGE-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; CHECK-CF-RV32-LARGE-NEXT: addi sp, sp, 32
-; CHECK-CF-RV32-LARGE-NEXT: ret
+; CHECK-CF-RV32-LARGE-NEXT: addi sp, sp, 16
+; CHECK-CF-RV32-LARGE-NEXT: jr t2
;
; CHECK-CF-RV64-LARGE-LABEL: caller_indirect_args:
; CHECK-CF-RV64-LARGE: # %bb.0: # %entry
>From 9d798ae81a47e22d69ff6f0cd87e50d43afbffa8 Mon Sep 17 00:00:00 2001
From: Kito Cheng <kito.cheng at sifive.com>
Date: Tue, 10 Mar 2026 09:36:19 +0800
Subject: [PATCH 6/7] !fixup Use NonX7 register classes unconditionally for
indirect calls/branches
Apply the NonX7 register class constraint to PseudoCALLIndirect,
PseudoTAILIndirect, and PseudoBRIND unconditionally, rather than only
when cf-protection-branch is enabled. This simplifies the LLVM code by
removing the separate NonX7 ISD nodes and pseudo instructions at a
negligible performance cost (one fewer register available for indirect
call/branch targets).
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 30 ++----------
llvm/lib/Target/RISCV/RISCVISelLowering.h | 1 -
llvm/lib/Target/RISCV/RISCVInstrInfo.td | 47 +++++++------------
.../lib/Target/RISCV/RISCVLandingPadSetup.cpp | 6 +--
.../instruction-select/brindirect-rv32.mir | 2 +-
.../instruction-select/brindirect-rv64.mir | 2 +-
.../RISCV/GlobalISel/irtranslator/calls.ll | 4 +-
llvm/test/CodeGen/RISCV/calls.ll | 4 +-
llvm/test/CodeGen/RISCV/cf-branch-isel.ll | 6 +--
llvm/test/CodeGen/RISCV/kcfi-isel-mir.ll | 4 +-
.../machine-outliner-call-reg-live-across.mir | 14 +++---
llvm/test/CodeGen/RISCV/opt-w-instrs.mir | 8 ++--
llvm/test/CodeGen/RISCV/pr97304.ll | 2 +-
.../CodeGen/RISCV/zicfilp-indirect-branch.ll | 6 +--
14 files changed, 51 insertions(+), 85 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 17ca9cfecd258..38bd8aaf789fe 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -317,7 +317,6 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::BR_JT, MVT::Other, Expand);
setOperationAction(ISD::BR_CC, XLenVT, Expand);
- setOperationAction(ISD::BRIND, MVT::Other, Custom);
setOperationAction(ISD::BRCOND, MVT::Other, Custom);
setOperationAction(ISD::SELECT_CC, XLenVT, Expand);
@@ -7892,8 +7891,6 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
return lowerSELECT(Op, DAG);
case ISD::BRCOND:
return lowerBRCOND(Op, DAG);
- case ISD::BRIND:
- return lowerBRIND(Op, DAG);
case ISD::VASTART:
return lowerVASTART(Op, DAG);
case ISD::FRAMEADDR:
@@ -10184,19 +10181,6 @@ SDValue RISCVTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
DAG.getCondCode(ISD::SETNE), Op.getOperand(2));
}
-SDValue RISCVTargetLowering::lowerBRIND(SDValue Op, SelectionDAG &DAG) const {
- // When cf-protection-branch is enabled, use BRIND_NONX7 to avoid using X7
- // for the target address, since X7 is reserved for landing pad labels.
- const MachineFunction &MF = DAG.getMachineFunction();
- if (!MF.getInfo<RISCVMachineFunctionInfo>()->hasCFProtectionBranch())
- return Op;
-
- SDLoc DL(Op);
- SDValue Chain = Op.getOperand(0);
- SDValue Addr = Op.getOperand(1);
- return DAG.getNode(RISCVISD::BRIND_NONX7, DL, Op.getValueType(), Chain, Addr);
-}
-
SDValue RISCVTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const {
MachineFunction &MF = DAG.getMachineFunction();
RISCVMachineFunctionInfo *FuncInfo = MF.getInfo<RISCVMachineFunctionInfo>();
@@ -24882,26 +24866,22 @@ SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI,
// Emit the call.
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
- // Determine which call opcode to use based on cf-protection-branch and
- // call type:
- // - SW_GUARDED_*: Large code model direct calls need X7 for landing pad label
- // - *_NONX7: Indirect calls with cf-protection must avoid X7
- // - Regular: No cf-protection or direct calls in non-large code model
+ // Determine which call opcode to use:
+ // - SW_GUARDED_*: Large code model direct calls with cf-protection-branch
+ // need X7 for landing pad label
+ // - Regular CALL/TAIL: All other cases. Indirect calls use NonX7 register
+ // classes unconditionally via tablegen patterns.
bool HasCFBranch =
MF.getInfo<RISCVMachineFunctionInfo>()->hasCFProtectionBranch();
bool IsIndirectCall = CLI.CB && CLI.CB->isIndirectCall();
bool NeedSWGuarded = getTargetMachine().getCodeModel() == CodeModel::Large &&
HasCFBranch &&
(!IsIndirectCall || CalleeIsLargeExternalSymbol);
- bool NeedNonX7 = HasCFBranch && IsIndirectCall;
unsigned TailOpc, CallOpc;
if (NeedSWGuarded) {
TailOpc = RISCVISD::SW_GUARDED_TAIL;
CallOpc = RISCVISD::SW_GUARDED_CALL;
- } else if (NeedNonX7) {
- TailOpc = RISCVISD::TAIL_NONX7;
- CallOpc = RISCVISD::CALL_NONX7;
} else {
TailOpc = RISCVISD::TAIL;
CallOpc = RISCVISD::CALL;
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index 10e77c5c5804a..8d88aeb7ae3fc 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -503,7 +503,6 @@ class RISCVTargetLowering : public TargetLowering {
SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
- SDValue lowerBRIND(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 0f5193fe0ae38..758b01abdd1cb 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -91,15 +91,6 @@ def riscv_brcc : RVSDNode<"BR_CC", SDT_RISCVBrCC,
def riscv_sw_guarded_brind : RVSDNode<"SW_GUARDED_BRIND",
SDTBrind, [SDNPHasChain]>;
-// NonX7 variants for cf-protection-branch. These avoid using X7 for indirect
-// branches/calls since X7 is used for landing pad labels.
-def riscv_brind_nonx7 : RVSDNode<"BRIND_NONX7", SDTBrind, [SDNPHasChain]>;
-def riscv_call_nonx7 : RVSDNode<"CALL_NONX7", SDT_RISCVCall,
- [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
- SDNPVariadic]>;
-def riscv_tail_nonx7 : RVSDNode<"TAIL_NONX7", SDT_RISCVCall,
- [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
- SDNPVariadic]>;
// RV64I shifts, directly matching the semantics of the named RISC-V
// instructions.
@@ -1772,26 +1763,22 @@ def PseudoBR : Pseudo<(outs), (ins simm21_lsb0_jal:$imm20), [(br bb:$imm20)]>,
PseudoInstExpansion<(JAL X0, simm21_lsb0_jal:$imm20)>;
let isBarrier = 1, isBranch = 1, isIndirectBranch = 1, isTerminator = 1 in {
-def PseudoBRIND : Pseudo<(outs), (ins GPRJALR:$rs1, simm12_lo:$imm12), []>,
+// Use GPRJALRNonX7 to avoid X7 which is reserved for landing pad labels
+// in cf-protection-branch. The NonX7 constraint is applied unconditionally
+// to simplify the code at a negligible performance cost.
+def PseudoBRIND : Pseudo<(outs), (ins GPRJALRNonX7:$rs1, simm12_lo:$imm12), []>,
PseudoInstExpansion<(JALR X0, GPR:$rs1, simm12_lo:$imm12)>;
-def PseudoBRINDNonX7 : Pseudo<(outs), (ins GPRJALRNonX7:$rs1, simm12_lo:$imm12), []>,
- PseudoInstExpansion<(JALR X0, GPR:$rs1, simm12_lo:$imm12)>;
def PseudoBRINDX7 : Pseudo<(outs), (ins GPRX7:$rs1, simm12_lo:$imm12), []>,
PseudoInstExpansion<(JALR X0, GPR:$rs1, simm12_lo:$imm12)>;
}
-def : Pat<(riscv_brind_nonx7 GPRJALRNonX7:$rs1),
- (PseudoBRINDNonX7 GPRJALRNonX7:$rs1, 0)>;
-def : Pat<(riscv_brind_nonx7 (add GPRJALRNonX7:$rs1, simm12_lo:$imm12)),
- (PseudoBRINDNonX7 GPRJALRNonX7:$rs1, simm12_lo:$imm12)>;
-
def : Pat<(riscv_sw_guarded_brind GPRX7:$rs1), (PseudoBRINDX7 GPRX7:$rs1, 0)>;
def : Pat<(riscv_sw_guarded_brind (add GPRX7:$rs1, simm12_lo:$imm12)),
(PseudoBRINDX7 GPRX7:$rs1, simm12_lo:$imm12)>;
-def : Pat<(brind GPRJALR:$rs1), (PseudoBRIND GPRJALR:$rs1, 0)>;
-def : Pat<(brind (add GPRJALR:$rs1, simm12_lo:$imm12)),
- (PseudoBRIND GPRJALR:$rs1, simm12_lo:$imm12)>;
+def : Pat<(brind GPRJALRNonX7:$rs1), (PseudoBRIND GPRJALRNonX7:$rs1, 0)>;
+def : Pat<(brind (add GPRJALRNonX7:$rs1, simm12_lo:$imm12)),
+ (PseudoBRIND GPRJALRNonX7:$rs1, simm12_lo:$imm12)>;
// PseudoCALLReg is a generic pseudo instruction for calls which will eventually
// expand to auipc and jalr while encoding, with any given register used as the
@@ -1824,12 +1811,12 @@ let Predicates = [HasStdExtSmrnmi] in
def : Pat<(riscv_mnret_glue), (MNRET)>;
let isCall = 1, Defs = [X1] in {
-def PseudoCALLIndirect : Pseudo<(outs), (ins GPRJALR:$rs1),
- [(riscv_call GPRJALR:$rs1)]>,
+// Use GPRJALRNonX7 to avoid X7 which is reserved for landing pad labels
+// in cf-protection-branch. The NonX7 constraint is applied unconditionally
+// to simplify the code at a negligible performance cost.
+def PseudoCALLIndirect : Pseudo<(outs), (ins GPRJALRNonX7:$rs1),
+ [(riscv_call GPRJALRNonX7:$rs1)]>,
PseudoInstExpansion<(JALR X1, GPR:$rs1, 0)>;
-def PseudoCALLIndirectNonX7 : Pseudo<(outs), (ins GPRJALRNonX7:$rs1),
- [(riscv_call_nonx7 GPRJALRNonX7:$rs1)]>,
- PseudoInstExpansion<(JALR X1, GPR:$rs1, 0)>;
def PseudoCALLIndirectX7 : Pseudo<(outs), (ins GPRX7:$rs1),
[(riscv_sw_guarded_call GPRX7:$rs1)]>,
PseudoInstExpansion<(JALR X1, GPR:$rs1, 0)>;
@@ -1849,12 +1836,12 @@ def PseudoTAIL : Pseudo<(outs), (ins call_symbol:$dst), [],
Sched<[WriteIALU, WriteJalr, ReadJalr]>;
let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [X2] in {
-def PseudoTAILIndirect : Pseudo<(outs), (ins GPRTC:$rs1),
- [(riscv_tail GPRTC:$rs1)]>,
+// Use GPRTCNonX7 to avoid X7 which is reserved for landing pad labels
+// in cf-protection-branch. The NonX7 constraint is applied unconditionally
+// to simplify the code at a negligible performance cost.
+def PseudoTAILIndirect : Pseudo<(outs), (ins GPRTCNonX7:$rs1),
+ [(riscv_tail GPRTCNonX7:$rs1)]>,
PseudoInstExpansion<(JALR X0, GPR:$rs1, 0)>;
-def PseudoTAILIndirectNonX7 : Pseudo<(outs), (ins GPRTCNonX7:$rs1),
- [(riscv_tail_nonx7 GPRTCNonX7:$rs1)]>,
- PseudoInstExpansion<(JALR X0, GPR:$rs1, 0)>;
def PseudoTAILIndirectX7 : Pseudo<(outs), (ins GPRX7:$rs1),
[(riscv_sw_guarded_tail GPRX7:$rs1)]>,
PseudoInstExpansion<(JALR X0, GPR:$rs1, 0)>;
diff --git a/llvm/lib/Target/RISCV/RISCVLandingPadSetup.cpp b/llvm/lib/Target/RISCV/RISCVLandingPadSetup.cpp
index 089ffb4edaf39..986f5da398b4b 100644
--- a/llvm/lib/Target/RISCV/RISCVLandingPadSetup.cpp
+++ b/llvm/lib/Target/RISCV/RISCVLandingPadSetup.cpp
@@ -67,9 +67,9 @@ bool RISCVLandingPadSetup::runOnMachineFunction(MachineFunction &MF) {
bool Changed = false;
for (MachineBasicBlock &MBB : MF)
for (MachineInstr &MI : llvm::make_early_inc_range(MBB)) {
- if (MI.getOpcode() != RISCV::PseudoBRINDNonX7 &&
- MI.getOpcode() != RISCV::PseudoCALLIndirectNonX7 &&
- MI.getOpcode() != RISCV::PseudoTAILIndirectNonX7)
+ if (MI.getOpcode() != RISCV::PseudoBRIND &&
+ MI.getOpcode() != RISCV::PseudoCALLIndirect &&
+ MI.getOpcode() != RISCV::PseudoTAILIndirect)
continue;
BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(RISCV::LUI), RISCV::X7)
.addImm(Label);
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/brindirect-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/brindirect-rv32.mir
index 79b9a352a8ead..b159ba64ca515 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/brindirect-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/brindirect-rv32.mir
@@ -13,7 +13,7 @@ body: |
; RV32I-NEXT: successors: %bb.1, %bb.2
; RV32I-NEXT: liveins: $x10
; RV32I-NEXT: {{ $}}
- ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprjalr = COPY $x10
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprjalrnonx7 = COPY $x10
; RV32I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1
; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0
; RV32I-NEXT: PseudoBRIND [[COPY]], 0
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/brindirect-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/brindirect-rv64.mir
index eb1bf20b82cd2..27419b24904f2 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/brindirect-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/brindirect-rv64.mir
@@ -13,7 +13,7 @@ body: |
; RV64I-NEXT: successors: %bb.1, %bb.2
; RV64I-NEXT: liveins: $x10
; RV64I-NEXT: {{ $}}
- ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprjalr = COPY $x10
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprjalrnonx7 = COPY $x10
; RV64I-NEXT: PseudoBRIND [[COPY]], 0
; RV64I-NEXT: {{ $}}
; RV64I-NEXT: bb.1:
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calls.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calls.ll
index 34e29718d0e9a..8a2f54691c088 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calls.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calls.ll
@@ -422,7 +422,7 @@ define void @test_indirect_call(ptr %func) {
; RV32I: bb.1 (%ir-block.0):
; RV32I-NEXT: liveins: $x10
; RV32I-NEXT: {{ $}}
- ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprjalr(p0) = COPY $x10
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprjalrnonx7(p0) = COPY $x10
; RV32I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
; RV32I-NEXT: PseudoCALLIndirect [[COPY]](p0), csr_ilp32_lp64, implicit-def $x1
; RV32I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
@@ -432,7 +432,7 @@ define void @test_indirect_call(ptr %func) {
; RV64I: bb.1 (%ir-block.0):
; RV64I-NEXT: liveins: $x10
; RV64I-NEXT: {{ $}}
- ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprjalr(p0) = COPY $x10
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprjalrnonx7(p0) = COPY $x10
; RV64I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
; RV64I-NEXT: PseudoCALLIndirect [[COPY]](p0), csr_ilp32_lp64, implicit-def $x1
; RV64I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
diff --git a/llvm/test/CodeGen/RISCV/calls.ll b/llvm/test/CodeGen/RISCV/calls.ll
index 7637978c40f78..8bd80100de0da 100644
--- a/llvm/test/CodeGen/RISCV/calls.ll
+++ b/llvm/test/CodeGen/RISCV/calls.ll
@@ -838,13 +838,13 @@ define fastcc void @fastcc_call_nonfastcc(){
; RV64I-LARGE-NEXT: li a2, 3
; RV64I-LARGE-NEXT: li a3, 4
; RV64I-LARGE-NEXT: li a4, 5
-; RV64I-LARGE-NEXT: ld t2, %pcrel_lo(.Lpcrel_hi6)(a5)
+; RV64I-LARGE-NEXT: ld t3, %pcrel_lo(.Lpcrel_hi6)(a5)
; RV64I-LARGE-NEXT: li a5, 6
; RV64I-LARGE-NEXT: li a6, 7
; RV64I-LARGE-NEXT: li a7, 8
; RV64I-LARGE-NEXT: sd t1, 0(sp)
; RV64I-LARGE-NEXT: sd t0, 8(sp)
-; RV64I-LARGE-NEXT: jalr t2
+; RV64I-LARGE-NEXT: jalr t3
; RV64I-LARGE-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-LARGE-NEXT: .cfi_restore ra
; RV64I-LARGE-NEXT: addi sp, sp, 32
diff --git a/llvm/test/CodeGen/RISCV/cf-branch-isel.ll b/llvm/test/CodeGen/RISCV/cf-branch-isel.ll
index fc5d0277af71b..ebaae4cfd49b8 100644
--- a/llvm/test/CodeGen/RISCV/cf-branch-isel.ll
+++ b/llvm/test/CodeGen/RISCV/cf-branch-isel.ll
@@ -9,7 +9,7 @@
define void @brind(i32 noundef signext %0) {
; CHECK-LABEL: name: brind
- ; CHECK: PseudoBRINDNonX7 killed %{{[0-9]+}}, 0
+ ; CHECK: PseudoBRIND killed %{{[0-9]+}}, 0
%2 = sext i32 %0 to i64
%3 = getelementptr inbounds [2 x ptr], ptr @brind.arr, i64 0, i64 %2
%4 = load ptr, ptr %3, align 8
@@ -30,14 +30,14 @@ bb2:
define i32 @indirect_call(ptr %0) {
; CHECK-LABEL: name: indirect_call
- ; CHECK: PseudoCALLIndirectNonX7
+ ; CHECK: PseudoCALLIndirect
call void %0()
ret i32 0
}
define void @indirect_tail(ptr %0) {
; CHECK-LABEL: name: indirect_tail
- ; CHECK: PseudoTAILIndirectNonX7
+ ; CHECK: PseudoTAILIndirect
tail call void %0()
ret void
}
diff --git a/llvm/test/CodeGen/RISCV/kcfi-isel-mir.ll b/llvm/test/CodeGen/RISCV/kcfi-isel-mir.ll
index 2c428cf4ac87c..97bf32434e701 100644
--- a/llvm/test/CodeGen/RISCV/kcfi-isel-mir.ll
+++ b/llvm/test/CodeGen/RISCV/kcfi-isel-mir.ll
@@ -5,7 +5,7 @@ define void @f1(ptr noundef %x) !kcfi_type !1 {
; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: liveins: $x10
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprjalr = COPY $x10
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprjalrnonx7 = COPY $x10
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $x2, implicit $x2
; CHECK-NEXT: PseudoCALLIndirect [[COPY]], csr_ilp32_lp64, implicit-def dead $x1, implicit-def $x2, cfi-type 12345678
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $x2, implicit $x2
@@ -19,7 +19,7 @@ define void @f2(ptr noundef %x) #0 {
; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: liveins: $x10
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprtc = COPY $x10
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprtcnonx7 = COPY $x10
; CHECK-NEXT: PseudoTAILIndirect [[COPY]], csr_ilp32_lp64, implicit $x2, cfi-type 12345678
tail call void %x() [ "kcfi"(i32 12345678) ]
ret void
diff --git a/llvm/test/CodeGen/RISCV/machine-outliner-call-reg-live-across.mir b/llvm/test/CodeGen/RISCV/machine-outliner-call-reg-live-across.mir
index 4e771d25cfedf..3a7f2ed477ef4 100644
--- a/llvm/test/CodeGen/RISCV/machine-outliner-call-reg-live-across.mir
+++ b/llvm/test/CodeGen/RISCV/machine-outliner-call-reg-live-across.mir
@@ -20,7 +20,7 @@
; CHECK-NEXT: lw a5, 32(sp)
; CHECK-NEXT: li a6, 1
; CHECK-NEXT: li a7, 1
- ; CHECK-NEXT: li t2, 0
+ ; CHECK-NEXT: li t3, 0
; CHECK-NEXT: mv a2, a0
; CHECK-NEXT: mv a3, t1
; CHECK-NEXT: tail OUTLINED_FUNCTION_0
@@ -52,7 +52,7 @@
; CHECK-NEXT: lw a5, 32(sp)
; CHECK-NEXT: li a6, 1
; CHECK-NEXT: li a7, 1
- ; CHECK-NEXT: li t2, 0
+ ; CHECK-NEXT: li t3, 0
; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: mv a3, t1
; CHECK-NEXT: tail OUTLINED_FUNCTION_0
@@ -70,7 +70,7 @@
; CHECK-LABEL: OUTLINED_FUNCTION_0:
; CHECK: # %bb.0:
; CHECK-NEXT: mv a4, t0
- ; CHECK-NEXT: jalr t2
+ ; CHECK-NEXT: jalr t3
; CHECK-NEXT: sw s3, 0(s1)
; CHECK-NEXT: li a0, 1
; CHECK-NEXT: sw s2, 0(s0)
@@ -202,11 +202,11 @@ body: |
renamable $x15 = LW $x2, 32 :: (load (s32) from %fixed-stack.4, align 16)
$x16 = ADDI $x0, 1
$x17 = ADDI $x0, 1
- $x7 = ADDI $x0, 0
+ $x28 = ADDI $x0, 0
$x12 = ADDI renamable $x10, 0
$x13 = ADDI killed renamable $x6, 0
$x14 = ADDI killed renamable $x5, 0
- PseudoCALLIndirect killed renamable $x7, csr_ilp32_lp64, implicit-def dead $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit-def $x2, implicit-def dead $x10
+ PseudoCALLIndirect killed renamable $x28, csr_ilp32_lp64, implicit-def dead $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit-def $x2, implicit-def dead $x10
SW killed renamable $x19, killed renamable $x9, 0 :: (store (s32) into %ir.var3)
$x10 = ADDI $x0, 1
SW killed renamable $x18, killed renamable $x8, 0 :: (store (s32) into %ir.var7)
@@ -336,11 +336,11 @@ body: |
renamable $x15 = LW $x2, 32 :: (load (s32) from %fixed-stack.4, align 16)
$x16 = ADDI $x0, 1
$x17 = ADDI $x0, 1
- $x7 = ADDI $x0, 0
+ $x28 = ADDI $x0, 0
$x11 = ADDI renamable $x10, 0
$x13 = ADDI killed renamable $x6, 0
$x14 = ADDI killed renamable $x5, 0
- PseudoCALLIndirect killed renamable $x7, csr_ilp32_lp64, implicit-def dead $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit-def $x2, implicit-def dead $x10
+ PseudoCALLIndirect killed renamable $x28, csr_ilp32_lp64, implicit-def dead $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit-def $x2, implicit-def dead $x10
SW killed renamable $x19, killed renamable $x9, 0 :: (store (s32) into %ir.var3)
$x10 = ADDI $x0, 1
SW killed renamable $x18, killed renamable $x8, 0 :: (store (s32) into %ir.var7)
diff --git a/llvm/test/CodeGen/RISCV/opt-w-instrs.mir b/llvm/test/CodeGen/RISCV/opt-w-instrs.mir
index 47407c2270ead..a7f2d95f4ef5c 100644
--- a/llvm/test/CodeGen/RISCV/opt-w-instrs.mir
+++ b/llvm/test/CodeGen/RISCV/opt-w-instrs.mir
@@ -192,7 +192,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[ADDI]], %bb.0, [[LW]], %bb.1
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprtc = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprtcnonx7 = COPY $x0
; CHECK-NEXT: $x10 = COPY [[COPY1]]
; CHECK-NEXT: $x11 = COPY [[PHI]]
; CHECK-NEXT: PseudoTAILIndirect [[COPY1]], csr_ilp32_lp64, implicit $x2, implicit $x10, implicit $x11
@@ -212,7 +212,7 @@ body: |
bb.2:
%1:gpr = PHI %3, %bb.0, %0, %bb.1
%6:gpr = ADDIW %1, 0
- %7:gprtc = COPY $x0
+ %7:gprtcnonx7 = COPY $x0
$x10 = COPY %7
$x11 = COPY %6
PseudoTAILIndirect %7, csr_ilp32_lp64, implicit $x2, implicit $x10, implicit $x11
@@ -240,7 +240,7 @@ body: |
; CHECK-NEXT: bb.2:
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
; CHECK-NEXT: $x10 = COPY [[ADDIW]]
- ; CHECK-NEXT: %call_target_dummy:gprjalr = COPY $x0
+ ; CHECK-NEXT: %call_target_dummy:gprjalrnonx7 = COPY $x0
; CHECK-NEXT: PseudoCALLIndirect %call_target_dummy, csr_ilp32_lp64, implicit-def $x1, implicit $x10
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
; CHECK-NEXT: $x10 = COPY [[LWU]]
@@ -260,7 +260,7 @@ body: |
bb.2:
ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
$x10 = COPY %16
- %call_target_dummy:gprjalr = COPY $x0
+ %call_target_dummy:gprjalrnonx7 = COPY $x0
PseudoCALLIndirect %call_target_dummy, csr_ilp32_lp64, implicit-def $x1, implicit $x10
ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
diff --git a/llvm/test/CodeGen/RISCV/pr97304.ll b/llvm/test/CodeGen/RISCV/pr97304.ll
index 694f6384b6855..c12e02deeeb80 100644
--- a/llvm/test/CodeGen/RISCV/pr97304.ll
+++ b/llvm/test/CodeGen/RISCV/pr97304.ll
@@ -16,7 +16,7 @@ define i32 @_ZNK2cv12LMSolverImpl3runERKNS_17_InputOutputArrayE(i1 %cmp436) {
; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY1]], 1
; CHECK-NEXT: ADJCALLSTACKDOWN 8, 0, implicit-def dead $x2, implicit $x2
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gprjalr = COPY $x0
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gprjalrnonx7 = COPY $x0
; CHECK-NEXT: SD [[COPY3]], [[COPY2]], 0 :: (store (s64) into stack)
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1
; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 32
diff --git a/llvm/test/CodeGen/RISCV/zicfilp-indirect-branch.ll b/llvm/test/CodeGen/RISCV/zicfilp-indirect-branch.ll
index 7f7c8fcd380d3..7384f48ee53b5 100644
--- a/llvm/test/CodeGen/RISCV/zicfilp-indirect-branch.ll
+++ b/llvm/test/CodeGen/RISCV/zicfilp-indirect-branch.ll
@@ -11,7 +11,7 @@
define void @brind(i32 noundef signext %0) {
; CHECK-LABEL: name: brind
- ; CHECK: PseudoBRINDNonX7 killed [[VAR:%.*]], 0
+ ; CHECK: PseudoBRIND killed [[VAR:%.*]], 0
%2 = sext i32 %0 to i64
%3 = getelementptr inbounds [2 x ptr], ptr @brind.arr, i64 0, i64 %2
%4 = load ptr, ptr %3, align 8
@@ -32,7 +32,7 @@ define void @brind(i32 noundef signext %0) {
define i32 @indirect_call(ptr %0) {
; CHECK-LABEL: name: indirect_call
- ; CHECK: PseudoCALLIndirectNonX7
+ ; CHECK: PseudoCALLIndirect
call void %0()
ret i32 0
}
@@ -40,7 +40,7 @@ define i32 @indirect_call(ptr %0) {
define void @indirect_tail(ptr %0) {
; CHECK-LABEL: name: indirect_tail
- ; CHECK: PseudoTAILIndirectNonX7
+ ; CHECK: PseudoTAILIndirect
tail call void %0()
ret void
}
>From 24e53263a55bc95d70cd5dee8bd7b409ebb7bc5d Mon Sep 17 00:00:00 2001
From: Kito Cheng <kito.cheng at sifive.com>
Date: Tue, 10 Mar 2026 14:52:02 +0800
Subject: [PATCH 7/7] !fixup
---
llvm/lib/Target/RISCV/RISCVInstrInfo.td | 1 -
1 file changed, 1 deletion(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 758b01abdd1cb..b8c726680ebfd 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -91,7 +91,6 @@ def riscv_brcc : RVSDNode<"BR_CC", SDT_RISCVBrCC,
def riscv_sw_guarded_brind : RVSDNode<"SW_GUARDED_BRIND",
SDTBrind, [SDNPHasChain]>;
-
// RV64I shifts, directly matching the semantics of the named RISC-V
// instructions.
def riscv_sllw : RVSDNode<"SLLW", SDT_RISCVIntBinOpW>;
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