[llvm] [X86] Fix assertion when lowering FP_ROUND (PR #185562)

[Aiden Grossman via llvm-commits]

https://github.com/boomanaiden154 created https://github.com/llvm/llvm-project/pull/185562

443ce5569ee9854cfef1139cf6b9cf05165e0902 caused us to start hitting assertions with non-standard vector widths (<3 x float>) in this case now that node types are actually enforced. There was a place in X86ISelLowering.cpp where we just passed along a 64-bit integer whereas other places constructing a CVTPS2PH node specifically construct a new integer.

>From 3dc591bdb8f15c5b31bf646b439ffff6a2edbaaa Mon Sep 17 00:00:00 2001
From: Aiden Grossman <aidengrossman at google.com>
Date: Tue, 10 Mar 2026 03:01:03 +0000
Subject: [PATCH] [X86] Fix assertion when lowering FP_ROUND

443ce5569ee9854cfef1139cf6b9cf05165e0902 caused us to start hitting
assertions with non-standard vector widths (<3 x float>) in this case
now that node types are actually enforced. There was a place in
X86ISelLowering.cpp where we just passed along a 64-bit integer whereas
other places constructing a CVTPS2PH node specifically construct a new
integer.
---
 llvm/lib/Target/X86/X86ISelLowering.cpp       | 10 ++++--
 .../CodeGen/X86/vector-half-conversions.ll    | 34 +++++++++++++++++++
 2 files changed, 41 insertions(+), 3 deletions(-)

diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 4ce343922a02e..48f4e71f3c514 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -35390,10 +35390,14 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
         return;
 
       if (IsStrict)
-        V = DAG.getNode(X86ISD::STRICT_CVTPS2PH, dl, {MVT::v8i16, MVT::Other},
-                        {Chain, Src, Rnd});
+        V = DAG.getNode(
+            X86ISD::STRICT_CVTPS2PH, dl, {MVT::v8i16, MVT::Other},
+            {Chain, Src,
+             DAG.getTargetConstant(Rnd->getAsZExtVal(), dl, MVT::i32)});
       else
-        V = DAG.getNode(X86ISD::CVTPS2PH, dl, MVT::v8i16, Src, Rnd);
+        V = DAG.getNode(
+            X86ISD::CVTPS2PH, dl, MVT::v8i16, Src,
+            DAG.getTargetConstant(Rnd->getAsZExtVal(), dl, MVT::i32));
 
       Results.push_back(DAG.getBitcast(MVT::v8f16, V));
       if (IsStrict)
diff --git a/llvm/test/CodeGen/X86/vector-half-conversions.ll b/llvm/test/CodeGen/X86/vector-half-conversions.ll
index 2fd0a96a6e4b0..3121856e7e07b 100644
--- a/llvm/test/CodeGen/X86/vector-half-conversions.ll
+++ b/llvm/test/CodeGen/X86/vector-half-conversions.ll
@@ -2178,6 +2178,40 @@ define <4 x i16> @cvt_4f32_to_4i16(<4 x float> %a0) nounwind {
   ret <4 x i16> %2
 }
 
+define <3 x half> @cvt_3f32_to_3f16(<3 x float> %a0) nounwind {
+; AVX-LABEL: cvt_3f32_to_3f16:
+; AVX:       # %bb.0:
+; AVX-NEXT:    subq $56, %rsp
+; AVX-NEXT:    vmovapd %xmm0, (%rsp) # 16-byte Spill
+; AVX-NEXT:    vshufpd {{.*#+}} xmm0 = xmm0[1,0]
+; AVX-NEXT:    callq __truncsfhf2 at PLT
+; AVX-NEXT:    vmovapd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; AVX-NEXT:    vmovshdup (%rsp), %xmm0 # 16-byte Folded Reload
+; AVX-NEXT:    # xmm0 = mem[1,1,3,3]
+; AVX-NEXT:    callq __truncsfhf2 at PLT
+; AVX-NEXT:    vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; AVX-NEXT:    vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; AVX-NEXT:    callq __truncsfhf2 at PLT
+; AVX-NEXT:    vpunpcklwd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 16-byte Folded Reload
+; AVX-NEXT:    # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1],xmm0[2],mem[2],xmm0[3],mem[3]
+; AVX-NEXT:    vinsertps $28, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 16-byte Folded Reload
+; AVX-NEXT:    # xmm0 = xmm0[0],mem[0],zero,zero
+; AVX-NEXT:    addq $56, %rsp
+; AVX-NEXT:    retq
+;
+; F16C-LABEL: cvt_3f32_to_3f16:
+; F16C:       # %bb.0:
+; F16C-NEXT:    vcvtps2ph $0, %xmm0, %xmm0
+; F16C-NEXT:    retq
+;
+; AVX512-LABEL: cvt_3f32_to_3f16:
+; AVX512:       # %bb.0:
+; AVX512-NEXT:    vcvtps2ph $0, %xmm0, %xmm0
+; AVX512-NEXT:    retq
+  %1 = fptrunc <3 x float> %a0 to <3 x half>
+  ret <3 x half> %1
+}
+
 define <8 x i16> @cvt_4f32_to_8i16_undef(<4 x float> %a0) nounwind {
 ; AVX-LABEL: cvt_4f32_to_8i16_undef:
 ; AVX:       # %bb.0: