[llvm] [BOLT][AArch64] Add minimal support for liveness analysis. (PR #183298)

[Paschalis Mpeis via llvm-commits]

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@@ -1238,6 +1239,19 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
     return true;
   }
 
+  BitVector getRegsUsedAsParams() const override {
+    BitVector Regs = BitVector(RegInfo->getNumRegs(), false);
+    Regs |= getAliases(AArch64::X0);
+    Regs |= getAliases(AArch64::X1);
+    Regs |= getAliases(AArch64::X2);
+    Regs |= getAliases(AArch64::X3);
+    Regs |= getAliases(AArch64::X4);
+    Regs |= getAliases(AArch64::X5);
+    Regs |= getAliases(AArch64::X6);
+    Regs |= getAliases(AArch64::X7);
+    return Regs;
+  }
+
   void getCalleeSavedRegs(BitVector &Regs) const override {
     Regs |= getAliases(AArch64::X18);
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paschalis-mpeis wrote:

Unrelated to this patch but `x18` is platform dependent.

IIRC, on Android x18 is reserved as the thread register and LLVM excludes r9/x18 from regalloc. 
For liveness, we might already be conservative in this case, but we should double check and handle it properly.

https://github.com/llvm/llvm-project/pull/183298