[llvm] AMDGPU/GlobalISel: Lower G_EXTRACT in legalizer (PR #181036)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 9 09:15:42 PDT 2026
https://github.com/vangthao95 updated https://github.com/llvm/llvm-project/pull/181036
>From c620ec34daef8c9331d3a050da1ebe7fe6968a44 Mon Sep 17 00:00:00 2001
From: Vang Thao <vang.thao at amd.com>
Date: Wed, 11 Feb 2026 14:23:14 -0800
Subject: [PATCH 1/6] AMDGPU/GlobalISel: Regbanklegalize rules for G_EXTRACT
---
.../AMDGPU/AMDGPURegBankLegalizeHelper.cpp | 14 +++++
.../AMDGPU/AMDGPURegBankLegalizeRules.cpp | 19 ++++++
.../AMDGPU/AMDGPURegBankLegalizeRules.h | 8 +++
.../GlobalISel/regbankselect-extract.mir | 61 +++++++++++++++++--
.../GlobalISel/regbankselect-merge-values.mir | 21 +++----
.../test/CodeGen/AMDGPU/addrspacecast.gfx6.ll | 2 +-
6 files changed, 108 insertions(+), 17 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
index d262f074679a8..8528acc76e703 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
@@ -1095,6 +1095,9 @@ LLT RegBankLegalizeHelper::getTyFromID(RegBankLLTMappingApplyID ID) {
case Sgpr128:
case Vgpr128:
return LLT::scalar(128);
+ case Sgpr1024:
+ case Vgpr1024:
+ return LLT::scalar(1024);
case SgprP0:
case VgprP0:
return LLT::pointer(0, 64);
@@ -1113,6 +1116,8 @@ LLT RegBankLegalizeHelper::getTyFromID(RegBankLLTMappingApplyID ID) {
case SgprP5:
case VgprP5:
return LLT::pointer(5, 32);
+ case SgprP6:
+ return LLT::pointer(6, 32);
case SgprP8:
return LLT::pointer(8, 128);
case SgprV2S16:
@@ -1227,12 +1232,14 @@ RegBankLegalizeHelper::getRegBankFromID(RegBankLLTMappingApplyID ID) {
case Sgpr32_WF:
case Sgpr64:
case Sgpr128:
+ case Sgpr1024:
case SgprP0:
case SgprP1:
case SgprP2:
case SgprP3:
case SgprP4:
case SgprP5:
+ case SgprP6:
case SgprP8:
case SgprPtr32:
case SgprPtr64:
@@ -1273,6 +1280,7 @@ RegBankLegalizeHelper::getRegBankFromID(RegBankLLTMappingApplyID ID) {
case Vgpr32:
case Vgpr64:
case Vgpr128:
+ case Vgpr1024:
case VgprP0:
case VgprP1:
case VgprP2:
@@ -1323,11 +1331,13 @@ bool RegBankLegalizeHelper::applyMappingDst(
case Sgpr32:
case Sgpr64:
case Sgpr128:
+ case Sgpr1024:
case SgprP0:
case SgprP1:
case SgprP3:
case SgprP4:
case SgprP5:
+ case SgprP6:
case SgprP8:
case SgprV2S16:
case SgprV2S32:
@@ -1336,6 +1346,7 @@ bool RegBankLegalizeHelper::applyMappingDst(
case Vgpr32:
case Vgpr64:
case Vgpr128:
+ case Vgpr1024:
case VgprP0:
case VgprP1:
case VgprP2:
@@ -1486,11 +1497,13 @@ bool RegBankLegalizeHelper::applyMappingSrc(
case Sgpr32:
case Sgpr64:
case Sgpr128:
+ case Sgpr1024:
case SgprP0:
case SgprP1:
case SgprP3:
case SgprP4:
case SgprP5:
+ case SgprP6:
case SgprP8:
case SgprV2S16:
case SgprV2S32:
@@ -1519,6 +1532,7 @@ bool RegBankLegalizeHelper::applyMappingSrc(
case Vgpr32:
case Vgpr64:
case Vgpr128:
+ case Vgpr1024:
case VgprP0:
case VgprP1:
case VgprP2:
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index a0be07d7eae05..5f5c615752fa7 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -56,6 +56,8 @@ bool matchUniformityAndLLT(Register Reg, UniformityLLTOpPredicateID UniID,
return MRI.getType(Reg) == LLT::scalar(64);
case S128:
return MRI.getType(Reg) == LLT::scalar(128);
+ case S1024:
+ return MRI.getType(Reg) == LLT::scalar(1024);
case P0:
return MRI.getType(Reg) == LLT::pointer(0, 64);
case P1:
@@ -68,6 +70,8 @@ bool matchUniformityAndLLT(Register Reg, UniformityLLTOpPredicateID UniID,
return MRI.getType(Reg) == LLT::pointer(4, 64);
case P5:
return MRI.getType(Reg) == LLT::pointer(5, 32);
+ case P6:
+ return MRI.getType(Reg) == LLT::pointer(6, 32);
case P8:
return MRI.getType(Reg) == LLT::pointer(8, 128);
case Ptr32:
@@ -108,6 +112,8 @@ bool matchUniformityAndLLT(Register Reg, UniformityLLTOpPredicateID UniID,
return MRI.getType(Reg) == LLT::scalar(64) && MUI.isUniform(Reg);
case UniS128:
return MRI.getType(Reg) == LLT::scalar(128) && MUI.isUniform(Reg);
+ case UniS1024:
+ return MRI.getType(Reg) == LLT::scalar(1024) && MUI.isUniform(Reg);
case UniP0:
return MRI.getType(Reg) == LLT::pointer(0, 64) && MUI.isUniform(Reg);
case UniP1:
@@ -120,6 +126,8 @@ bool matchUniformityAndLLT(Register Reg, UniformityLLTOpPredicateID UniID,
return MRI.getType(Reg) == LLT::pointer(4, 64) && MUI.isUniform(Reg);
case UniP5:
return MRI.getType(Reg) == LLT::pointer(5, 32) && MUI.isUniform(Reg);
+ case UniP6:
+ return MRI.getType(Reg) == LLT::pointer(6, 32) && MUI.isUniform(Reg);
case UniP8:
return MRI.getType(Reg) == LLT::pointer(8, 128) && MUI.isUniform(Reg);
case UniPtr32:
@@ -167,6 +175,8 @@ bool matchUniformityAndLLT(Register Reg, UniformityLLTOpPredicateID UniID,
return MRI.getType(Reg) == LLT::scalar(64) && MUI.isDivergent(Reg);
case DivS128:
return MRI.getType(Reg) == LLT::scalar(128) && MUI.isDivergent(Reg);
+ case DivS1024:
+ return MRI.getType(Reg) == LLT::scalar(1024) && MUI.isDivergent(Reg);
case DivP0:
return MRI.getType(Reg) == LLT::pointer(0, 64) && MUI.isDivergent(Reg);
case DivP1:
@@ -644,6 +654,15 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
.Any({{UniBRC}, {{}, {}, VerifyAllSgpr}})
.Any({{DivBRC}, {{}, {}, ApplyAllVgpr}});
+ addRulesForGOpcs({G_EXTRACT})
+ .Any({{UniS32, S64}, {{Sgpr32}, {Sgpr64}}})
+ .Any({{DivS32, S64}, {{Vgpr32}, {Vgpr64}}})
+ .Any({{UniS32, S1024}, {{Sgpr32}, {Sgpr1024}}})
+ .Any({{DivS32, S1024}, {{Vgpr32}, {Vgpr1024}}})
+ .Any({{DivP3}, {{VgprP3}, {VgprP0, Imm}}})
+ .Any({{DivP5, P0}, {{VgprP5}, {VgprP0, Imm}}})
+ .Any({{UniP6, P0}, {{SgprP6}, {SgprP0, Imm}}});
+
Predicate isSignedICmp([](const MachineInstr &MI) -> bool {
auto Pred =
static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
index eee4f6276b925..99f397b9bd9fd 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
@@ -44,18 +44,21 @@ enum UniformityLLTOpPredicateID {
S32,
S64,
S128,
+ S1024,
UniS1,
UniS16,
UniS32,
UniS64,
UniS128,
+ UniS1024,
DivS1,
DivS16,
DivS32,
DivS64,
DivS128,
+ DivS1024,
// pointers
P0,
@@ -64,6 +67,7 @@ enum UniformityLLTOpPredicateID {
P3,
P4,
P5,
+ P6,
P8,
Ptr32,
Ptr64,
@@ -75,6 +79,7 @@ enum UniformityLLTOpPredicateID {
UniP3,
UniP4,
UniP5,
+ UniP6,
UniP8,
UniPtr32,
UniPtr64,
@@ -149,12 +154,14 @@ enum RegBankLLTMappingApplyID {
Sgpr32,
Sgpr64,
Sgpr128,
+ Sgpr1024,
SgprP0,
SgprP1,
SgprP2,
SgprP3,
SgprP4,
SgprP5,
+ SgprP6,
SgprP8,
SgprPtr32,
SgprPtr64,
@@ -175,6 +182,7 @@ enum RegBankLLTMappingApplyID {
Vgpr32,
Vgpr64,
Vgpr128,
+ Vgpr1024,
VgprP0,
VgprP1,
VgprP2,
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract.mir
index 85cb851b6bc3d..9d98184f198cc 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract.mir
@@ -1,6 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s
---
name: extract_lo32_i64_s
@@ -76,10 +75,64 @@ body: |
; CHECK-LABEL: name: extract_lo32_i64_a
; CHECK: liveins: $agpr0_agpr1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:agpr(s64) = COPY $agpr0_agpr1
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:agpr(s32) = G_EXTRACT [[COPY]](s64), 0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $agpr0_agpr1
+ ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:vgpr(s32) = G_EXTRACT [[COPY]](s64), 0
; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](s32)
%0:_(s64) = COPY $agpr0_agpr1
%1:_(s32) = G_EXTRACT %0, 0
S_ENDPGM 0, implicit %1
...
+
+---
+name: extract_p3_from_p0_v
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+ ; CHECK-LABEL: name: extract_p3_from_p0_v
+ ; CHECK: liveins: $vgpr0_vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(p0) = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:vgpr(p3) = G_EXTRACT [[COPY]](p0), 0
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](p3)
+ %0:_(p0) = COPY $vgpr0_vgpr1
+ %1:_(p3) = G_EXTRACT %0, 0
+ S_ENDPGM 0, implicit %1
+...
+
+---
+name: extract_p5_from_p0_v
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+ ; CHECK-LABEL: name: extract_p5_from_p0_v
+ ; CHECK: liveins: $vgpr0_vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(p0) = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:vgpr(p5) = G_EXTRACT [[COPY]](p0), 0
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](p5)
+ %0:_(p0) = COPY $vgpr0_vgpr1
+ %1:_(p5) = G_EXTRACT %0, 0
+ S_ENDPGM 0, implicit %1
+...
+
+---
+name: extract_p6_from_p0_s
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1
+ ; CHECK-LABEL: name: extract_p6_from_p0_s
+ ; CHECK: liveins: $sgpr0_sgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(p0) = COPY $sgpr0_sgpr1
+ ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:sgpr(p6) = G_EXTRACT [[COPY]](p0), 0
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](p6)
+ %0:_(p0) = COPY $sgpr0_sgpr1
+ %1:_(p6) = G_EXTRACT %0, 0
+ S_ENDPGM 0, implicit %1
+...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-merge-values.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-merge-values.mir
index e22df46b505a5..a8bdccdb9031e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-merge-values.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-merge-values.mir
@@ -1,6 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s
---
name: merge_s64_s32_s32_ss
@@ -56,9 +55,9 @@ body: |
; CHECK-LABEL: name: merge_s64_s32_s32_aa
; CHECK: liveins: $agpr0, $agpr1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:agpr(s32) = COPY $agpr0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:agpr(s32) = COPY $agpr1
- ; CHECK-NEXT: [[MV:%[0-9]+]]:agpr(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $agpr0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $agpr1
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
; CHECK-NEXT: S_ENDPGM 0, implicit [[MV]](s64)
%0:_(s32) = COPY $agpr0
%1:_(s32) = COPY $agpr1
@@ -77,10 +76,9 @@ body: |
; CHECK: liveins: $sgpr0, $agpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:agpr(s32) = COPY $agpr0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $agpr0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY1]](s32)
; CHECK-NEXT: S_ENDPGM 0, implicit [[MV]](s64)
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $agpr0
@@ -98,11 +96,10 @@ body: |
; CHECK-LABEL: name: merge_s64_s32_s32_as
; CHECK: liveins: $sgpr0, $agpr0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:agpr(s32) = COPY $agpr0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $agpr0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY2]](s32)
; CHECK-NEXT: S_ENDPGM 0, implicit [[MV]](s64)
%0:_(s32) = COPY $agpr0
%1:_(s32) = COPY $sgpr0
diff --git a/llvm/test/CodeGen/AMDGPU/addrspacecast.gfx6.ll b/llvm/test/CodeGen/AMDGPU/addrspacecast.gfx6.ll
index 35d0214a6d48d..f7c51fbf47ba3 100644
--- a/llvm/test/CodeGen/AMDGPU/addrspacecast.gfx6.ll
+++ b/llvm/test/CodeGen/AMDGPU/addrspacecast.gfx6.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdpal -mcpu=tahiti < %s | FileCheck -check-prefixes=CHECK,SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdpal -mcpu=tahiti < %s | FileCheck -check-prefixes=CHECK,GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=tahiti < %s | FileCheck -check-prefixes=CHECK,GISEL %s
define ptr @global_to_flat_addrspacecast(ptr addrspace(1) %ptr) {
; CHECK-LABEL: global_to_flat_addrspacecast:
>From 4378ccdb7f01bf9ca5193f580ec886b360a7d3a9 Mon Sep 17 00:00:00 2001
From: Vang Thao <vang.thao at amd.com>
Date: Thu, 12 Feb 2026 11:49:47 -0800
Subject: [PATCH 2/6] Use BRC to cover all reg class sizes
---
.../AMDGPU/AMDGPURegBankLegalizeRules.cpp | 10 +-
.../GlobalISel/regbankselect-extract.mir | 513 +++++++++++++++++-
.../GlobalISel/regbankselect-merge-values.mir | 21 +-
3 files changed, 522 insertions(+), 22 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index 5f5c615752fa7..00aa878469577 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -655,13 +655,11 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
.Any({{DivBRC}, {{}, {}, ApplyAllVgpr}});
addRulesForGOpcs({G_EXTRACT})
- .Any({{UniS32, S64}, {{Sgpr32}, {Sgpr64}}})
- .Any({{DivS32, S64}, {{Vgpr32}, {Vgpr64}}})
- .Any({{UniS32, S1024}, {{Sgpr32}, {Sgpr1024}}})
- .Any({{DivS32, S1024}, {{Vgpr32}, {Vgpr1024}}})
+ .Any({{UniBRC}, {{SgprBRC}, {SgprBRC, Imm}}})
+ .Any({{DivBRC}, {{VgprBRC}, {VgprBRC, Imm}}})
.Any({{DivP3}, {{VgprP3}, {VgprP0, Imm}}})
- .Any({{DivP5, P0}, {{VgprP5}, {VgprP0, Imm}}})
- .Any({{UniP6, P0}, {{SgprP6}, {SgprP0, Imm}}});
+ .Any({{DivP5}, {{VgprP5}, {VgprP0, Imm}}})
+ .Any({{UniP6}, {{SgprP6}, {SgprP0, Imm}}});
Predicate isSignedICmp([](const MachineInstr &MI) -> bool {
auto Pred =
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract.mir
index 9d98184f198cc..2997172bb984a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract.mir
@@ -1,6 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# TODO: Re-enable extract_lo32_i64_a test after AGPR support.
+
---
name: extract_lo32_i64_s
legalized: true
@@ -65,24 +67,521 @@ body: |
%1:_(s32) = G_EXTRACT %0, 0
...
+# ---
+# name: extract_lo32_i64_a
+# legalized: true
+#
+# body: |
+# bb.0:
+# liveins: $agpr0_agpr1
+# %0:_(s64) = COPY $agpr0_agpr1
+# %1:_(s32) = G_EXTRACT %0, 0
+# S_ENDPGM 0, implicit %1
+# ...
+
---
-name: extract_lo32_i64_a
+name: extract_s32_from_s96_s
legalized: true
body: |
bb.0:
- liveins: $agpr0_agpr1
- ; CHECK-LABEL: name: extract_lo32_i64_a
- ; CHECK: liveins: $agpr0_agpr1
+ liveins: $sgpr0_sgpr1_sgpr2
+ ; CHECK-LABEL: name: extract_s32_from_s96_s
+ ; CHECK: liveins: $sgpr0_sgpr1_sgpr2
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $agpr0_agpr1
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:vgpr(s32) = G_EXTRACT [[COPY]](s64), 0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s96) = COPY $sgpr0_sgpr1_sgpr2
+ ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:sgpr(s32) = G_EXTRACT [[COPY]](s96), 0
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](s32)
+ %0:_(s96) = COPY $sgpr0_sgpr1_sgpr2
+ %1:_(s32) = G_EXTRACT %0, 0
+ S_ENDPGM 0, implicit %1
+...
+
+---
+name: extract_s32_from_s96_v
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1_vgpr2
+ ; CHECK-LABEL: name: extract_s32_from_s96_v
+ ; CHECK: liveins: $vgpr0_vgpr1_vgpr2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s96) = COPY $vgpr0_vgpr1_vgpr2
+ ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:vgpr(s32) = G_EXTRACT [[COPY]](s96), 0
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](s32)
+ %0:_(s96) = COPY $vgpr0_vgpr1_vgpr2
+ %1:_(s32) = G_EXTRACT %0, 0
+ S_ENDPGM 0, implicit %1
+...
+
+---
+name: extract_s32_from_s128_s
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1_sgpr2_sgpr3
+ ; CHECK-LABEL: name: extract_s32_from_s128_s
+ ; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
+ ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:sgpr(s32) = G_EXTRACT [[COPY]](s128), 0
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](s32)
+ %0:_(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
+ %1:_(s32) = G_EXTRACT %0, 0
+ S_ENDPGM 0, implicit %1
+...
+
+---
+name: extract_s32_from_s128_v
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1_vgpr2_vgpr3
+ ; CHECK-LABEL: name: extract_s32_from_s128_v
+ ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:vgpr(s32) = G_EXTRACT [[COPY]](s128), 0
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](s32)
+ %0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ %1:_(s32) = G_EXTRACT %0, 0
+ S_ENDPGM 0, implicit %1
+...
+
+---
+name: extract_s32_from_s256_s
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
+ ; CHECK-LABEL: name: extract_s32_from_s256_s
+ ; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s256) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
+ ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:sgpr(s32) = G_EXTRACT [[COPY]](s256), 0
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](s32)
+ %0:_(s256) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
+ %1:_(s32) = G_EXTRACT %0, 0
+ S_ENDPGM 0, implicit %1
+...
+
+---
+name: extract_s32_from_s256_v
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+ ; CHECK-LABEL: name: extract_s32_from_s256_v
+ ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+ ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:vgpr(s32) = G_EXTRACT [[COPY]](s256), 0
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](s32)
+ %0:_(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+ %1:_(s32) = G_EXTRACT %0, 0
+ S_ENDPGM 0, implicit %1
+...
+
+---
+name: extract_s32_from_s512_s
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
+ ; CHECK-LABEL: name: extract_s32_from_s512_s
+ ; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s512) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
+ ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:sgpr(s32) = G_EXTRACT [[COPY]](s512), 0
; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](s32)
- %0:_(s64) = COPY $agpr0_agpr1
+ %0:_(s512) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
%1:_(s32) = G_EXTRACT %0, 0
S_ENDPGM 0, implicit %1
...
+---
+name: extract_s32_from_s512_v
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+ ; CHECK-LABEL: name: extract_s32_from_s512_v
+ ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s512) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+ ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:vgpr(s32) = G_EXTRACT [[COPY]](s512), 0
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](s32)
+ %0:_(s512) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+ %1:_(s32) = G_EXTRACT %0, 0
+ S_ENDPGM 0, implicit %1
+...
+
+---
+name: extract_s64_from_s96_s
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1_sgpr2
+ ; CHECK-LABEL: name: extract_s64_from_s96_s
+ ; CHECK: liveins: $sgpr0_sgpr1_sgpr2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s96) = COPY $sgpr0_sgpr1_sgpr2
+ ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:sgpr(s64) = G_EXTRACT [[COPY]](s96), 0
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](s64)
+ %0:_(s96) = COPY $sgpr0_sgpr1_sgpr2
+ %1:_(s64) = G_EXTRACT %0, 0
+ S_ENDPGM 0, implicit %1
+...
+
+---
+name: extract_s64_from_s96_v
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1_vgpr2
+ ; CHECK-LABEL: name: extract_s64_from_s96_v
+ ; CHECK: liveins: $vgpr0_vgpr1_vgpr2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s96) = COPY $vgpr0_vgpr1_vgpr2
+ ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:vgpr(s64) = G_EXTRACT [[COPY]](s96), 0
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](s64)
+ %0:_(s96) = COPY $vgpr0_vgpr1_vgpr2
+ %1:_(s64) = G_EXTRACT %0, 0
+ S_ENDPGM 0, implicit %1
+...
+
+---
+name: extract_s64_from_s128_s
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1_sgpr2_sgpr3
+ ; CHECK-LABEL: name: extract_s64_from_s128_s
+ ; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
+ ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:sgpr(s64) = G_EXTRACT [[COPY]](s128), 0
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](s64)
+ %0:_(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
+ %1:_(s64) = G_EXTRACT %0, 0
+ S_ENDPGM 0, implicit %1
+...
+
+---
+name: extract_s64_from_s128_v
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1_vgpr2_vgpr3
+ ; CHECK-LABEL: name: extract_s64_from_s128_v
+ ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:vgpr(s64) = G_EXTRACT [[COPY]](s128), 0
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](s64)
+ %0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ %1:_(s64) = G_EXTRACT %0, 0
+ S_ENDPGM 0, implicit %1
+...
+
+---
+name: extract_s64_from_s256_s
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
+ ; CHECK-LABEL: name: extract_s64_from_s256_s
+ ; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s256) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
+ ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:sgpr(s64) = G_EXTRACT [[COPY]](s256), 0
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](s64)
+ %0:_(s256) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
+ %1:_(s64) = G_EXTRACT %0, 0
+ S_ENDPGM 0, implicit %1
+...
+
+---
+name: extract_s64_from_s256_v
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+ ; CHECK-LABEL: name: extract_s64_from_s256_v
+ ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+ ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:vgpr(s64) = G_EXTRACT [[COPY]](s256), 0
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](s64)
+ %0:_(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+ %1:_(s64) = G_EXTRACT %0, 0
+ S_ENDPGM 0, implicit %1
+...
+
+---
+name: extract_s64_from_s512_s
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
+ ; CHECK-LABEL: name: extract_s64_from_s512_s
+ ; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s512) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
+ ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:sgpr(s64) = G_EXTRACT [[COPY]](s512), 0
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](s64)
+ %0:_(s512) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
+ %1:_(s64) = G_EXTRACT %0, 0
+ S_ENDPGM 0, implicit %1
+...
+
+---
+name: extract_s64_from_s512_v
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+ ; CHECK-LABEL: name: extract_s64_from_s512_v
+ ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s512) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+ ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:vgpr(s64) = G_EXTRACT [[COPY]](s512), 0
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](s64)
+ %0:_(s512) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+ %1:_(s64) = G_EXTRACT %0, 0
+ S_ENDPGM 0, implicit %1
+...
+
+---
+name: extract_s96_from_s128_s
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1_sgpr2_sgpr3
+ ; CHECK-LABEL: name: extract_s96_from_s128_s
+ ; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
+ ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:sgpr(s96) = G_EXTRACT [[COPY]](s128), 0
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](s96)
+ %0:_(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
+ %1:_(s96) = G_EXTRACT %0, 0
+ S_ENDPGM 0, implicit %1
+...
+
+---
+name: extract_s96_from_s128_v
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1_vgpr2_vgpr3
+ ; CHECK-LABEL: name: extract_s96_from_s128_v
+ ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:vgpr(s96) = G_EXTRACT [[COPY]](s128), 0
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](s96)
+ %0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ %1:_(s96) = G_EXTRACT %0, 0
+ S_ENDPGM 0, implicit %1
+...
+
+---
+name: extract_s96_from_s256_s
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
+ ; CHECK-LABEL: name: extract_s96_from_s256_s
+ ; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s256) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
+ ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:sgpr(s96) = G_EXTRACT [[COPY]](s256), 0
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](s96)
+ %0:_(s256) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
+ %1:_(s96) = G_EXTRACT %0, 0
+ S_ENDPGM 0, implicit %1
+...
+
+---
+name: extract_s96_from_s256_v
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+ ; CHECK-LABEL: name: extract_s96_from_s256_v
+ ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+ ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:vgpr(s96) = G_EXTRACT [[COPY]](s256), 0
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](s96)
+ %0:_(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+ %1:_(s96) = G_EXTRACT %0, 0
+ S_ENDPGM 0, implicit %1
+...
+
+---
+name: extract_s96_from_s512_s
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
+ ; CHECK-LABEL: name: extract_s96_from_s512_s
+ ; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s512) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
+ ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:sgpr(s96) = G_EXTRACT [[COPY]](s512), 0
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](s96)
+ %0:_(s512) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
+ %1:_(s96) = G_EXTRACT %0, 0
+ S_ENDPGM 0, implicit %1
+...
+
+---
+name: extract_s96_from_s512_v
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+ ; CHECK-LABEL: name: extract_s96_from_s512_v
+ ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s512) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+ ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:vgpr(s96) = G_EXTRACT [[COPY]](s512), 0
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](s96)
+ %0:_(s512) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+ %1:_(s96) = G_EXTRACT %0, 0
+ S_ENDPGM 0, implicit %1
+...
+
+---
+name: extract_s128_from_s256_s
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
+ ; CHECK-LABEL: name: extract_s128_from_s256_s
+ ; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s256) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
+ ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:sgpr(s128) = G_EXTRACT [[COPY]](s256), 0
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](s128)
+ %0:_(s256) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
+ %1:_(s128) = G_EXTRACT %0, 0
+ S_ENDPGM 0, implicit %1
+...
+
+---
+name: extract_s128_from_s256_v
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+ ; CHECK-LABEL: name: extract_s128_from_s256_v
+ ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+ ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:vgpr(s128) = G_EXTRACT [[COPY]](s256), 0
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](s128)
+ %0:_(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+ %1:_(s128) = G_EXTRACT %0, 0
+ S_ENDPGM 0, implicit %1
+...
+
+---
+name: extract_s128_from_s512_s
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
+ ; CHECK-LABEL: name: extract_s128_from_s512_s
+ ; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s512) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
+ ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:sgpr(s128) = G_EXTRACT [[COPY]](s512), 0
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](s128)
+ %0:_(s512) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
+ %1:_(s128) = G_EXTRACT %0, 0
+ S_ENDPGM 0, implicit %1
+...
+
+---
+name: extract_s128_from_s512_v
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+ ; CHECK-LABEL: name: extract_s128_from_s512_v
+ ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s512) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+ ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:vgpr(s128) = G_EXTRACT [[COPY]](s512), 0
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](s128)
+ %0:_(s512) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+ %1:_(s128) = G_EXTRACT %0, 0
+ S_ENDPGM 0, implicit %1
+...
+
+---
+name: extract_s256_from_s512_s
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
+ ; CHECK-LABEL: name: extract_s256_from_s512_s
+ ; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s512) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
+ ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:sgpr(s256) = G_EXTRACT [[COPY]](s512), 0
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](s256)
+ %0:_(s512) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
+ %1:_(s256) = G_EXTRACT %0, 0
+ S_ENDPGM 0, implicit %1
+...
+
+---
+name: extract_s256_from_s512_v
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+ ; CHECK-LABEL: name: extract_s256_from_s512_v
+ ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s512) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+ ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:vgpr(s256) = G_EXTRACT [[COPY]](s512), 0
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](s256)
+ %0:_(s512) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+ %1:_(s256) = G_EXTRACT %0, 0
+ S_ENDPGM 0, implicit %1
+...
---
name: extract_p3_from_p0_v
legalized: true
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-merge-values.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-merge-values.mir
index a8bdccdb9031e..e22df46b505a5 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-merge-values.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-merge-values.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
---
name: merge_s64_s32_s32_ss
@@ -55,9 +56,9 @@ body: |
; CHECK-LABEL: name: merge_s64_s32_s32_aa
; CHECK: liveins: $agpr0, $agpr1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $agpr0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $agpr1
- ; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:agpr(s32) = COPY $agpr0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:agpr(s32) = COPY $agpr1
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:agpr(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
; CHECK-NEXT: S_ENDPGM 0, implicit [[MV]](s64)
%0:_(s32) = COPY $agpr0
%1:_(s32) = COPY $agpr1
@@ -76,9 +77,10 @@ body: |
; CHECK: liveins: $sgpr0, $agpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $agpr0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:agpr(s32) = COPY $agpr0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY1]](s32)
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
; CHECK-NEXT: S_ENDPGM 0, implicit [[MV]](s64)
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $agpr0
@@ -96,10 +98,11 @@ body: |
; CHECK-LABEL: name: merge_s64_s32_s32_as
; CHECK: liveins: $sgpr0, $agpr0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $agpr0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:agpr(s32) = COPY $agpr0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
; CHECK-NEXT: S_ENDPGM 0, implicit [[MV]](s64)
%0:_(s32) = COPY $agpr0
%1:_(s32) = COPY $sgpr0
>From eb1f3155e6bbc8a502d7a59bdc320c511bdaad52 Mon Sep 17 00:00:00 2001
From: Vang Thao <vang.thao at amd.com>
Date: Fri, 27 Feb 2026 00:38:54 -0800
Subject: [PATCH 3/6] Lower G_EXTRACT in legalizer
---
.../lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 132 +++-
llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h | 2 +
.../AMDGPU/AMDGPURegBankLegalizeHelper.cpp | 14 -
.../AMDGPU/AMDGPURegBankLegalizeRules.cpp | 17 -
.../AMDGPU/AMDGPURegBankLegalizeRules.h | 8 -
.../GlobalISel/artifact-combiner-extract.mir | 62 +-
.../CodeGen/AMDGPU/GlobalISel/global-value.ll | 14 +-
.../GlobalISel/legalize-addrspacecast.mir | 42 +-
.../AMDGPU/GlobalISel/legalize-and.mir | 22 +-
.../AMDGPU/GlobalISel/legalize-extract.mir | 356 +++++++++--
.../GlobalISel/legalize-implicit-def.mir | 7 +-
.../CodeGen/AMDGPU/GlobalISel/legalize-or.mir | 22 +-
.../AMDGPU/GlobalISel/legalize-select.mir | 22 +-
.../AMDGPU/GlobalISel/legalize-xor.mir | 22 +-
.../AMDGPU/GlobalISel/legalize-zext.mir | 7 +-
.../GlobalISel/regbankselect-extract.mir | 570 +-----------------
16 files changed, 560 insertions(+), 759 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index 5a993a456439e..c1b9b0c780c7c 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -1938,42 +1938,71 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
return Query.Types[0] != EltTy;
});
- for (unsigned Op : {G_EXTRACT, G_INSERT}) {
- unsigned BigTyIdx = Op == G_EXTRACT ? 1 : 0;
- unsigned LitTyIdx = Op == G_EXTRACT ? 0 : 1;
-
- // FIXME: Doesn't handle extract of illegal sizes.
- getActionDefinitionsBuilder(Op)
- .lowerIf(all(typeIs(LitTyIdx, S16), sizeIs(BigTyIdx, 32)))
- .lowerIf([=](const LegalityQuery &Query) {
- // Sub-vector(or single element) insert and extract.
+ {
+ const unsigned BigTyIdx = 0; // destination / result
+ const unsigned LitTyIdx = 1; // inserted value
+ getActionDefinitionsBuilder(G_INSERT)
+ .lowerIf(all(typeIs(LitTyIdx, S16), sizeIs(BigTyIdx, 32)))
+ .lowerIf([=](const LegalityQuery &Query) {
+ // Sub-vector(or single element) insert.
// TODO: verify immediate offset here since lower only works with
// whole elements.
const LLT BigTy = Query.Types[BigTyIdx];
return BigTy.isVector();
})
- // FIXME: Multiples of 16 should not be legal.
- .legalIf([=](const LegalityQuery &Query) {
+ // FIXME: Multiples of 16 should not be legal.
+ .legalIf([=](const LegalityQuery &Query) {
const LLT BigTy = Query.Types[BigTyIdx];
const LLT LitTy = Query.Types[LitTyIdx];
return (BigTy.getSizeInBits() % 32 == 0) &&
(LitTy.getSizeInBits() % 16 == 0);
})
- .widenScalarIf(
- [=](const LegalityQuery &Query) {
+ .widenScalarIf(
+ [=](const LegalityQuery &Query) {
+ const LLT BigTy = Query.Types[BigTyIdx];
+ return (BigTy.getScalarSizeInBits() < 16);
+ },
+ LegalizeMutations::widenScalarOrEltToNextPow2(BigTyIdx, 16))
+ .widenScalarIf(
+ [=](const LegalityQuery &Query) {
+ const LLT LitTy = Query.Types[LitTyIdx];
+ return (LitTy.getScalarSizeInBits() < 16);
+ },
+ LegalizeMutations::widenScalarOrEltToNextPow2(LitTyIdx, 16))
+ .moreElementsIf(isSmallOddVector(BigTyIdx), oneMoreElement(BigTyIdx))
+ .widenScalarToNextPow2(BigTyIdx, 32);
+ }
+
+ {
+ const unsigned BigTyIdx = 1; // source
+ const unsigned LitTyIdx = 0; // destination
+ getActionDefinitionsBuilder(G_EXTRACT)
+ .lowerIf([=](const LegalityQuery &Query) {
+ // Sub-vector(or single element) extract.
+ // TODO: verify immediate offset here since lower only works with
+ // whole elements.
+ const LLT BigTy = Query.Types[BigTyIdx];
+ return BigTy.isVector();
+ })
+ .customIf([=](const LegalityQuery &Query) {
const LLT BigTy = Query.Types[BigTyIdx];
- return (BigTy.getScalarSizeInBits() < 16);
- },
- LegalizeMutations::widenScalarOrEltToNextPow2(BigTyIdx, 16))
- .widenScalarIf(
- [=](const LegalityQuery &Query) {
const LLT LitTy = Query.Types[LitTyIdx];
- return (LitTy.getScalarSizeInBits() < 16);
- },
- LegalizeMutations::widenScalarOrEltToNextPow2(LitTyIdx, 16))
- .moreElementsIf(isSmallOddVector(BigTyIdx), oneMoreElement(BigTyIdx))
- .widenScalarToNextPow2(BigTyIdx, 32);
-
+ return !LitTy.isVector() && BigTy.getSizeInBits() % 32 == 0;
+ })
+ .widenScalarIf(
+ [=](const LegalityQuery &Query) {
+ const LLT BigTy = Query.Types[BigTyIdx];
+ return (BigTy.getScalarSizeInBits() < 16);
+ },
+ LegalizeMutations::widenScalarOrEltToNextPow2(BigTyIdx, 16))
+ .widenScalarIf(
+ [=](const LegalityQuery &Query) {
+ const LLT LitTy = Query.Types[LitTyIdx];
+ return (LitTy.getScalarSizeInBits() < 16);
+ },
+ LegalizeMutations::widenScalarOrEltToNextPow2(LitTyIdx, 16))
+ .moreElementsIf(isSmallOddVector(BigTyIdx), oneMoreElement(BigTyIdx))
+ .widenScalarToNextPow2(BigTyIdx, 32);
}
auto &BuildVector =
@@ -2250,6 +2279,8 @@ bool AMDGPULegalizerInfo::legalizeCustom(
case TargetOpcode::G_FMINIMUMNUM:
case TargetOpcode::G_FMAXIMUMNUM:
return legalizeMinNumMaxNum(Helper, MI);
+ case TargetOpcode::G_EXTRACT:
+ return legalizeExtract(MI, MRI, B);
case TargetOpcode::G_EXTRACT_VECTOR_ELT:
return legalizeExtractVectorElt(MI, MRI, B);
case TargetOpcode::G_INSERT_VECTOR_ELT:
@@ -2885,6 +2916,59 @@ bool AMDGPULegalizerInfo::legalizeMinNumMaxNum(LegalizerHelper &Helper,
return Helper.lowerFMinNumMaxNum(MI) == LegalizerHelper::Legalized;
}
+bool AMDGPULegalizerInfo::legalizeExtract(MachineInstr &MI,
+ MachineRegisterInfo &MRI,
+ MachineIRBuilder &B) const {
+ auto [DstReg, DstTy, SrcReg, SrcTy] = MI.getFirst2RegLLTs();
+
+ assert(!SrcTy.isVector() && !DstTy.isVector());
+ assert(SrcTy.getSizeInBits() % 32 == 0);
+
+ unsigned Offset = MI.getOperand(2).getImm();
+ unsigned DstSize = DstTy.getSizeInBits();
+ const LLT S32 = LLT::scalar(32);
+
+ // For pointer types, work on the integer representation.
+ LLT ScalarSrcTy = LLT::scalar(SrcTy.getSizeInBits());
+ Register ScalarSrc = SrcReg;
+ if (SrcTy.isPointer())
+ ScalarSrc = B.buildPtrToInt(ScalarSrcTy, SrcReg).getReg(0);
+
+ Register ScalarDst = DstReg;
+ if (DstTy.isPointer())
+ ScalarDst = MRI.createGenericVirtualRegister(LLT::scalar(DstSize));
+
+ // Simple case where Dst and Offset are multiples of 32-bit, we can unmerge
+ // and get the subreg(s).
+ if (DstSize % 32 == 0 && Offset % 32 == 0) {
+ unsigned StartIdx = Offset / 32;
+ unsigned DstCount = DstSize / 32;
+ auto Unmerge = B.buildUnmerge(S32, ScalarSrc);
+ if (DstCount == 1) {
+ B.buildCopy(ScalarDst, Unmerge.getReg(StartIdx));
+ } else {
+ SmallVector<Register, 4> Pieces;
+ for (unsigned I = 0; I < DstCount; ++I)
+ Pieces.push_back(Unmerge.getReg(StartIdx + I));
+ B.buildMergeLikeInstr(ScalarDst, Pieces);
+ }
+ } else {
+ // Let Trunc handle non-trivial cases.
+ Register ShiftedSrc = ScalarSrc;
+ if (Offset != 0) {
+ auto ShiftAmt = B.buildConstant(S32, Offset);
+ ShiftedSrc = B.buildLShr(ScalarSrcTy, ScalarSrc, ShiftAmt).getReg(0);
+ }
+ B.buildTrunc(ScalarDst, ShiftedSrc);
+ }
+
+ if (DstTy.isPointer())
+ B.buildIntToPtr(DstReg, ScalarDst);
+
+ MI.eraseFromParent();
+ return true;
+}
+
bool AMDGPULegalizerInfo::legalizeExtractVectorElt(
MachineInstr &MI, MachineRegisterInfo &MRI,
MachineIRBuilder &B) const {
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
index 1224ee7ac60be..fa45c518a5052 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
@@ -56,6 +56,8 @@ class AMDGPULegalizerInfo final : public LegalizerInfo {
bool legalizeFPTOI(MachineInstr &MI, MachineRegisterInfo &MRI,
MachineIRBuilder &B, bool Signed) const;
bool legalizeMinNumMaxNum(LegalizerHelper &Helper, MachineInstr &MI) const;
+ bool legalizeExtract(MachineInstr &MI, MachineRegisterInfo &MRI,
+ MachineIRBuilder &B) const;
bool legalizeExtractVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
MachineIRBuilder &B) const;
bool legalizeInsertVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
index 8528acc76e703..d262f074679a8 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
@@ -1095,9 +1095,6 @@ LLT RegBankLegalizeHelper::getTyFromID(RegBankLLTMappingApplyID ID) {
case Sgpr128:
case Vgpr128:
return LLT::scalar(128);
- case Sgpr1024:
- case Vgpr1024:
- return LLT::scalar(1024);
case SgprP0:
case VgprP0:
return LLT::pointer(0, 64);
@@ -1116,8 +1113,6 @@ LLT RegBankLegalizeHelper::getTyFromID(RegBankLLTMappingApplyID ID) {
case SgprP5:
case VgprP5:
return LLT::pointer(5, 32);
- case SgprP6:
- return LLT::pointer(6, 32);
case SgprP8:
return LLT::pointer(8, 128);
case SgprV2S16:
@@ -1232,14 +1227,12 @@ RegBankLegalizeHelper::getRegBankFromID(RegBankLLTMappingApplyID ID) {
case Sgpr32_WF:
case Sgpr64:
case Sgpr128:
- case Sgpr1024:
case SgprP0:
case SgprP1:
case SgprP2:
case SgprP3:
case SgprP4:
case SgprP5:
- case SgprP6:
case SgprP8:
case SgprPtr32:
case SgprPtr64:
@@ -1280,7 +1273,6 @@ RegBankLegalizeHelper::getRegBankFromID(RegBankLLTMappingApplyID ID) {
case Vgpr32:
case Vgpr64:
case Vgpr128:
- case Vgpr1024:
case VgprP0:
case VgprP1:
case VgprP2:
@@ -1331,13 +1323,11 @@ bool RegBankLegalizeHelper::applyMappingDst(
case Sgpr32:
case Sgpr64:
case Sgpr128:
- case Sgpr1024:
case SgprP0:
case SgprP1:
case SgprP3:
case SgprP4:
case SgprP5:
- case SgprP6:
case SgprP8:
case SgprV2S16:
case SgprV2S32:
@@ -1346,7 +1336,6 @@ bool RegBankLegalizeHelper::applyMappingDst(
case Vgpr32:
case Vgpr64:
case Vgpr128:
- case Vgpr1024:
case VgprP0:
case VgprP1:
case VgprP2:
@@ -1497,13 +1486,11 @@ bool RegBankLegalizeHelper::applyMappingSrc(
case Sgpr32:
case Sgpr64:
case Sgpr128:
- case Sgpr1024:
case SgprP0:
case SgprP1:
case SgprP3:
case SgprP4:
case SgprP5:
- case SgprP6:
case SgprP8:
case SgprV2S16:
case SgprV2S32:
@@ -1532,7 +1519,6 @@ bool RegBankLegalizeHelper::applyMappingSrc(
case Vgpr32:
case Vgpr64:
case Vgpr128:
- case Vgpr1024:
case VgprP0:
case VgprP1:
case VgprP2:
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index 00aa878469577..a0be07d7eae05 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -56,8 +56,6 @@ bool matchUniformityAndLLT(Register Reg, UniformityLLTOpPredicateID UniID,
return MRI.getType(Reg) == LLT::scalar(64);
case S128:
return MRI.getType(Reg) == LLT::scalar(128);
- case S1024:
- return MRI.getType(Reg) == LLT::scalar(1024);
case P0:
return MRI.getType(Reg) == LLT::pointer(0, 64);
case P1:
@@ -70,8 +68,6 @@ bool matchUniformityAndLLT(Register Reg, UniformityLLTOpPredicateID UniID,
return MRI.getType(Reg) == LLT::pointer(4, 64);
case P5:
return MRI.getType(Reg) == LLT::pointer(5, 32);
- case P6:
- return MRI.getType(Reg) == LLT::pointer(6, 32);
case P8:
return MRI.getType(Reg) == LLT::pointer(8, 128);
case Ptr32:
@@ -112,8 +108,6 @@ bool matchUniformityAndLLT(Register Reg, UniformityLLTOpPredicateID UniID,
return MRI.getType(Reg) == LLT::scalar(64) && MUI.isUniform(Reg);
case UniS128:
return MRI.getType(Reg) == LLT::scalar(128) && MUI.isUniform(Reg);
- case UniS1024:
- return MRI.getType(Reg) == LLT::scalar(1024) && MUI.isUniform(Reg);
case UniP0:
return MRI.getType(Reg) == LLT::pointer(0, 64) && MUI.isUniform(Reg);
case UniP1:
@@ -126,8 +120,6 @@ bool matchUniformityAndLLT(Register Reg, UniformityLLTOpPredicateID UniID,
return MRI.getType(Reg) == LLT::pointer(4, 64) && MUI.isUniform(Reg);
case UniP5:
return MRI.getType(Reg) == LLT::pointer(5, 32) && MUI.isUniform(Reg);
- case UniP6:
- return MRI.getType(Reg) == LLT::pointer(6, 32) && MUI.isUniform(Reg);
case UniP8:
return MRI.getType(Reg) == LLT::pointer(8, 128) && MUI.isUniform(Reg);
case UniPtr32:
@@ -175,8 +167,6 @@ bool matchUniformityAndLLT(Register Reg, UniformityLLTOpPredicateID UniID,
return MRI.getType(Reg) == LLT::scalar(64) && MUI.isDivergent(Reg);
case DivS128:
return MRI.getType(Reg) == LLT::scalar(128) && MUI.isDivergent(Reg);
- case DivS1024:
- return MRI.getType(Reg) == LLT::scalar(1024) && MUI.isDivergent(Reg);
case DivP0:
return MRI.getType(Reg) == LLT::pointer(0, 64) && MUI.isDivergent(Reg);
case DivP1:
@@ -654,13 +644,6 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
.Any({{UniBRC}, {{}, {}, VerifyAllSgpr}})
.Any({{DivBRC}, {{}, {}, ApplyAllVgpr}});
- addRulesForGOpcs({G_EXTRACT})
- .Any({{UniBRC}, {{SgprBRC}, {SgprBRC, Imm}}})
- .Any({{DivBRC}, {{VgprBRC}, {VgprBRC, Imm}}})
- .Any({{DivP3}, {{VgprP3}, {VgprP0, Imm}}})
- .Any({{DivP5}, {{VgprP5}, {VgprP0, Imm}}})
- .Any({{UniP6}, {{SgprP6}, {SgprP0, Imm}}});
-
Predicate isSignedICmp([](const MachineInstr &MI) -> bool {
auto Pred =
static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
index 99f397b9bd9fd..eee4f6276b925 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
@@ -44,21 +44,18 @@ enum UniformityLLTOpPredicateID {
S32,
S64,
S128,
- S1024,
UniS1,
UniS16,
UniS32,
UniS64,
UniS128,
- UniS1024,
DivS1,
DivS16,
DivS32,
DivS64,
DivS128,
- DivS1024,
// pointers
P0,
@@ -67,7 +64,6 @@ enum UniformityLLTOpPredicateID {
P3,
P4,
P5,
- P6,
P8,
Ptr32,
Ptr64,
@@ -79,7 +75,6 @@ enum UniformityLLTOpPredicateID {
UniP3,
UniP4,
UniP5,
- UniP6,
UniP8,
UniPtr32,
UniPtr64,
@@ -154,14 +149,12 @@ enum RegBankLLTMappingApplyID {
Sgpr32,
Sgpr64,
Sgpr128,
- Sgpr1024,
SgprP0,
SgprP1,
SgprP2,
SgprP3,
SgprP4,
SgprP5,
- SgprP6,
SgprP8,
SgprPtr32,
SgprPtr64,
@@ -182,7 +175,6 @@ enum RegBankLLTMappingApplyID {
Vgpr32,
Vgpr64,
Vgpr128,
- Vgpr1024,
VgprP0,
VgprP1,
VgprP2,
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-extract.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-extract.mir
index b72abbf557b36..623536e5ef8ce 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-extract.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-extract.mir
@@ -72,8 +72,9 @@ body: |
bb.0:
; CHECK-LABEL: name: extract_s32_merge_s128_s64_s64_offset0
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[C]](s64), 0
- ; CHECK-NEXT: $vgpr0 = COPY [[EXTRACT]](s32)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
+ ; CHECK-NEXT: $vgpr0 = COPY [[COPY]](s32)
%0:_(s64) = G_CONSTANT i64 0
%1:_(s64) = G_CONSTANT i64 1
%2:_(s128) = G_MERGE_VALUES %0, %1
@@ -88,8 +89,9 @@ body: |
bb.0:
; CHECK-LABEL: name: extract_s32_merge_s128_s64_s64_offset32
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[C]](s64), 32
- ; CHECK-NEXT: $vgpr0 = COPY [[EXTRACT]](s32)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
+ ; CHECK-NEXT: $vgpr0 = COPY [[COPY]](s32)
%0:_(s64) = G_CONSTANT i64 0
%1:_(s64) = G_CONSTANT i64 1
%2:_(s128) = G_MERGE_VALUES %0, %1
@@ -104,8 +106,9 @@ body: |
bb.0:
; CHECK-LABEL: name: extract_s32_merge_s128_s64_s64_offset64
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[C]](s64), 0
- ; CHECK-NEXT: $vgpr0 = COPY [[EXTRACT]](s32)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
+ ; CHECK-NEXT: $vgpr0 = COPY [[COPY]](s32)
%0:_(s64) = G_CONSTANT i64 0
%1:_(s64) = G_CONSTANT i64 1
%2:_(s128) = G_MERGE_VALUES %0, %1
@@ -120,8 +123,9 @@ body: |
bb.0:
; CHECK-LABEL: name: extract_s32_merge_s128_s64_s64_offset96
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[C]](s64), 32
- ; CHECK-NEXT: $vgpr0 = COPY [[EXTRACT]](s32)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
+ ; CHECK-NEXT: $vgpr0 = COPY [[COPY]](s32)
%0:_(s64) = G_CONSTANT i64 0
%1:_(s64) = G_CONSTANT i64 1
%2:_(s128) = G_MERGE_VALUES %0, %1
@@ -136,10 +140,8 @@ name: extract_s16_merge_s128_s64_s64_offset18
body: |
bb.0:
; CHECK-LABEL: name: extract_s16_merge_s128_s64_s64_offset18
- ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:_(s16) = G_EXTRACT [[C]](s64), 18
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EXTRACT]](s16)
- ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: $vgpr0 = COPY [[C]](s32)
%0:_(s64) = G_CONSTANT i64 0
%1:_(s64) = G_CONSTANT i64 1
%2:_(s128) = G_MERGE_VALUES %0, %1
@@ -156,9 +158,8 @@ body: |
bb.0:
; CHECK-LABEL: name: extract_s16_merge_s128_s64_s64_offset82
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:_(s16) = G_EXTRACT [[C]](s64), 18
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EXTRACT]](s16)
- ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: $vgpr0 = COPY [[C1]](s32)
%0:_(s64) = G_CONSTANT i64 0
%1:_(s64) = G_CONSTANT i64 1
%2:_(s128) = G_MERGE_VALUES %0, %1
@@ -177,9 +178,10 @@ body: |
; CHECK-LABEL: name: extract_s64_merge_s128_s64_s64_offset32
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[C]](s64), [[C1]](s64)
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:_(s64) = G_EXTRACT [[MV]](s128), 32
- ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[EXTRACT]](s64)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64)
+ ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C1]](s64)
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV1]](s32), [[UV2]](s32)
+ ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
%0:_(s64) = G_CONSTANT i64 0
%1:_(s64) = G_CONSTANT i64 1
%2:_(s128) = G_MERGE_VALUES %0, %1
@@ -198,8 +200,9 @@ body: |
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C]](s32), [[C1]](s32)
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[MV]](s64), 1
- ; CHECK-NEXT: $vgpr0 = COPY [[EXTRACT]](s32)
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[MV]], [[C1]](s32)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)
+ ; CHECK-NEXT: $vgpr0 = COPY [[TRUNC]](s32)
%0:_(s32) = G_CONSTANT i32 0
%1:_(s32) = G_CONSTANT i32 1
%2:_(s64) = G_MERGE_VALUES %0, %1
@@ -252,10 +255,8 @@ body: |
; CHECK-LABEL: name: extract_s64_merge_s96_s32_s32_s32_offset0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[C]](s32), [[C1]](s32), [[C2]](s32)
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:_(s64) = G_EXTRACT [[MV]](s96), 0
- ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[EXTRACT]](s64)
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C]](s32), [[C1]](s32)
+ ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
%0:_(s32) = G_CONSTANT i32 0
%1:_(s32) = G_CONSTANT i32 1
%2:_(s32) = G_CONSTANT i32 1
@@ -270,12 +271,10 @@ name: extract_s64_merge_s96_s32_s32_s32_offset32
body: |
bb.0:
; CHECK-LABEL: name: extract_s64_merge_s96_s32_s32_s32_offset32
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[C]](s32), [[C1]](s32), [[C2]](s32)
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:_(s64) = G_EXTRACT [[MV]](s96), 32
- ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[EXTRACT]](s64)
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C]](s32), [[C1]](s32)
+ ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
%0:_(s32) = G_CONSTANT i32 0
%1:_(s32) = G_CONSTANT i32 1
%2:_(s32) = G_CONSTANT i32 1
@@ -348,8 +347,9 @@ body: |
bb.0:
; CHECK-LABEL: name: extract_s32_build_vector_v2s64_s64_s64_offset64
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[C]](s64), 0
- ; CHECK-NEXT: $vgpr0 = COPY [[EXTRACT]](s32)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
+ ; CHECK-NEXT: $vgpr0 = COPY [[COPY]](s32)
%0:_(s64) = G_CONSTANT i64 0
%1:_(s64) = G_CONSTANT i64 1
%2:_(<2 x s64>) = G_BUILD_VECTOR %0, %1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/global-value.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/global-value.ll
index da17977602cb1..f99c5f0c8fd55 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/global-value.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/global-value.ll
@@ -142,8 +142,11 @@ define ptr addrspace(6) @external_constant32_got() {
; GCN: bb.1 (%ir-block.0):
; GCN-NEXT: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p4) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @external_constant32, target-flags(amdgpu-gotprel32-hi) @external_constant32, implicit-def $scc
; GCN-NEXT: [[LOAD:%[0-9]+]]:_(p4) = G_LOAD [[SI_PC_ADD_REL_OFFSET]](p4) :: (dereferenceable invariant load (p4) from got, addrspace 4)
- ; GCN-NEXT: [[EXTRACT:%[0-9]+]]:_(p6) = G_EXTRACT [[LOAD]](p4), 0
- ; GCN-NEXT: $vgpr0 = COPY [[EXTRACT]](p6)
+ ; GCN-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[LOAD]](p4)
+ ; GCN-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[PTRTOINT]](s64)
+ ; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
+ ; GCN-NEXT: [[INTTOPTR:%[0-9]+]]:_(p6) = G_INTTOPTR [[COPY]](s32)
+ ; GCN-NEXT: $vgpr0 = COPY [[INTTOPTR]](p6)
; GCN-NEXT: SI_RETURN implicit $vgpr0
;
; GCN-PAL-LABEL: name: external_constant32_got
@@ -159,8 +162,11 @@ define ptr addrspace(6) @internal_constant32_pcrel() {
; GCN-LABEL: name: internal_constant32_pcrel
; GCN: bb.1 (%ir-block.0):
; GCN-NEXT: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p4) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @internal_constant32, target-flags(amdgpu-rel32-hi) @internal_constant32, implicit-def $scc
- ; GCN-NEXT: [[EXTRACT:%[0-9]+]]:_(p6) = G_EXTRACT [[SI_PC_ADD_REL_OFFSET]](p4), 0
- ; GCN-NEXT: $vgpr0 = COPY [[EXTRACT]](p6)
+ ; GCN-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[SI_PC_ADD_REL_OFFSET]](p4)
+ ; GCN-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[PTRTOINT]](s64)
+ ; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
+ ; GCN-NEXT: [[INTTOPTR:%[0-9]+]]:_(p6) = G_INTTOPTR [[COPY]](s32)
+ ; GCN-NEXT: $vgpr0 = COPY [[INTTOPTR]](p6)
; GCN-NEXT: SI_RETURN implicit $vgpr0
;
; GCN-PAL-LABEL: name: internal_constant32_pcrel
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir
index e83b4eabd5dc8..15fee3d567f44 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir
@@ -186,9 +186,12 @@ body: |
; GCN-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; GCN-NEXT: [[C:%[0-9]+]]:_(p5) = G_CONSTANT i32 -1
; GCN-NEXT: [[C1:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
- ; GCN-NEXT: [[EXTRACT:%[0-9]+]]:_(p5) = G_EXTRACT [[COPY]](p0), 0
+ ; GCN-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY]](p0)
+ ; GCN-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[PTRTOINT]](s64)
+ ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
+ ; GCN-NEXT: [[INTTOPTR:%[0-9]+]]:_(p5) = G_INTTOPTR [[COPY1]](s32)
; GCN-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](p0), [[C1]]
- ; GCN-NEXT: [[SELECT:%[0-9]+]]:_(p5) = G_SELECT [[ICMP]](s1), [[EXTRACT]], [[C]]
+ ; GCN-NEXT: [[SELECT:%[0-9]+]]:_(p5) = G_SELECT [[ICMP]](s1), [[INTTOPTR]], [[C]]
; GCN-NEXT: $vgpr0 = COPY [[SELECT]](p5)
%0:_(p0) = COPY $vgpr0_vgpr1
%1:_(p5) = G_ADDRSPACE_CAST %0
@@ -255,9 +258,12 @@ body: |
; GCN-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; GCN-NEXT: [[C:%[0-9]+]]:_(p3) = G_CONSTANT i32 -1
; GCN-NEXT: [[C1:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
- ; GCN-NEXT: [[EXTRACT:%[0-9]+]]:_(p3) = G_EXTRACT [[COPY]](p0), 0
+ ; GCN-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY]](p0)
+ ; GCN-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[PTRTOINT]](s64)
+ ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
+ ; GCN-NEXT: [[INTTOPTR:%[0-9]+]]:_(p3) = G_INTTOPTR [[COPY1]](s32)
; GCN-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](p0), [[C1]]
- ; GCN-NEXT: [[SELECT:%[0-9]+]]:_(p3) = G_SELECT [[ICMP]](s1), [[EXTRACT]], [[C]]
+ ; GCN-NEXT: [[SELECT:%[0-9]+]]:_(p3) = G_SELECT [[ICMP]](s1), [[INTTOPTR]], [[C]]
; GCN-NEXT: $vgpr0 = COPY [[SELECT]](p3)
%0:_(p0) = COPY $vgpr0_vgpr1
%1:_(p3) = G_ADDRSPACE_CAST %0
@@ -326,12 +332,18 @@ body: |
; GCN-NEXT: [[UV:%[0-9]+]]:_(p0), [[UV1:%[0-9]+]]:_(p0) = G_UNMERGE_VALUES [[COPY]](<2 x p0>)
; GCN-NEXT: [[C:%[0-9]+]]:_(p3) = G_CONSTANT i32 -1
; GCN-NEXT: [[C1:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
- ; GCN-NEXT: [[EXTRACT:%[0-9]+]]:_(p3) = G_EXTRACT [[UV]](p0), 0
+ ; GCN-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[UV]](p0)
+ ; GCN-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[PTRTOINT]](s64)
+ ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
+ ; GCN-NEXT: [[INTTOPTR:%[0-9]+]]:_(p3) = G_INTTOPTR [[COPY1]](s32)
; GCN-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](p0), [[C1]]
- ; GCN-NEXT: [[SELECT:%[0-9]+]]:_(p3) = G_SELECT [[ICMP]](s1), [[EXTRACT]], [[C]]
- ; GCN-NEXT: [[EXTRACT1:%[0-9]+]]:_(p3) = G_EXTRACT [[UV1]](p0), 0
+ ; GCN-NEXT: [[SELECT:%[0-9]+]]:_(p3) = G_SELECT [[ICMP]](s1), [[INTTOPTR]], [[C]]
+ ; GCN-NEXT: [[PTRTOINT1:%[0-9]+]]:_(s64) = G_PTRTOINT [[UV1]](p0)
+ ; GCN-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[PTRTOINT1]](s64)
+ ; GCN-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV4]](s32)
+ ; GCN-NEXT: [[INTTOPTR1:%[0-9]+]]:_(p3) = G_INTTOPTR [[COPY2]](s32)
; GCN-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](p0), [[C1]]
- ; GCN-NEXT: [[SELECT1:%[0-9]+]]:_(p3) = G_SELECT [[ICMP1]](s1), [[EXTRACT1]], [[C]]
+ ; GCN-NEXT: [[SELECT1:%[0-9]+]]:_(p3) = G_SELECT [[ICMP1]](s1), [[INTTOPTR1]], [[C]]
; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p3>) = G_BUILD_VECTOR [[SELECT]](p3), [[SELECT1]](p3)
; GCN-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x p3>)
%0:_(<2 x p0>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
@@ -410,8 +422,11 @@ body: |
; GCN: liveins: $vgpr0_vgpr1
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
- ; GCN-NEXT: [[EXTRACT:%[0-9]+]]:_(p6) = G_EXTRACT [[COPY]](p4), 0
- ; GCN-NEXT: $vgpr0 = COPY [[EXTRACT]](p6)
+ ; GCN-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY]](p4)
+ ; GCN-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[PTRTOINT]](s64)
+ ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
+ ; GCN-NEXT: [[INTTOPTR:%[0-9]+]]:_(p6) = G_INTTOPTR [[COPY1]](s32)
+ ; GCN-NEXT: $vgpr0 = COPY [[INTTOPTR]](p6)
%0:_(p4) = COPY $vgpr0_vgpr1
%1:_(p6) = G_ADDRSPACE_CAST %0
$vgpr0 = COPY %1
@@ -467,8 +482,11 @@ body: |
; GCN: liveins: $vgpr0_vgpr1
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
- ; GCN-NEXT: [[EXTRACT:%[0-9]+]]:_(p6) = G_EXTRACT [[COPY]](p0), 0
- ; GCN-NEXT: $vgpr0 = COPY [[EXTRACT]](p6)
+ ; GCN-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY]](p0)
+ ; GCN-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[PTRTOINT]](s64)
+ ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
+ ; GCN-NEXT: [[INTTOPTR:%[0-9]+]]:_(p6) = G_INTTOPTR [[COPY1]](s32)
+ ; GCN-NEXT: $vgpr0 = COPY [[INTTOPTR]](p6)
%0:_(p0) = COPY $vgpr0_vgpr1
%1:_(p6) = G_ADDRSPACE_CAST %0
$vgpr0 = COPY %1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
index 83ca3233a6d8f..6460dd35fd658 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
@@ -148,15 +148,19 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s96) = COPY $vgpr0_vgpr1_vgpr2
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s96) = COPY $vgpr3_vgpr4_vgpr5
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:_(s64) = G_EXTRACT [[COPY]](s96), 0
- ; CHECK-NEXT: [[EXTRACT1:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY]](s96), 64
- ; CHECK-NEXT: [[EXTRACT2:%[0-9]+]]:_(s64) = G_EXTRACT [[COPY1]](s96), 0
- ; CHECK-NEXT: [[EXTRACT3:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY1]](s96), 64
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[EXTRACT]], [[EXTRACT2]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[EXTRACT1]], [[EXTRACT3]]
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND]](s64)
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32), [[AND1]](s32)
- ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[MV]](s96)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96)
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
+ ; CHECK-NEXT: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
+ ; CHECK-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s96)
+ ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV6]](s32), [[UV7]](s32)
+ ; CHECK-NEXT: [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s96)
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV11]](s32)
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[MV]], [[MV1]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
+ ; CHECK-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND]](s64)
+ ; CHECK-NEXT: [[MV2:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[UV12]](s32), [[UV13]](s32), [[AND1]](s32)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[MV2]](s96)
%0:_(s96) = COPY $vgpr0_vgpr1_vgpr2
%1:_(s96) = COPY $vgpr3_vgpr4_vgpr5
%2:_(s96) = G_AND %0, %1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
index d981769285f2b..c63b09acc28bf 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
@@ -11,8 +11,9 @@ body: |
; CHECK: liveins: $vgpr0_vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY]](s64), 0
- ; CHECK-NEXT: $vgpr0 = COPY [[EXTRACT]](s32)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
+ ; CHECK-NEXT: $vgpr0 = COPY [[COPY1]](s32)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = G_EXTRACT %0, 0
$vgpr0 = COPY %1
@@ -27,8 +28,9 @@ body: |
; CHECK: liveins: $vgpr0_vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY]](s64), 32
- ; CHECK-NEXT: $vgpr0 = COPY [[EXTRACT]](s32)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
+ ; CHECK-NEXT: $vgpr0 = COPY [[COPY1]](s32)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = G_EXTRACT %0, 32
$vgpr0 = COPY %1
@@ -82,8 +84,9 @@ body: |
; CHECK: liveins: $vgpr0_vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY]](s64), 0
- ; CHECK-NEXT: $vgpr0 = COPY [[EXTRACT]](s32)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
+ ; CHECK-NEXT: $vgpr0 = COPY [[COPY1]](s32)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s48) = G_TRUNC %0
%2:_(s32) = G_EXTRACT %1, 0
@@ -100,8 +103,9 @@ body: |
; CHECK: liveins: $vgpr0_vgpr1_vgpr2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s96) = COPY $vgpr0_vgpr1_vgpr2
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY]](s96), 0
- ; CHECK-NEXT: $vgpr0 = COPY [[EXTRACT]](s32)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
+ ; CHECK-NEXT: $vgpr0 = COPY [[COPY1]](s32)
%0:_(s96) = COPY $vgpr0_vgpr1_vgpr2
%1:_(s32) = G_EXTRACT %0, 0
$vgpr0 = COPY %1
@@ -116,8 +120,9 @@ body: |
; CHECK: liveins: $vgpr0_vgpr1_vgpr2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s96) = COPY $vgpr0_vgpr1_vgpr2
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY]](s96), 32
- ; CHECK-NEXT: $vgpr0 = COPY [[EXTRACT]](s32)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
+ ; CHECK-NEXT: $vgpr0 = COPY [[COPY1]](s32)
%0:_(s96) = COPY $vgpr0_vgpr1_vgpr2
%1:_(s32) = G_EXTRACT %0, 32
$vgpr0 = COPY %1
@@ -132,8 +137,9 @@ body: |
; CHECK: liveins: $vgpr0_vgpr1_vgpr2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s96) = COPY $vgpr0_vgpr1_vgpr2
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY]](s96), 64
- ; CHECK-NEXT: $vgpr0 = COPY [[EXTRACT]](s32)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
+ ; CHECK-NEXT: $vgpr0 = COPY [[COPY1]](s32)
%0:_(s96) = COPY $vgpr0_vgpr1_vgpr2
%1:_(s32) = G_EXTRACT %0, 64
$vgpr0 = COPY %1
@@ -148,8 +154,9 @@ body: |
; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY]](s128), 0
- ; CHECK-NEXT: $vgpr0 = COPY [[EXTRACT]](s32)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s128)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
+ ; CHECK-NEXT: $vgpr0 = COPY [[COPY1]](s32)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s32) = G_EXTRACT %0, 0
$vgpr0 = COPY %1
@@ -164,8 +171,9 @@ body: |
; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY]](s128), 32
- ; CHECK-NEXT: $vgpr0 = COPY [[EXTRACT]](s32)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s128)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
+ ; CHECK-NEXT: $vgpr0 = COPY [[COPY1]](s32)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s32) = G_EXTRACT %0, 32
$vgpr0 = COPY %1
@@ -180,8 +188,9 @@ body: |
; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY]](s128), 64
- ; CHECK-NEXT: $vgpr0 = COPY [[EXTRACT]](s32)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s128)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
+ ; CHECK-NEXT: $vgpr0 = COPY [[COPY1]](s32)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s32) = G_EXTRACT %0, 64
$vgpr0 = COPY %1
@@ -196,8 +205,9 @@ body: |
; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY]](s128), 96
- ; CHECK-NEXT: $vgpr0 = COPY [[EXTRACT]](s32)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s128)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
+ ; CHECK-NEXT: $vgpr0 = COPY [[COPY1]](s32)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s32) = G_EXTRACT %0, 96
$vgpr0 = COPY %1
@@ -315,8 +325,9 @@ body: |
; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY]](s128), 32
- ; CHECK-NEXT: $vgpr0 = COPY [[EXTRACT]](s32)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s128)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
+ ; CHECK-NEXT: $vgpr0 = COPY [[COPY1]](s32)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s32) = G_EXTRACT %0, 32
$vgpr0 = COPY %1
@@ -331,8 +342,9 @@ body: |
; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY]](s128), 64
- ; CHECK-NEXT: $vgpr0 = COPY [[EXTRACT]](s32)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s128)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
+ ; CHECK-NEXT: $vgpr0 = COPY [[COPY1]](s32)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s32) = G_EXTRACT %0, 64
$vgpr0 = COPY %1
@@ -347,8 +359,9 @@ body: |
; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY]](s128), 96
- ; CHECK-NEXT: $vgpr0 = COPY [[EXTRACT]](s32)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s128)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
+ ; CHECK-NEXT: $vgpr0 = COPY [[COPY1]](s32)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s32) = G_EXTRACT %0, 96
$vgpr0 = COPY %1
@@ -752,11 +765,11 @@ body: |
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
; CHECK-NEXT: $vgpr0 = COPY [[LSHR]](s32)
%0:_(s32) = COPY $vgpr0
- %1:_(s8) = G_EXTRACT %0, 16
+ %1:_(s8) = G_EXTRACT %0, 24
%2:_(s32) = G_ANYEXT %1
$vgpr0 = COPY %2
...
@@ -896,9 +909,10 @@ body: |
; CHECK: liveins: $vgpr0_vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:_(s16) = G_EXTRACT [[COPY]](s64), 16
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EXTRACT]](s16)
- ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[C]](s32)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)
+ ; CHECK-NEXT: $vgpr0 = COPY [[TRUNC]](s32)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s16) = G_EXTRACT %0, 16
%2:_(s32) = G_ANYEXT %1
@@ -914,9 +928,10 @@ body: |
; CHECK: liveins: $vgpr0_vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:_(s16) = G_EXTRACT [[COPY]](s64), 32
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EXTRACT]](s16)
- ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[C]](s32)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)
+ ; CHECK-NEXT: $vgpr0 = COPY [[TRUNC]](s32)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s16) = G_EXTRACT %0, 32
%2:_(s32) = G_ANYEXT %1
@@ -932,9 +947,10 @@ body: |
; CHECK: liveins: $vgpr0_vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:_(s16) = G_EXTRACT [[COPY]](s64), 48
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EXTRACT]](s16)
- ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 48
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[C]](s32)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)
+ ; CHECK-NEXT: $vgpr0 = COPY [[TRUNC]](s32)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s16) = G_EXTRACT %0, 48
%2:_(s32) = G_ANYEXT %1
@@ -1137,9 +1153,8 @@ body: |
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:_(s16) = G_EXTRACT [[COPY]](p3), 0
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EXTRACT]](s16)
- ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY]](p3)
+ ; CHECK-NEXT: $vgpr0 = COPY [[PTRTOINT]](s32)
%0:_(p3) = COPY $vgpr0
%1:_(s16) = G_EXTRACT %0, 0
%2:_(s32) = G_ANYEXT %1
@@ -1156,11 +1171,266 @@ body: |
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:_(s16) = G_EXTRACT [[COPY]](p3), 1
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EXTRACT]](s16)
- ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY]](p3)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[PTRTOINT]], [[C]](s32)
+ ; CHECK-NEXT: $vgpr0 = COPY [[LSHR]](s32)
%0:_(p3) = COPY $vgpr0
%1:_(s16) = G_EXTRACT %0, 1
%2:_(s32) = G_ANYEXT %1
$vgpr0 = COPY %2
...
+
+---
+name: test_extract_s24_s32_offset0
+body: |
+ bb.0:
+ liveins: $vgpr0
+
+ ; CHECK-LABEL: name: test_extract_s24_s32_offset0
+ ; CHECK: liveins: $vgpr0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; CHECK-NEXT: $vgpr0 = COPY [[COPY]](s32)
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s24) = G_EXTRACT %0, 0
+ %2:_(s32) = G_ANYEXT %1
+ $vgpr0 = COPY %2
+...
+
+---
+name: test_extract_s24_s64_offset0
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: test_extract_s24_s64_offset0
+ ; CHECK: liveins: $vgpr0_vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK-NEXT: $vgpr0 = COPY [[TRUNC]](s32)
+ %0:_(s64) = COPY $vgpr0_vgpr1
+ %1:_(s24) = G_EXTRACT %0, 0
+ %2:_(s32) = G_ANYEXT %1
+ $vgpr0 = COPY %2
+...
+
+---
+name: test_extract_s24_s64_offset8
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: test_extract_s24_s64_offset8
+ ; CHECK: liveins: $vgpr0_vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[C]](s32)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)
+ ; CHECK-NEXT: $vgpr0 = COPY [[TRUNC]](s32)
+ %0:_(s64) = COPY $vgpr0_vgpr1
+ %1:_(s24) = G_EXTRACT %0, 8
+ %2:_(s32) = G_ANYEXT %1
+ $vgpr0 = COPY %2
+...
+
+---
+name: test_extract_s32_s64_offset1
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: test_extract_s32_s64_offset1
+ ; CHECK: liveins: $vgpr0_vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[C]](s32)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)
+ ; CHECK-NEXT: $vgpr0 = COPY [[TRUNC]](s32)
+ %0:_(s64) = COPY $vgpr0_vgpr1
+ %1:_(s32) = G_EXTRACT %0, 1
+ $vgpr0 = COPY %1
+...
+
+---
+name: test_extract_s48_s64_offset0
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: test_extract_s48_s64_offset0
+ ; CHECK: liveins: $vgpr0_vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[COPY]](s64)
+ %0:_(s64) = COPY $vgpr0_vgpr1
+ %1:_(s48) = G_EXTRACT %0, 0
+ %2:_(s64) = G_ANYEXT %1
+ $vgpr0_vgpr1 = COPY %2
+...
+---
+name: test_extract_s48_s128_offset0
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1_vgpr2_vgpr3
+
+ ; CHECK-LABEL: name: test_extract_s48_s128_offset0
+ ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s128)
+ ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[TRUNC]](s64)
+ %0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ %1:_(s48) = G_EXTRACT %0, 0
+ %2:_(s64) = G_ANYEXT %1
+ $vgpr0_vgpr1 = COPY %2
+...
+---
+name: test_extract_s48_s128_offset32
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1_vgpr2_vgpr3
+
+ ; CHECK-LABEL: name: test_extract_s48_s128_offset32
+ ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C]](s32)
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C]](s32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]]
+ ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[OR]](s64)
+ %0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ %1:_(s48) = G_EXTRACT %0, 32
+ %2:_(s64) = G_ANYEXT %1
+ $vgpr0_vgpr1 = COPY %2
+...
+
+---
+name: test_extract_s64_s128_offset0
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1_vgpr2_vgpr3
+
+ ; CHECK-LABEL: name: test_extract_s64_s128_offset0
+ ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
+ ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[UV]](s64)
+ %0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ %1:_(s64) = G_EXTRACT %0, 0
+ $vgpr0_vgpr1 = COPY %1
+...
+---
+name: test_extract_s64_s128_offset1
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1_vgpr2_vgpr3
+
+ ; CHECK-LABEL: name: test_extract_s64_s128_offset1
+ ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C1]](s32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]]
+ ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[OR]](s64)
+ %0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ %1:_(s64) = G_EXTRACT %0, 1
+ $vgpr0_vgpr1 = COPY %1
+...
+---
+name: test_extract_s64_s128_offset32
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1_vgpr2_vgpr3
+
+ ; CHECK-LABEL: name: test_extract_s64_s128_offset32
+ ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s128)
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV1]](s32), [[UV2]](s32)
+ ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
+ %0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ %1:_(s64) = G_EXTRACT %0, 32
+ $vgpr0_vgpr1 = COPY %1
+...
+---
+name: test_extract_s64_s128_offset64
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1_vgpr2_vgpr3
+
+ ; CHECK-LABEL: name: test_extract_s64_s128_offset64
+ ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
+ ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[UV1]](s64)
+ %0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ %1:_(s64) = G_EXTRACT %0, 64
+ $vgpr0_vgpr1 = COPY %1
+...
+
+---
+name: test_extract_s96_s128_offset0
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1_vgpr2_vgpr3
+
+ ; CHECK-LABEL: name: test_extract_s96_s128_offset0
+ ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s128)
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32), [[UV2]](s32)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[MV]](s96)
+ %0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ %1:_(s96) = G_EXTRACT %0, 0
+ $vgpr0_vgpr1_vgpr2 = COPY %1
+...
+---
+name: test_extract_s96_s128_offset32
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1_vgpr2_vgpr3
+
+ ; CHECK-LABEL: name: test_extract_s96_s128_offset32
+ ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s128)
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[UV1]](s32), [[UV2]](s32), [[UV3]](s32)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[MV]](s96)
+ %0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ %1:_(s96) = G_EXTRACT %0, 32
+ $vgpr0_vgpr1_vgpr2 = COPY %1
+...
+
+---
+name: test_extract_p3_p0_offset0
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+ ; CHECK-LABEL: name: test_extract_p3_p0_offset0
+ ; CHECK: liveins: $vgpr0_vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY]](p0)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[PTRTOINT]](s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
+ ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p3) = G_INTTOPTR [[COPY1]](s32)
+ ; CHECK-NEXT: $vgpr0 = COPY [[INTTOPTR]](p3)
+ %0:_(p0) = COPY $vgpr0_vgpr1
+ %1:_(p3) = G_EXTRACT %0, 0
+ $vgpr0 = COPY %1
+...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def.mir
index 4e4ab1bce4651..5cefe0ef89cf0 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def.mir
@@ -135,10 +135,9 @@ body: |
bb.0:
; CHECK-LABEL: name: test_implicit_def_s448
- ; CHECK: [[DEF:%[0-9]+]]:_(s512) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s448) = G_TRUNC [[DEF]](s512)
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[TRUNC]](s448), 0
- ; CHECK-NEXT: $vgpr0 = COPY [[EXTRACT]](s32)
+ ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+ ; CHECK-NEXT: $vgpr0 = COPY [[COPY]](s32)
%0:_(s448) = G_IMPLICIT_DEF
%1:_(s32) = G_EXTRACT %0, 0
$vgpr0 = COPY %1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
index c9a3060607067..c446f5537bbf1 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
@@ -148,15 +148,19 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s96) = COPY $vgpr0_vgpr1_vgpr2
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s96) = COPY $vgpr3_vgpr4_vgpr5
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:_(s64) = G_EXTRACT [[COPY]](s96), 0
- ; CHECK-NEXT: [[EXTRACT1:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY]](s96), 64
- ; CHECK-NEXT: [[EXTRACT2:%[0-9]+]]:_(s64) = G_EXTRACT [[COPY1]](s96), 0
- ; CHECK-NEXT: [[EXTRACT3:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY1]](s96), 64
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[EXTRACT]], [[EXTRACT2]]
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[EXTRACT1]], [[EXTRACT3]]
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[OR]](s64)
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32), [[OR1]](s32)
- ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[MV]](s96)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96)
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
+ ; CHECK-NEXT: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
+ ; CHECK-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s96)
+ ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV6]](s32), [[UV7]](s32)
+ ; CHECK-NEXT: [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s96)
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV11]](s32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[MV]], [[MV1]]
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[COPY2]], [[COPY3]]
+ ; CHECK-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[OR]](s64)
+ ; CHECK-NEXT: [[MV2:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[UV12]](s32), [[UV13]](s32), [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[MV2]](s96)
%0:_(s96) = COPY $vgpr0_vgpr1_vgpr2
%1:_(s96) = COPY $vgpr3_vgpr4_vgpr5
%2:_(s96) = G_OR %0, %1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir
index be576872313e2..9708910f23f85 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir
@@ -177,15 +177,19 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr6
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY2]](s32), [[C]]
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:_(s64) = G_EXTRACT [[COPY]](s96), 0
- ; CHECK-NEXT: [[EXTRACT1:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY]](s96), 64
- ; CHECK-NEXT: [[EXTRACT2:%[0-9]+]]:_(s64) = G_EXTRACT [[COPY1]](s96), 0
- ; CHECK-NEXT: [[EXTRACT3:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY1]](s96), 64
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[EXTRACT]], [[EXTRACT2]]
- ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[EXTRACT1]], [[EXTRACT3]]
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SELECT]](s64)
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32), [[SELECT1]](s32)
- ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[MV]](s96)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96)
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
+ ; CHECK-NEXT: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96)
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
+ ; CHECK-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s96)
+ ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV6]](s32), [[UV7]](s32)
+ ; CHECK-NEXT: [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s96)
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV11]](s32)
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[MV]], [[MV1]]
+ ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[COPY3]], [[COPY4]]
+ ; CHECK-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SELECT]](s64)
+ ; CHECK-NEXT: [[MV2:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[UV12]](s32), [[UV13]](s32), [[SELECT1]](s32)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[MV2]](s96)
%0:_(s96) = COPY $vgpr0_vgpr1_vgpr2
%1:_(s96) = COPY $vgpr3_vgpr4_vgpr5
%2:_(s32) = COPY $vgpr6
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir
index a635689f66f17..9430fd94a40d2 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir
@@ -148,15 +148,19 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s96) = COPY $vgpr0_vgpr1_vgpr2
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s96) = COPY $vgpr3_vgpr4_vgpr5
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:_(s64) = G_EXTRACT [[COPY]](s96), 0
- ; CHECK-NEXT: [[EXTRACT1:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY]](s96), 64
- ; CHECK-NEXT: [[EXTRACT2:%[0-9]+]]:_(s64) = G_EXTRACT [[COPY1]](s96), 0
- ; CHECK-NEXT: [[EXTRACT3:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY1]](s96), 64
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[EXTRACT]], [[EXTRACT2]]
- ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[EXTRACT1]], [[EXTRACT3]]
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64)
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32), [[XOR1]](s32)
- ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[MV]](s96)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96)
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
+ ; CHECK-NEXT: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
+ ; CHECK-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s96)
+ ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV6]](s32), [[UV7]](s32)
+ ; CHECK-NEXT: [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s96)
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV11]](s32)
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[MV]], [[MV1]]
+ ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[COPY2]], [[COPY3]]
+ ; CHECK-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64)
+ ; CHECK-NEXT: [[MV2:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[UV12]](s32), [[UV13]](s32), [[XOR1]](s32)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[MV2]](s96)
%0:_(s96) = COPY $vgpr0_vgpr1_vgpr2
%1:_(s96) = COPY $vgpr3_vgpr4_vgpr5
%2:_(s96) = G_XOR %0, %1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir
index bce7722a2d12c..2c738f146972e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir
@@ -731,17 +731,14 @@ body: |
; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR2]](s32), [[OR3]](s32)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY [[MV]](s64)
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY [[C3]](s64)
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:_(s48) = G_EXTRACT [[MV1]](s64), 0
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[COPY2]]
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[EXTRACT]](s48)
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[ANYEXT]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[MV1]]
; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND2]](s64)
; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C]](s32)
; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[UV2]], [[C1]]
; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[LSHR2]], [[C]](s32)
; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND3]], [[SHL4]]
- ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV3]], [[C1]]
- ; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
+ ; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[UV3]], [[SHL3]]
; CHECK-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR4]](s32), [[OR5]](s32)
; CHECK-NEXT: [[OR6:%[0-9]+]]:_(s32) = G_OR [[C2]], [[SHL3]]
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[OR6]](s32)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract.mir
index 2997172bb984a..85cb851b6bc3d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract.mir
@@ -1,7 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s
-
-# TODO: Re-enable extract_lo32_i64_a test after AGPR support.
+# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
---
name: extract_lo32_i64_s
@@ -67,571 +66,20 @@ body: |
%1:_(s32) = G_EXTRACT %0, 0
...
-# ---
-# name: extract_lo32_i64_a
-# legalized: true
-#
-# body: |
-# bb.0:
-# liveins: $agpr0_agpr1
-# %0:_(s64) = COPY $agpr0_agpr1
-# %1:_(s32) = G_EXTRACT %0, 0
-# S_ENDPGM 0, implicit %1
-# ...
-
----
-name: extract_s32_from_s96_s
-legalized: true
-
-body: |
- bb.0:
- liveins: $sgpr0_sgpr1_sgpr2
- ; CHECK-LABEL: name: extract_s32_from_s96_s
- ; CHECK: liveins: $sgpr0_sgpr1_sgpr2
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s96) = COPY $sgpr0_sgpr1_sgpr2
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:sgpr(s32) = G_EXTRACT [[COPY]](s96), 0
- ; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](s32)
- %0:_(s96) = COPY $sgpr0_sgpr1_sgpr2
- %1:_(s32) = G_EXTRACT %0, 0
- S_ENDPGM 0, implicit %1
-...
-
----
-name: extract_s32_from_s96_v
-legalized: true
-
-body: |
- bb.0:
- liveins: $vgpr0_vgpr1_vgpr2
- ; CHECK-LABEL: name: extract_s32_from_s96_v
- ; CHECK: liveins: $vgpr0_vgpr1_vgpr2
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s96) = COPY $vgpr0_vgpr1_vgpr2
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:vgpr(s32) = G_EXTRACT [[COPY]](s96), 0
- ; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](s32)
- %0:_(s96) = COPY $vgpr0_vgpr1_vgpr2
- %1:_(s32) = G_EXTRACT %0, 0
- S_ENDPGM 0, implicit %1
-...
-
----
-name: extract_s32_from_s128_s
-legalized: true
-
-body: |
- bb.0:
- liveins: $sgpr0_sgpr1_sgpr2_sgpr3
- ; CHECK-LABEL: name: extract_s32_from_s128_s
- ; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:sgpr(s32) = G_EXTRACT [[COPY]](s128), 0
- ; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](s32)
- %0:_(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
- %1:_(s32) = G_EXTRACT %0, 0
- S_ENDPGM 0, implicit %1
-...
-
----
-name: extract_s32_from_s128_v
-legalized: true
-
-body: |
- bb.0:
- liveins: $vgpr0_vgpr1_vgpr2_vgpr3
- ; CHECK-LABEL: name: extract_s32_from_s128_v
- ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:vgpr(s32) = G_EXTRACT [[COPY]](s128), 0
- ; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](s32)
- %0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- %1:_(s32) = G_EXTRACT %0, 0
- S_ENDPGM 0, implicit %1
-...
-
----
-name: extract_s32_from_s256_s
-legalized: true
-
-body: |
- bb.0:
- liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
- ; CHECK-LABEL: name: extract_s32_from_s256_s
- ; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s256) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:sgpr(s32) = G_EXTRACT [[COPY]](s256), 0
- ; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](s32)
- %0:_(s256) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
- %1:_(s32) = G_EXTRACT %0, 0
- S_ENDPGM 0, implicit %1
-...
-
----
-name: extract_s32_from_s256_v
-legalized: true
-
-body: |
- bb.0:
- liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
- ; CHECK-LABEL: name: extract_s32_from_s256_v
- ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:vgpr(s32) = G_EXTRACT [[COPY]](s256), 0
- ; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](s32)
- %0:_(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
- %1:_(s32) = G_EXTRACT %0, 0
- S_ENDPGM 0, implicit %1
-...
-
----
-name: extract_s32_from_s512_s
-legalized: true
-
-body: |
- bb.0:
- liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
- ; CHECK-LABEL: name: extract_s32_from_s512_s
- ; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s512) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:sgpr(s32) = G_EXTRACT [[COPY]](s512), 0
- ; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](s32)
- %0:_(s512) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
- %1:_(s32) = G_EXTRACT %0, 0
- S_ENDPGM 0, implicit %1
-...
-
---
-name: extract_s32_from_s512_v
+name: extract_lo32_i64_a
legalized: true
body: |
bb.0:
- liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
- ; CHECK-LABEL: name: extract_s32_from_s512_v
- ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+ liveins: $agpr0_agpr1
+ ; CHECK-LABEL: name: extract_lo32_i64_a
+ ; CHECK: liveins: $agpr0_agpr1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s512) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:vgpr(s32) = G_EXTRACT [[COPY]](s512), 0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:agpr(s64) = COPY $agpr0_agpr1
+ ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:agpr(s32) = G_EXTRACT [[COPY]](s64), 0
; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](s32)
- %0:_(s512) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+ %0:_(s64) = COPY $agpr0_agpr1
%1:_(s32) = G_EXTRACT %0, 0
S_ENDPGM 0, implicit %1
...
-
----
-name: extract_s64_from_s96_s
-legalized: true
-
-body: |
- bb.0:
- liveins: $sgpr0_sgpr1_sgpr2
- ; CHECK-LABEL: name: extract_s64_from_s96_s
- ; CHECK: liveins: $sgpr0_sgpr1_sgpr2
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s96) = COPY $sgpr0_sgpr1_sgpr2
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:sgpr(s64) = G_EXTRACT [[COPY]](s96), 0
- ; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](s64)
- %0:_(s96) = COPY $sgpr0_sgpr1_sgpr2
- %1:_(s64) = G_EXTRACT %0, 0
- S_ENDPGM 0, implicit %1
-...
-
----
-name: extract_s64_from_s96_v
-legalized: true
-
-body: |
- bb.0:
- liveins: $vgpr0_vgpr1_vgpr2
- ; CHECK-LABEL: name: extract_s64_from_s96_v
- ; CHECK: liveins: $vgpr0_vgpr1_vgpr2
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s96) = COPY $vgpr0_vgpr1_vgpr2
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:vgpr(s64) = G_EXTRACT [[COPY]](s96), 0
- ; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](s64)
- %0:_(s96) = COPY $vgpr0_vgpr1_vgpr2
- %1:_(s64) = G_EXTRACT %0, 0
- S_ENDPGM 0, implicit %1
-...
-
----
-name: extract_s64_from_s128_s
-legalized: true
-
-body: |
- bb.0:
- liveins: $sgpr0_sgpr1_sgpr2_sgpr3
- ; CHECK-LABEL: name: extract_s64_from_s128_s
- ; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:sgpr(s64) = G_EXTRACT [[COPY]](s128), 0
- ; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](s64)
- %0:_(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
- %1:_(s64) = G_EXTRACT %0, 0
- S_ENDPGM 0, implicit %1
-...
-
----
-name: extract_s64_from_s128_v
-legalized: true
-
-body: |
- bb.0:
- liveins: $vgpr0_vgpr1_vgpr2_vgpr3
- ; CHECK-LABEL: name: extract_s64_from_s128_v
- ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:vgpr(s64) = G_EXTRACT [[COPY]](s128), 0
- ; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](s64)
- %0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- %1:_(s64) = G_EXTRACT %0, 0
- S_ENDPGM 0, implicit %1
-...
-
----
-name: extract_s64_from_s256_s
-legalized: true
-
-body: |
- bb.0:
- liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
- ; CHECK-LABEL: name: extract_s64_from_s256_s
- ; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s256) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:sgpr(s64) = G_EXTRACT [[COPY]](s256), 0
- ; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](s64)
- %0:_(s256) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
- %1:_(s64) = G_EXTRACT %0, 0
- S_ENDPGM 0, implicit %1
-...
-
----
-name: extract_s64_from_s256_v
-legalized: true
-
-body: |
- bb.0:
- liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
- ; CHECK-LABEL: name: extract_s64_from_s256_v
- ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:vgpr(s64) = G_EXTRACT [[COPY]](s256), 0
- ; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](s64)
- %0:_(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
- %1:_(s64) = G_EXTRACT %0, 0
- S_ENDPGM 0, implicit %1
-...
-
----
-name: extract_s64_from_s512_s
-legalized: true
-
-body: |
- bb.0:
- liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
- ; CHECK-LABEL: name: extract_s64_from_s512_s
- ; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s512) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:sgpr(s64) = G_EXTRACT [[COPY]](s512), 0
- ; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](s64)
- %0:_(s512) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
- %1:_(s64) = G_EXTRACT %0, 0
- S_ENDPGM 0, implicit %1
-...
-
----
-name: extract_s64_from_s512_v
-legalized: true
-
-body: |
- bb.0:
- liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
- ; CHECK-LABEL: name: extract_s64_from_s512_v
- ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s512) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:vgpr(s64) = G_EXTRACT [[COPY]](s512), 0
- ; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](s64)
- %0:_(s512) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
- %1:_(s64) = G_EXTRACT %0, 0
- S_ENDPGM 0, implicit %1
-...
-
----
-name: extract_s96_from_s128_s
-legalized: true
-
-body: |
- bb.0:
- liveins: $sgpr0_sgpr1_sgpr2_sgpr3
- ; CHECK-LABEL: name: extract_s96_from_s128_s
- ; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:sgpr(s96) = G_EXTRACT [[COPY]](s128), 0
- ; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](s96)
- %0:_(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
- %1:_(s96) = G_EXTRACT %0, 0
- S_ENDPGM 0, implicit %1
-...
-
----
-name: extract_s96_from_s128_v
-legalized: true
-
-body: |
- bb.0:
- liveins: $vgpr0_vgpr1_vgpr2_vgpr3
- ; CHECK-LABEL: name: extract_s96_from_s128_v
- ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:vgpr(s96) = G_EXTRACT [[COPY]](s128), 0
- ; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](s96)
- %0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- %1:_(s96) = G_EXTRACT %0, 0
- S_ENDPGM 0, implicit %1
-...
-
----
-name: extract_s96_from_s256_s
-legalized: true
-
-body: |
- bb.0:
- liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
- ; CHECK-LABEL: name: extract_s96_from_s256_s
- ; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s256) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:sgpr(s96) = G_EXTRACT [[COPY]](s256), 0
- ; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](s96)
- %0:_(s256) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
- %1:_(s96) = G_EXTRACT %0, 0
- S_ENDPGM 0, implicit %1
-...
-
----
-name: extract_s96_from_s256_v
-legalized: true
-
-body: |
- bb.0:
- liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
- ; CHECK-LABEL: name: extract_s96_from_s256_v
- ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:vgpr(s96) = G_EXTRACT [[COPY]](s256), 0
- ; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](s96)
- %0:_(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
- %1:_(s96) = G_EXTRACT %0, 0
- S_ENDPGM 0, implicit %1
-...
-
----
-name: extract_s96_from_s512_s
-legalized: true
-
-body: |
- bb.0:
- liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
- ; CHECK-LABEL: name: extract_s96_from_s512_s
- ; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s512) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:sgpr(s96) = G_EXTRACT [[COPY]](s512), 0
- ; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](s96)
- %0:_(s512) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
- %1:_(s96) = G_EXTRACT %0, 0
- S_ENDPGM 0, implicit %1
-...
-
----
-name: extract_s96_from_s512_v
-legalized: true
-
-body: |
- bb.0:
- liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
- ; CHECK-LABEL: name: extract_s96_from_s512_v
- ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s512) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:vgpr(s96) = G_EXTRACT [[COPY]](s512), 0
- ; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](s96)
- %0:_(s512) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
- %1:_(s96) = G_EXTRACT %0, 0
- S_ENDPGM 0, implicit %1
-...
-
----
-name: extract_s128_from_s256_s
-legalized: true
-
-body: |
- bb.0:
- liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
- ; CHECK-LABEL: name: extract_s128_from_s256_s
- ; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s256) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:sgpr(s128) = G_EXTRACT [[COPY]](s256), 0
- ; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](s128)
- %0:_(s256) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
- %1:_(s128) = G_EXTRACT %0, 0
- S_ENDPGM 0, implicit %1
-...
-
----
-name: extract_s128_from_s256_v
-legalized: true
-
-body: |
- bb.0:
- liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
- ; CHECK-LABEL: name: extract_s128_from_s256_v
- ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:vgpr(s128) = G_EXTRACT [[COPY]](s256), 0
- ; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](s128)
- %0:_(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
- %1:_(s128) = G_EXTRACT %0, 0
- S_ENDPGM 0, implicit %1
-...
-
----
-name: extract_s128_from_s512_s
-legalized: true
-
-body: |
- bb.0:
- liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
- ; CHECK-LABEL: name: extract_s128_from_s512_s
- ; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s512) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:sgpr(s128) = G_EXTRACT [[COPY]](s512), 0
- ; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](s128)
- %0:_(s512) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
- %1:_(s128) = G_EXTRACT %0, 0
- S_ENDPGM 0, implicit %1
-...
-
----
-name: extract_s128_from_s512_v
-legalized: true
-
-body: |
- bb.0:
- liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
- ; CHECK-LABEL: name: extract_s128_from_s512_v
- ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s512) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:vgpr(s128) = G_EXTRACT [[COPY]](s512), 0
- ; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](s128)
- %0:_(s512) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
- %1:_(s128) = G_EXTRACT %0, 0
- S_ENDPGM 0, implicit %1
-...
-
----
-name: extract_s256_from_s512_s
-legalized: true
-
-body: |
- bb.0:
- liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
- ; CHECK-LABEL: name: extract_s256_from_s512_s
- ; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s512) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:sgpr(s256) = G_EXTRACT [[COPY]](s512), 0
- ; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](s256)
- %0:_(s512) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
- %1:_(s256) = G_EXTRACT %0, 0
- S_ENDPGM 0, implicit %1
-...
-
----
-name: extract_s256_from_s512_v
-legalized: true
-
-body: |
- bb.0:
- liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
- ; CHECK-LABEL: name: extract_s256_from_s512_v
- ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s512) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:vgpr(s256) = G_EXTRACT [[COPY]](s512), 0
- ; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](s256)
- %0:_(s512) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
- %1:_(s256) = G_EXTRACT %0, 0
- S_ENDPGM 0, implicit %1
-...
----
-name: extract_p3_from_p0_v
-legalized: true
-
-body: |
- bb.0:
- liveins: $vgpr0_vgpr1
- ; CHECK-LABEL: name: extract_p3_from_p0_v
- ; CHECK: liveins: $vgpr0_vgpr1
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(p0) = COPY $vgpr0_vgpr1
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:vgpr(p3) = G_EXTRACT [[COPY]](p0), 0
- ; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](p3)
- %0:_(p0) = COPY $vgpr0_vgpr1
- %1:_(p3) = G_EXTRACT %0, 0
- S_ENDPGM 0, implicit %1
-...
-
----
-name: extract_p5_from_p0_v
-legalized: true
-
-body: |
- bb.0:
- liveins: $vgpr0_vgpr1
- ; CHECK-LABEL: name: extract_p5_from_p0_v
- ; CHECK: liveins: $vgpr0_vgpr1
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(p0) = COPY $vgpr0_vgpr1
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:vgpr(p5) = G_EXTRACT [[COPY]](p0), 0
- ; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](p5)
- %0:_(p0) = COPY $vgpr0_vgpr1
- %1:_(p5) = G_EXTRACT %0, 0
- S_ENDPGM 0, implicit %1
-...
-
----
-name: extract_p6_from_p0_s
-legalized: true
-
-body: |
- bb.0:
- liveins: $sgpr0_sgpr1
- ; CHECK-LABEL: name: extract_p6_from_p0_s
- ; CHECK: liveins: $sgpr0_sgpr1
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(p0) = COPY $sgpr0_sgpr1
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:sgpr(p6) = G_EXTRACT [[COPY]](p0), 0
- ; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](p6)
- %0:_(p0) = COPY $sgpr0_sgpr1
- %1:_(p6) = G_EXTRACT %0, 0
- S_ENDPGM 0, implicit %1
-...
>From 967798c7b5373e27f2a6056415aa76677208e0dd Mon Sep 17 00:00:00 2001
From: Vang Thao <vang.thao at amd.com>
Date: Tue, 3 Mar 2026 10:23:24 -0800
Subject: [PATCH 4/6] Move lowering to helper, add pointer support
---
.../CodeGen/GlobalISel/LegalizerHelper.cpp | 27 +-
.../lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 109 +---
llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h | 2 -
.../GlobalISel/artifact-combiner-extract.mir | 52 +-
.../CodeGen/AMDGPU/GlobalISel/global-value.ll | 10 +-
.../AMDGPU/GlobalISel/inst-select-extract.mir | 199 -------
.../AMDGPU/GlobalISel/inst-select-insert.mir | 528 ------------------
.../GlobalISel/legalize-addrspacecast.mir | 30 +-
.../AMDGPU/GlobalISel/legalize-and.mir | 4 +-
.../AMDGPU/GlobalISel/legalize-extract.mir | 219 ++++++--
.../GlobalISel/legalize-implicit-def.mir | 3 +-
.../AMDGPU/GlobalISel/legalize-insert.mir | 442 ++++++++++++---
.../GlobalISel/legalize-load-constant.mir | 69 ++-
.../AMDGPU/GlobalISel/legalize-load-flat.mir | 184 +++++-
.../GlobalISel/legalize-load-global.mir | 138 ++++-
.../CodeGen/AMDGPU/GlobalISel/legalize-or.mir | 4 +-
.../AMDGPU/GlobalISel/legalize-select.mir | 4 +-
.../AMDGPU/GlobalISel/legalize-xor.mir | 4 +-
.../GlobalISel/regbankselect-extract.mir | 85 ---
.../GlobalISel/regbankselect-insert.mir | 187 -------
.../GlobalISel/regbankselect-merge-values.mir | 32 +-
21 files changed, 974 insertions(+), 1358 deletions(-)
delete mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extract.mir
delete mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert.mir
delete mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract.mir
delete mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert.mir
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index e6eec3194b716..fb2da824de04b 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -9436,23 +9436,40 @@ LegalizerHelper::lowerExtract(MachineInstr &MI) {
}
}
- if (DstTy.isScalar() &&
- (SrcTy.isScalar() ||
+ const DataLayout &DL = MIRBuilder.getDataLayout();
+ if ((SrcTy.isPointer() &&
+ DL.isNonIntegralAddressSpace(SrcTy.getAddressSpace())) ||
+ (DstTy.isPointer() &&
+ DL.isNonIntegralAddressSpace(DstTy.getAddressSpace()))) {
+ LLVM_DEBUG(dbgs() << "Not casting non-integral address space integer\n");
+ return UnableToLegalize;
+ }
+
+ if ((DstTy.isScalar() || DstTy.isPointer()) &&
+ (SrcTy.isScalar() || SrcTy.isPointer() ||
(SrcTy.isVector() && DstTy == SrcTy.getElementType()))) {
LLT SrcIntTy = SrcTy;
if (!SrcTy.isScalar()) {
SrcIntTy = LLT::scalar(SrcTy.getSizeInBits());
- SrcReg = MIRBuilder.buildBitcast(SrcIntTy, SrcReg).getReg(0);
+ SrcReg = MIRBuilder.buildCast(SrcIntTy, SrcReg).getReg(0);
}
+ Register ResultReg = DstReg;
+ if (DstTy.isPointer())
+ ResultReg =
+ MRI.createGenericVirtualRegister(LLT::scalar(DstTy.getSizeInBits()));
+
if (Offset == 0)
- MIRBuilder.buildTrunc(DstReg, SrcReg);
+ MIRBuilder.buildTrunc(ResultReg, SrcReg);
else {
auto ShiftAmt = MIRBuilder.buildConstant(SrcIntTy, Offset);
auto Shr = MIRBuilder.buildLShr(SrcIntTy, SrcReg, ShiftAmt);
- MIRBuilder.buildTrunc(DstReg, Shr);
+ MIRBuilder.buildTrunc(ResultReg, Shr);
}
+ if (DstTy.isPointer())
+ MIRBuilder.buildIntToPtr(DstReg, ResultReg);
+
MI.eraseFromParent();
return Legalized;
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index c1b9b0c780c7c..d55f312c2e9cb 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -1938,25 +1938,14 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
return Query.Types[0] != EltTy;
});
- {
- const unsigned BigTyIdx = 0; // destination / result
- const unsigned LitTyIdx = 1; // inserted value
- getActionDefinitionsBuilder(G_INSERT)
- .lowerIf(all(typeIs(LitTyIdx, S16), sizeIs(BigTyIdx, 32)))
+ for (unsigned Op : {G_INSERT, G_EXTRACT}) {
+ unsigned BigTyIdx = Op == G_INSERT ? 0 : 1;
+ unsigned LitTyIdx = Op == G_INSERT ? 1 : 0;
+ getActionDefinitionsBuilder(Op)
.lowerIf([=](const LegalityQuery &Query) {
- // Sub-vector(or single element) insert.
- // TODO: verify immediate offset here since lower only works with
- // whole elements.
const LLT BigTy = Query.Types[BigTyIdx];
return BigTy.isVector();
})
- // FIXME: Multiples of 16 should not be legal.
- .legalIf([=](const LegalityQuery &Query) {
- const LLT BigTy = Query.Types[BigTyIdx];
- const LLT LitTy = Query.Types[LitTyIdx];
- return (BigTy.getSizeInBits() % 32 == 0) &&
- (LitTy.getSizeInBits() % 16 == 0);
- })
.widenScalarIf(
[=](const LegalityQuery &Query) {
const LLT BigTy = Query.Types[BigTyIdx];
@@ -1970,39 +1959,8 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
},
LegalizeMutations::widenScalarOrEltToNextPow2(LitTyIdx, 16))
.moreElementsIf(isSmallOddVector(BigTyIdx), oneMoreElement(BigTyIdx))
- .widenScalarToNextPow2(BigTyIdx, 32);
- }
-
- {
- const unsigned BigTyIdx = 1; // source
- const unsigned LitTyIdx = 0; // destination
- getActionDefinitionsBuilder(G_EXTRACT)
- .lowerIf([=](const LegalityQuery &Query) {
- // Sub-vector(or single element) extract.
- // TODO: verify immediate offset here since lower only works with
- // whole elements.
- const LLT BigTy = Query.Types[BigTyIdx];
- return BigTy.isVector();
- })
- .customIf([=](const LegalityQuery &Query) {
- const LLT BigTy = Query.Types[BigTyIdx];
- const LLT LitTy = Query.Types[LitTyIdx];
- return !LitTy.isVector() && BigTy.getSizeInBits() % 32 == 0;
- })
- .widenScalarIf(
- [=](const LegalityQuery &Query) {
- const LLT BigTy = Query.Types[BigTyIdx];
- return (BigTy.getScalarSizeInBits() < 16);
- },
- LegalizeMutations::widenScalarOrEltToNextPow2(BigTyIdx, 16))
- .widenScalarIf(
- [=](const LegalityQuery &Query) {
- const LLT LitTy = Query.Types[LitTyIdx];
- return (LitTy.getScalarSizeInBits() < 16);
- },
- LegalizeMutations::widenScalarOrEltToNextPow2(LitTyIdx, 16))
- .moreElementsIf(isSmallOddVector(BigTyIdx), oneMoreElement(BigTyIdx))
- .widenScalarToNextPow2(BigTyIdx, 32);
+ .widenScalarToNextPow2(BigTyIdx, 32)
+ .lower();
}
auto &BuildVector =
@@ -2279,8 +2237,6 @@ bool AMDGPULegalizerInfo::legalizeCustom(
case TargetOpcode::G_FMINIMUMNUM:
case TargetOpcode::G_FMAXIMUMNUM:
return legalizeMinNumMaxNum(Helper, MI);
- case TargetOpcode::G_EXTRACT:
- return legalizeExtract(MI, MRI, B);
case TargetOpcode::G_EXTRACT_VECTOR_ELT:
return legalizeExtractVectorElt(MI, MRI, B);
case TargetOpcode::G_INSERT_VECTOR_ELT:
@@ -2916,59 +2872,6 @@ bool AMDGPULegalizerInfo::legalizeMinNumMaxNum(LegalizerHelper &Helper,
return Helper.lowerFMinNumMaxNum(MI) == LegalizerHelper::Legalized;
}
-bool AMDGPULegalizerInfo::legalizeExtract(MachineInstr &MI,
- MachineRegisterInfo &MRI,
- MachineIRBuilder &B) const {
- auto [DstReg, DstTy, SrcReg, SrcTy] = MI.getFirst2RegLLTs();
-
- assert(!SrcTy.isVector() && !DstTy.isVector());
- assert(SrcTy.getSizeInBits() % 32 == 0);
-
- unsigned Offset = MI.getOperand(2).getImm();
- unsigned DstSize = DstTy.getSizeInBits();
- const LLT S32 = LLT::scalar(32);
-
- // For pointer types, work on the integer representation.
- LLT ScalarSrcTy = LLT::scalar(SrcTy.getSizeInBits());
- Register ScalarSrc = SrcReg;
- if (SrcTy.isPointer())
- ScalarSrc = B.buildPtrToInt(ScalarSrcTy, SrcReg).getReg(0);
-
- Register ScalarDst = DstReg;
- if (DstTy.isPointer())
- ScalarDst = MRI.createGenericVirtualRegister(LLT::scalar(DstSize));
-
- // Simple case where Dst and Offset are multiples of 32-bit, we can unmerge
- // and get the subreg(s).
- if (DstSize % 32 == 0 && Offset % 32 == 0) {
- unsigned StartIdx = Offset / 32;
- unsigned DstCount = DstSize / 32;
- auto Unmerge = B.buildUnmerge(S32, ScalarSrc);
- if (DstCount == 1) {
- B.buildCopy(ScalarDst, Unmerge.getReg(StartIdx));
- } else {
- SmallVector<Register, 4> Pieces;
- for (unsigned I = 0; I < DstCount; ++I)
- Pieces.push_back(Unmerge.getReg(StartIdx + I));
- B.buildMergeLikeInstr(ScalarDst, Pieces);
- }
- } else {
- // Let Trunc handle non-trivial cases.
- Register ShiftedSrc = ScalarSrc;
- if (Offset != 0) {
- auto ShiftAmt = B.buildConstant(S32, Offset);
- ShiftedSrc = B.buildLShr(ScalarSrcTy, ScalarSrc, ShiftAmt).getReg(0);
- }
- B.buildTrunc(ScalarDst, ShiftedSrc);
- }
-
- if (DstTy.isPointer())
- B.buildIntToPtr(DstReg, ScalarDst);
-
- MI.eraseFromParent();
- return true;
-}
-
bool AMDGPULegalizerInfo::legalizeExtractVectorElt(
MachineInstr &MI, MachineRegisterInfo &MRI,
MachineIRBuilder &B) const {
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
index fa45c518a5052..1224ee7ac60be 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
@@ -56,8 +56,6 @@ class AMDGPULegalizerInfo final : public LegalizerInfo {
bool legalizeFPTOI(MachineInstr &MI, MachineRegisterInfo &MRI,
MachineIRBuilder &B, bool Signed) const;
bool legalizeMinNumMaxNum(LegalizerHelper &Helper, MachineInstr &MI) const;
- bool legalizeExtract(MachineInstr &MI, MachineRegisterInfo &MRI,
- MachineIRBuilder &B) const;
bool legalizeExtractVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
MachineIRBuilder &B) const;
bool legalizeInsertVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-extract.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-extract.mir
index 623536e5ef8ce..b88febd5cd980 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-extract.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-extract.mir
@@ -71,10 +71,8 @@ name: extract_s32_merge_s128_s64_s64_offset0
body: |
bb.0:
; CHECK-LABEL: name: extract_s32_merge_s128_s64_s64_offset0
- ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64)
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; CHECK-NEXT: $vgpr0 = COPY [[COPY]](s32)
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: $vgpr0 = COPY [[C]](s32)
%0:_(s64) = G_CONSTANT i64 0
%1:_(s64) = G_CONSTANT i64 1
%2:_(s128) = G_MERGE_VALUES %0, %1
@@ -88,10 +86,8 @@ name: extract_s32_merge_s128_s64_s64_offset32
body: |
bb.0:
; CHECK-LABEL: name: extract_s32_merge_s128_s64_s64_offset32
- ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64)
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; CHECK-NEXT: $vgpr0 = COPY [[COPY]](s32)
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: $vgpr0 = COPY [[C]](s32)
%0:_(s64) = G_CONSTANT i64 0
%1:_(s64) = G_CONSTANT i64 1
%2:_(s128) = G_MERGE_VALUES %0, %1
@@ -105,10 +101,8 @@ name: extract_s32_merge_s128_s64_s64_offset64
body: |
bb.0:
; CHECK-LABEL: name: extract_s32_merge_s128_s64_s64_offset64
- ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64)
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; CHECK-NEXT: $vgpr0 = COPY [[COPY]](s32)
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: $vgpr0 = COPY [[C]](s32)
%0:_(s64) = G_CONSTANT i64 0
%1:_(s64) = G_CONSTANT i64 1
%2:_(s128) = G_MERGE_VALUES %0, %1
@@ -123,9 +117,8 @@ body: |
bb.0:
; CHECK-LABEL: name: extract_s32_merge_s128_s64_s64_offset96
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64)
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; CHECK-NEXT: $vgpr0 = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: $vgpr0 = COPY [[C1]](s32)
%0:_(s64) = G_CONSTANT i64 0
%1:_(s64) = G_CONSTANT i64 1
%2:_(s128) = G_MERGE_VALUES %0, %1
@@ -178,10 +171,11 @@ body: |
; CHECK-LABEL: name: extract_s64_merge_s128_s64_s64_offset32
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64)
- ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C1]](s64)
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV1]](s32), [[UV2]](s32)
- ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[C]], [[C2]](s32)
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[C1]], [[C2]](s32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]]
+ ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[OR]](s64)
%0:_(s64) = G_CONSTANT i64 0
%1:_(s64) = G_CONSTANT i64 1
%2:_(s128) = G_MERGE_VALUES %0, %1
@@ -200,7 +194,8 @@ body: |
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C]](s32), [[C1]](s32)
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[MV]], [[C1]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[MV]], [[COPY]](s32)
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)
; CHECK-NEXT: $vgpr0 = COPY [[TRUNC]](s32)
%0:_(s32) = G_CONSTANT i32 0
@@ -271,10 +266,17 @@ name: extract_s64_merge_s96_s32_s32_s32_offset32
body: |
bb.0:
; CHECK-LABEL: name: extract_s64_merge_s96_s32_s32_s32_offset32
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C]](s32), [[C1]](s32)
- ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
+ ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C2]](s32), [[DEF]](s32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[MV]], [[C3]](s32)
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[MV1]], [[C3]](s32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]]
+ ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[OR]](s64)
%0:_(s32) = G_CONSTANT i32 0
%1:_(s32) = G_CONSTANT i32 1
%2:_(s32) = G_CONSTANT i32 1
@@ -346,10 +348,8 @@ name: extract_s32_build_vector_v2s64_s64_s64_offset64
body: |
bb.0:
; CHECK-LABEL: name: extract_s32_build_vector_v2s64_s64_s64_offset64
- ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64)
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; CHECK-NEXT: $vgpr0 = COPY [[COPY]](s32)
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: $vgpr0 = COPY [[C]](s32)
%0:_(s64) = G_CONSTANT i64 0
%1:_(s64) = G_CONSTANT i64 1
%2:_(<2 x s64>) = G_BUILD_VECTOR %0, %1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/global-value.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/global-value.ll
index f99c5f0c8fd55..f98e6d9610922 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/global-value.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/global-value.ll
@@ -143,9 +143,8 @@ define ptr addrspace(6) @external_constant32_got() {
; GCN-NEXT: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p4) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @external_constant32, target-flags(amdgpu-gotprel32-hi) @external_constant32, implicit-def $scc
; GCN-NEXT: [[LOAD:%[0-9]+]]:_(p4) = G_LOAD [[SI_PC_ADD_REL_OFFSET]](p4) :: (dereferenceable invariant load (p4) from got, addrspace 4)
; GCN-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[LOAD]](p4)
- ; GCN-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[PTRTOINT]](s64)
- ; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; GCN-NEXT: [[INTTOPTR:%[0-9]+]]:_(p6) = G_INTTOPTR [[COPY]](s32)
+ ; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[PTRTOINT]](s64)
+ ; GCN-NEXT: [[INTTOPTR:%[0-9]+]]:_(p6) = G_INTTOPTR [[TRUNC]](s32)
; GCN-NEXT: $vgpr0 = COPY [[INTTOPTR]](p6)
; GCN-NEXT: SI_RETURN implicit $vgpr0
;
@@ -163,9 +162,8 @@ define ptr addrspace(6) @internal_constant32_pcrel() {
; GCN: bb.1 (%ir-block.0):
; GCN-NEXT: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p4) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @internal_constant32, target-flags(amdgpu-rel32-hi) @internal_constant32, implicit-def $scc
; GCN-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[SI_PC_ADD_REL_OFFSET]](p4)
- ; GCN-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[PTRTOINT]](s64)
- ; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; GCN-NEXT: [[INTTOPTR:%[0-9]+]]:_(p6) = G_INTTOPTR [[COPY]](s32)
+ ; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[PTRTOINT]](s64)
+ ; GCN-NEXT: [[INTTOPTR:%[0-9]+]]:_(p6) = G_INTTOPTR [[TRUNC]](s32)
; GCN-NEXT: $vgpr0 = COPY [[INTTOPTR]](p6)
; GCN-NEXT: SI_RETURN implicit $vgpr0
;
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extract.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extract.mir
deleted file mode 100644
index b8ef754d5de5e..0000000000000
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extract.mir
+++ /dev/null
@@ -1,199 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s
----
-name: extract512
-legalized: true
-regBankSelected: true
-
-body: |
- bb.0:
- ; CHECK-LABEL: name: extract512
- ; CHECK: [[DEF:%[0-9]+]]:sgpr_512 = IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub7
- ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub8
- ; CHECK-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub9
- ; CHECK-NEXT: [[COPY10:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub10
- ; CHECK-NEXT: [[COPY11:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub11
- ; CHECK-NEXT: [[COPY12:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub12
- ; CHECK-NEXT: [[COPY13:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub13
- ; CHECK-NEXT: [[COPY14:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub14
- ; CHECK-NEXT: [[COPY15:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub15
- ; CHECK-NEXT: $sgpr0 = COPY [[COPY]]
- ; CHECK-NEXT: $sgpr1 = COPY [[COPY1]]
- ; CHECK-NEXT: $sgpr2 = COPY [[COPY2]]
- ; CHECK-NEXT: $sgpr3 = COPY [[COPY3]]
- ; CHECK-NEXT: $sgpr4 = COPY [[COPY4]]
- ; CHECK-NEXT: $sgpr5 = COPY [[COPY5]]
- ; CHECK-NEXT: $sgpr6 = COPY [[COPY6]]
- ; CHECK-NEXT: $sgpr7 = COPY [[COPY7]]
- ; CHECK-NEXT: $sgpr8 = COPY [[COPY8]]
- ; CHECK-NEXT: $sgpr9 = COPY [[COPY9]]
- ; CHECK-NEXT: $sgpr10 = COPY [[COPY10]]
- ; CHECK-NEXT: $sgpr11 = COPY [[COPY11]]
- ; CHECK-NEXT: $sgpr12 = COPY [[COPY12]]
- ; CHECK-NEXT: $sgpr13 = COPY [[COPY13]]
- ; CHECK-NEXT: $sgpr14 = COPY [[COPY14]]
- ; CHECK-NEXT: $sgpr15 = COPY [[COPY15]]
- ; CHECK-NEXT: SI_RETURN_TO_EPILOG $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $sgpr14, $sgpr15
- %0:sgpr(s512) = G_IMPLICIT_DEF
- %1:sgpr(s32) = G_EXTRACT %0:sgpr(s512), 0
- %2:sgpr(s32) = G_EXTRACT %0:sgpr(s512), 32
- %3:sgpr(s32) = G_EXTRACT %0:sgpr(s512), 64
- %4:sgpr(s32) = G_EXTRACT %0:sgpr(s512), 96
- %5:sgpr(s32) = G_EXTRACT %0:sgpr(s512), 128
- %6:sgpr(s32) = G_EXTRACT %0:sgpr(s512), 160
- %7:sgpr(s32) = G_EXTRACT %0:sgpr(s512), 192
- %8:sgpr(s32) = G_EXTRACT %0:sgpr(s512), 224
- %9:sgpr(s32) = G_EXTRACT %0:sgpr(s512), 256
- %10:sgpr(s32) = G_EXTRACT %0:sgpr(s512), 288
- %11:sgpr(s32) = G_EXTRACT %0:sgpr(s512), 320
- %12:sgpr(s32) = G_EXTRACT %0:sgpr(s512), 352
- %13:sgpr(s32) = G_EXTRACT %0:sgpr(s512), 384
- %14:sgpr(s32) = G_EXTRACT %0:sgpr(s512), 416
- %15:sgpr(s32) = G_EXTRACT %0:sgpr(s512), 448
- %16:sgpr(s32) = G_EXTRACT %0:sgpr(s512), 480
- $sgpr0 = COPY %1:sgpr(s32)
- $sgpr1 = COPY %2:sgpr(s32)
- $sgpr2 = COPY %3:sgpr(s32)
- $sgpr3 = COPY %4:sgpr(s32)
- $sgpr4 = COPY %5:sgpr(s32)
- $sgpr5 = COPY %6:sgpr(s32)
- $sgpr6 = COPY %7:sgpr(s32)
- $sgpr7 = COPY %8:sgpr(s32)
- $sgpr8 = COPY %9:sgpr(s32)
- $sgpr9 = COPY %10:sgpr(s32)
- $sgpr10 = COPY %11:sgpr(s32)
- $sgpr11 = COPY %12:sgpr(s32)
- $sgpr12 = COPY %13:sgpr(s32)
- $sgpr13 = COPY %14:sgpr(s32)
- $sgpr14 = COPY %15:sgpr(s32)
- $sgpr15 = COPY %16:sgpr(s32)
- SI_RETURN_TO_EPILOG $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $sgpr14, $sgpr15
-...
-
----
-name: extract_s_s32_s1024
-legalized: true
-regBankSelected: true
-
-body: |
- bb.0:
- ; CHECK-LABEL: name: extract_s_s32_s1024
- ; CHECK: [[DEF:%[0-9]+]]:sgpr_1024 = IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub7
- ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub8
- ; CHECK-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub9
- ; CHECK-NEXT: [[COPY10:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub10
- ; CHECK-NEXT: [[COPY11:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub11
- ; CHECK-NEXT: [[COPY12:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub12
- ; CHECK-NEXT: [[COPY13:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub13
- ; CHECK-NEXT: [[COPY14:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub14
- ; CHECK-NEXT: [[COPY15:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub15
- ; CHECK-NEXT: [[COPY16:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub16
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub17
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub18
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub19
- ; CHECK-NEXT: [[COPY20:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub20
- ; CHECK-NEXT: [[COPY21:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub21
- ; CHECK-NEXT: [[COPY22:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub22
- ; CHECK-NEXT: [[COPY23:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub23
- ; CHECK-NEXT: [[COPY24:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub24
- ; CHECK-NEXT: [[COPY25:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub25
- ; CHECK-NEXT: [[COPY26:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub26
- ; CHECK-NEXT: [[COPY27:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub27
- ; CHECK-NEXT: [[COPY28:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub28
- ; CHECK-NEXT: [[COPY29:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub29
- ; CHECK-NEXT: [[COPY30:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub30
- ; CHECK-NEXT: [[COPY31:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub31
- ; CHECK-NEXT: S_ENDPGM 0, implicit [[DEF]], implicit [[COPY]], implicit [[COPY1]], implicit [[COPY2]], implicit [[COPY3]], implicit [[COPY4]], implicit [[COPY5]], implicit [[COPY6]], implicit [[COPY7]], implicit [[COPY8]], implicit [[COPY9]], implicit [[COPY10]], implicit [[COPY11]], implicit [[COPY12]], implicit [[COPY13]], implicit [[COPY14]], implicit [[COPY15]], implicit [[COPY16]], implicit [[COPY17]], implicit [[COPY18]], implicit [[COPY19]], implicit [[COPY20]], implicit [[COPY21]], implicit [[COPY22]], implicit [[COPY23]], implicit [[COPY24]], implicit [[COPY25]], implicit [[COPY26]], implicit [[COPY27]], implicit [[COPY28]], implicit [[COPY29]], implicit [[COPY30]], implicit [[COPY31]]
- %0:sgpr(s1024) = G_IMPLICIT_DEF
- %1:sgpr(s32) = G_EXTRACT %0:sgpr, 0
- %2:sgpr(s32) = G_EXTRACT %0:sgpr, 32
- %3:sgpr(s32) = G_EXTRACT %0:sgpr, 64
- %4:sgpr(s32) = G_EXTRACT %0:sgpr, 96
- %5:sgpr(s32) = G_EXTRACT %0:sgpr, 128
- %6:sgpr(s32) = G_EXTRACT %0:sgpr, 160
- %7:sgpr(s32) = G_EXTRACT %0:sgpr, 192
- %8:sgpr(s32) = G_EXTRACT %0:sgpr, 224
- %9:sgpr(s32) = G_EXTRACT %0:sgpr, 256
- %10:sgpr(s32) = G_EXTRACT %0:sgpr, 288
- %11:sgpr(s32) = G_EXTRACT %0:sgpr, 320
- %12:sgpr(s32) = G_EXTRACT %0:sgpr, 352
- %13:sgpr(s32) = G_EXTRACT %0:sgpr, 384
- %14:sgpr(s32) = G_EXTRACT %0:sgpr, 416
- %15:sgpr(s32) = G_EXTRACT %0:sgpr, 448
- %16:sgpr(s32) = G_EXTRACT %0:sgpr, 480
-
- %17:sgpr(s32) = G_EXTRACT %0:sgpr, 512
- %18:sgpr(s32) = G_EXTRACT %0:sgpr, 544
- %19:sgpr(s32) = G_EXTRACT %0:sgpr, 576
- %20:sgpr(s32) = G_EXTRACT %0:sgpr, 608
- %21:sgpr(s32) = G_EXTRACT %0:sgpr, 640
- %22:sgpr(s32) = G_EXTRACT %0:sgpr, 672
- %23:sgpr(s32) = G_EXTRACT %0:sgpr, 704
- %24:sgpr(s32) = G_EXTRACT %0:sgpr, 736
- %25:sgpr(s32) = G_EXTRACT %0:sgpr, 768
- %26:sgpr(s32) = G_EXTRACT %0:sgpr, 800
- %27:sgpr(s32) = G_EXTRACT %0:sgpr, 832
- %28:sgpr(s32) = G_EXTRACT %0:sgpr, 864
- %29:sgpr(s32) = G_EXTRACT %0:sgpr, 896
- %30:sgpr(s32) = G_EXTRACT %0:sgpr, 928
- %31:sgpr(s32) = G_EXTRACT %0:sgpr, 960
- %32:sgpr(s32) = G_EXTRACT %0:sgpr, 992
-
- S_ENDPGM 0, implicit %0, implicit %1, implicit %2, implicit %3, implicit %4, implicit %5, implicit %6, implicit %7, implicit %8, implicit %9, implicit %10, implicit %11, implicit %12, implicit %13, implicit %14, implicit %15, implicit %16, implicit %17, implicit %18, implicit %19, implicit %20, implicit %21, implicit %22, implicit %23, implicit %24, implicit %25, implicit %26, implicit %27, implicit %28, implicit %29, implicit %30, implicit %31, implicit %32
-...
-
-# TODO: Handle offset 32
----
-name: extract_sgpr_s64_from_s128
-legalized: true
-regBankSelected: true
-
-body: |
- bb.0:
- ; CHECK-LABEL: name: extract_sgpr_s64_from_s128
- ; CHECK: [[DEF:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY [[DEF]].sub0_sub1
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY [[DEF]].sub2_sub3
- ; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY]], implicit [[COPY1]]
- %0:sgpr(s128) = G_IMPLICIT_DEF
- %1:sgpr(s64) = G_EXTRACT %0, 0
- %2:sgpr(s64) = G_EXTRACT %0, 64
- S_ENDPGM 0, implicit %1, implicit %2
-
-...
-
----
-name: extract_sgpr_s96_from_s128
-legalized: true
-regBankSelected: true
-
-body: |
- bb.0:
- liveins: $sgpr0_sgpr1_sgpr2_sgpr3
- ; CHECK-LABEL: name: extract_sgpr_s96_from_s128
- ; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_96 = COPY [[COPY]].sub0_sub1_sub2
- ; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY1]]
- %0:sgpr(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
- %1:sgpr(s96) = G_EXTRACT %0, 0
- S_ENDPGM 0, implicit %1
-
-...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert.mir
deleted file mode 100644
index 0ae0b70b76d5a..0000000000000
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert.mir
+++ /dev/null
@@ -1,528 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
-
----
-
-name: insert_s512_s32
-legalized: true
-regBankSelected: true
-
-body: |
- bb.0:
- ; CHECK-LABEL: name: insert_s512_s32
- ; CHECK: [[DEF:%[0-9]+]]:sgpr_512 = IMPLICIT_DEF
- ; CHECK-NEXT: [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
- ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[DEF]], [[DEF1]], %subreg.sub0
- ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG]], [[DEF1]], %subreg.sub1
- ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG1]], [[DEF1]], %subreg.sub2
- ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG2]], [[DEF1]], %subreg.sub3
- ; CHECK-NEXT: [[INSERT_SUBREG4:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG3]], [[DEF1]], %subreg.sub4
- ; CHECK-NEXT: [[INSERT_SUBREG5:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG4]], [[DEF1]], %subreg.sub5
- ; CHECK-NEXT: [[INSERT_SUBREG6:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG5]], [[DEF1]], %subreg.sub6
- ; CHECK-NEXT: [[INSERT_SUBREG7:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG6]], [[DEF1]], %subreg.sub7
- ; CHECK-NEXT: [[INSERT_SUBREG8:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG7]], [[DEF1]], %subreg.sub8
- ; CHECK-NEXT: [[INSERT_SUBREG9:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG8]], [[DEF1]], %subreg.sub9
- ; CHECK-NEXT: [[INSERT_SUBREG10:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG9]], [[DEF1]], %subreg.sub10
- ; CHECK-NEXT: [[INSERT_SUBREG11:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG10]], [[DEF1]], %subreg.sub11
- ; CHECK-NEXT: [[INSERT_SUBREG12:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG11]], [[DEF1]], %subreg.sub12
- ; CHECK-NEXT: [[INSERT_SUBREG13:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG12]], [[DEF1]], %subreg.sub13
- ; CHECK-NEXT: [[INSERT_SUBREG14:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG13]], [[DEF1]], %subreg.sub14
- ; CHECK-NEXT: [[INSERT_SUBREG15:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG14]], [[DEF1]], %subreg.sub15
- ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 = COPY [[INSERT_SUBREG15]]
- ; CHECK-NEXT: SI_RETURN_TO_EPILOG $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
- %0:sgpr(s512) = G_IMPLICIT_DEF
- %1:sgpr(s32) = G_IMPLICIT_DEF
- %2:sgpr(s512) = G_INSERT %0:sgpr, %1:sgpr(s32), 0
- %3:sgpr(s512) = G_INSERT %2:sgpr, %1:sgpr(s32), 32
- %4:sgpr(s512) = G_INSERT %3:sgpr, %1:sgpr(s32), 64
- %5:sgpr(s512) = G_INSERT %4:sgpr, %1:sgpr(s32), 96
- %6:sgpr(s512) = G_INSERT %5:sgpr, %1:sgpr(s32), 128
- %7:sgpr(s512) = G_INSERT %6:sgpr, %1:sgpr(s32), 160
- %8:sgpr(s512) = G_INSERT %7:sgpr, %1:sgpr(s32), 192
- %9:sgpr(s512) = G_INSERT %8:sgpr, %1:sgpr(s32), 224
- %10:sgpr(s512) = G_INSERT %9:sgpr, %1:sgpr(s32), 256
- %11:sgpr(s512) = G_INSERT %10:sgpr, %1:sgpr(s32), 288
- %12:sgpr(s512) = G_INSERT %11:sgpr, %1:sgpr(s32), 320
- %13:sgpr(s512) = G_INSERT %12:sgpr, %1:sgpr(s32), 352
- %14:sgpr(s512) = G_INSERT %13:sgpr, %1:sgpr(s32), 384
- %15:sgpr(s512) = G_INSERT %14:sgpr, %1:sgpr(s32), 416
- %16:sgpr(s512) = G_INSERT %15:sgpr, %1:sgpr(s32), 448
- %17:sgpr(s512) = G_INSERT %16:sgpr, %1:sgpr(s32), 480
- $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 = COPY %17:sgpr(s512)
- SI_RETURN_TO_EPILOG $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
-...
-
----
-
-name: insert_v_s64_v_s32_0
-legalized: true
-regBankSelected: true
-
-body: |
- bb.0:
- liveins: $vgpr0_vgpr1, $vgpr2
- ; CHECK-LABEL: name: insert_v_s64_v_s32_0
- ; CHECK: liveins: $vgpr0_vgpr1, $vgpr2
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
- ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vreg_64 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub0
- ; CHECK-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
- %0:vgpr(s64) = COPY $vgpr0_vgpr1
- %1:vgpr(s32) = COPY $vgpr2
- %2:vgpr(s64) = G_INSERT %0, %1, 0
- S_ENDPGM 0, implicit %2
-...
-
----
-
-name: insert_v_s64_v_s32_32
-legalized: true
-regBankSelected: true
-
-body: |
- bb.0:
- liveins: $vgpr0_vgpr1, $vgpr2
- ; CHECK-LABEL: name: insert_v_s64_v_s32_32
- ; CHECK: liveins: $vgpr0_vgpr1, $vgpr2
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
- ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vreg_64 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub1
- ; CHECK-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
- %0:vgpr(s64) = COPY $vgpr0_vgpr1
- %1:vgpr(s32) = COPY $vgpr2
- %2:vgpr(s64) = G_INSERT %0, %1, 32
- S_ENDPGM 0, implicit %2
-...
-
----
-
-name: insert_s_s64_s_s32_0
-legalized: true
-regBankSelected: true
-
-body: |
- bb.0:
- liveins: $sgpr0_sgpr1, $sgpr2
- ; CHECK-LABEL: name: insert_s_s64_s_s32_0
- ; CHECK: liveins: $sgpr0_sgpr1, $sgpr2
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
- ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:sreg_64 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub0
- ; CHECK-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
- %0:sgpr(s64) = COPY $sgpr0_sgpr1
- %1:sgpr(s32) = COPY $sgpr2
- %2:sgpr(s64) = G_INSERT %0, %1, 0
- S_ENDPGM 0, implicit %2
-...
-
----
-
-name: insert_s_s64_s_s32_32
-legalized: true
-regBankSelected: true
-
-body: |
- bb.0:
- liveins: $sgpr0_sgpr1, $sgpr2
- ; CHECK-LABEL: name: insert_s_s64_s_s32_32
- ; CHECK: liveins: $sgpr0_sgpr1, $sgpr2
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
- ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:sreg_64 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub1
- ; CHECK-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
- %0:sgpr(s64) = COPY $sgpr0_sgpr1
- %1:sgpr(s32) = COPY $sgpr2
- %2:sgpr(s64) = G_INSERT %0, %1, 32
- S_ENDPGM 0, implicit %2
-...
-
----
-
-name: insert_s_s64_v_s32_32
-legalized: true
-regBankSelected: true
-
-body: |
- bb.0:
- liveins: $sgpr0_sgpr1, $vgpr0
- ; CHECK-LABEL: name: insert_s_s64_v_s32_32
- ; CHECK: liveins: $sgpr0_sgpr1, $vgpr0
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
- ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vreg_64 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub1
- ; CHECK-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
- %0:sgpr(s64) = COPY $sgpr0_sgpr1
- %1:vgpr(s32) = COPY $vgpr2
- %2:vgpr(s64) = G_INSERT %0, %1, 32
- S_ENDPGM 0, implicit %2
-...
-
----
-
-name: insert_v_s64_s_s32_32
-legalized: true
-regBankSelected: true
-
-body: |
- bb.0:
- liveins: $vgpr0_vgpr1, $sgpr0
- ; CHECK-LABEL: name: insert_v_s64_s_s32_32
- ; CHECK: liveins: $vgpr0_vgpr1, $sgpr0
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vreg_64 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub1
- ; CHECK-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
- %0:vgpr(s64) = COPY $vgpr0_vgpr1
- %1:sgpr(s32) = COPY $sgpr0
- %2:vgpr(s64) = G_INSERT %0, %1, 32
- S_ENDPGM 0, implicit %2
-...
-
----
-
-name: insert_v_s96_v_s64_0
-legalized: true
-regBankSelected: true
-
-body: |
- bb.0:
- liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4
- ; CHECK-LABEL: name: insert_v_s96_v_s64_0
- ; CHECK: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_96 = COPY $vgpr0_vgpr1_vgpr2
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
- ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vreg_96 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub0_sub1
- ; CHECK-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
- %0:vgpr(s96) = COPY $vgpr0_vgpr1_vgpr2
- %1:vgpr(s64) = COPY $vgpr3_vgpr4
- %2:vgpr(s96) = G_INSERT %0, %1, 0
- S_ENDPGM 0, implicit %2
-...
-
----
-
-name: insert_v_s96_v_s64_32
-legalized: true
-regBankSelected: true
-
-body: |
- bb.0:
- liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4
- ; CHECK-LABEL: name: insert_v_s96_v_s64_32
- ; CHECK: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_96 = COPY $vgpr0_vgpr1_vgpr2
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
- ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vreg_96 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub1_sub2
- ; CHECK-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
- %0:vgpr(s96) = COPY $vgpr0_vgpr1_vgpr2
- %1:vgpr(s64) = COPY $vgpr3_vgpr4
- %2:vgpr(s96) = G_INSERT %0, %1, 32
- S_ENDPGM 0, implicit %2
-...
-
----
-
-name: insert_s_s96_s_s64_0
-legalized: true
-regBankSelected: true
-
-body: |
- bb.0:
- liveins: $sgpr0_sgpr1_sgpr2, $sgpr4_sgpr5
- ; CHECK-LABEL: name: insert_s_s96_s_s64_0
- ; CHECK: liveins: $sgpr0_sgpr1_sgpr2, $sgpr4_sgpr5
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_96 = COPY $sgpr0_sgpr1_sgpr2
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5
- ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:sgpr_96 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub0_sub1
- ; CHECK-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
- %0:sgpr(s96) = COPY $sgpr0_sgpr1_sgpr2
- %1:sgpr(s64) = COPY $sgpr4_sgpr5
- %2:sgpr(s96) = G_INSERT %0, %1, 0
- S_ENDPGM 0, implicit %2
-...
-
----
-
-name: insert_s_s128_s_s64_0
-legalized: true
-regBankSelected: true
-
-body: |
- bb.0:
- liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5
- ; CHECK-LABEL: name: insert_s_s128_s_s64_0
- ; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5
- ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:sgpr_128 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub0_sub1
- ; CHECK-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
- %0:sgpr(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
- %1:sgpr(s64) = COPY $sgpr4_sgpr5
- %2:sgpr(s128) = G_INSERT %0, %1, 0
- S_ENDPGM 0, implicit %2
-...
-
-# ---
-
-# name: insert_s_s128_s_s64_32
-# legalized: true
-# regBankSelected: true
-
-# body: |
-# bb.0:
-# liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5
-# %0:sgpr(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
-# %1:sgpr(s64) = COPY $sgpr4_sgpr5
-# %2:sgpr(s128) = G_INSERT %0, %1, 32
-# S_ENDPGM 0, implicit %2
-# ...
-
----
-
-name: insert_s_s128_s_s64_64
-legalized: true
-regBankSelected: true
-
-body: |
- bb.0:
- liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5
- ; CHECK-LABEL: name: insert_s_s128_s_s64_64
- ; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5
- ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:sgpr_128 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub2_sub3
- ; CHECK-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
- %0:sgpr(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
- %1:sgpr(s64) = COPY $sgpr4_sgpr5
- %2:sgpr(s128) = G_INSERT %0, %1, 64
- S_ENDPGM 0, implicit %2
-...
-
----
-
-name: insert_s_v256_v_s64_96
-legalized: true
-regBankSelected: true
-
-body: |
- bb.0:
- liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9
- ; CHECK-LABEL: name: insert_s_v256_v_s64_96
- ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr8_vgpr9
- ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vreg_256 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub3_sub4
- ; CHECK-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
- %0:vgpr(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
- %1:vgpr(s64) = COPY $vgpr8_vgpr9
- %2:vgpr(s256) = G_INSERT %0, %1, 96
- S_ENDPGM 0, implicit %2
-...
-
----
-
-name: insert_s_s256_s_s64_128
-legalized: true
-regBankSelected: true
-
-body: |
- bb.0:
- liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9
- ; CHECK-LABEL: name: insert_s_s256_s_s64_128
- ; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5
- ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:sgpr_256 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub4_sub5
- ; CHECK-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
- %0:sgpr(s256) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
- %1:sgpr(s64) = COPY $sgpr4_sgpr5
- %2:sgpr(s256) = G_INSERT %0, %1, 128
- S_ENDPGM 0, implicit %2
-...
-
-# ---
-
-# name: insert_s_s256_s_s64_160
-# legalized: true
-# regBankSelected: true
-
-# body: |
-# bb.0:
-# liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9
-# %0:sgpr(s256) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
-# %1:sgpr(s64) = COPY $sgpr4_sgpr5
-# %2:sgpr(s256) = G_INSERT %0, %1, 160
-# S_ENDPGM 0, implicit %2
-# ...
-
----
-
-name: insert_s_s128_s_s96_0
-legalized: true
-regBankSelected: true
-
-body: |
- bb.0:
- liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5_sgpr6
- ; CHECK-LABEL: name: insert_s_s128_s_s96_0
- ; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5_sgpr6
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_96 = COPY $sgpr4_sgpr5_sgpr6
- ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:sgpr_128 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub0_sub1_sub2
- ; CHECK-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
- %0:sgpr(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
- %1:sgpr(s96) = COPY $sgpr4_sgpr5_sgpr6
- %2:sgpr(s128) = G_INSERT %0, %1, 0
- S_ENDPGM 0, implicit %2
-...
-
----
-
-name: insert_s_s160_s_s96_0
-legalized: true
-regBankSelected: true
-
-body: |
- bb.0:
- liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4, $sgpr8_sgpr9_sgpr10
- ; CHECK-LABEL: name: insert_s_s160_s_s96_0
- ; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4, $sgpr8_sgpr9_sgpr10
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_160 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_96 = COPY $sgpr8_sgpr9_sgpr10
- ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:sgpr_160 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub0_sub1_sub2
- ; CHECK-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
- %0:sgpr(s160) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4
- %1:sgpr(s96) = COPY $sgpr8_sgpr9_sgpr10
- %2:sgpr(s160) = G_INSERT %0, %1, 0
- S_ENDPGM 0, implicit %2
-...
-
----
-
-name: insert_s_s256_s_s128_0
-legalized: true
-regBankSelected: true
-
-body: |
- bb.0:
- liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11
-
- ; CHECK-LABEL: name: insert_s_s256_s_s128_0
- ; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_128 = COPY $sgpr8_sgpr9_sgpr10_sgpr11
- ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:sgpr_256 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub0_sub1_sub2_sub3
- ; CHECK-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
- %0:sgpr(s256) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
- %1:sgpr(s128) = COPY $sgpr8_sgpr9_sgpr10_sgpr11
- %2:sgpr(s256) = G_INSERT %0, %1, 0
- S_ENDPGM 0, implicit %2
-...
-
----
-
-name: insert_v_s256_v_s128_32
-legalized: true
-regBankSelected: true
-
-body: |
- bb.0:
- liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11
-
- ; CHECK-LABEL: name: insert_v_s256_v_s128_32
- ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_128 = COPY $vgpr8_vgpr9_vgpr10_vgpr11
- ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vreg_256 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub1_sub2_sub3_sub4
- ; CHECK-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
- %0:vgpr(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
- %1:vgpr(s128) = COPY $vgpr8_vgpr9_vgpr10_vgpr11
- %2:vgpr(s256) = G_INSERT %0, %1, 32
- S_ENDPGM 0, implicit %2
-...
-
----
-
-name: insert_v_s256_v_s128_64
-legalized: true
-regBankSelected: true
-
-body: |
- bb.0:
- liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11
-
- ; CHECK-LABEL: name: insert_v_s256_v_s128_64
- ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_128 = COPY $vgpr8_vgpr9_vgpr10_vgpr11
- ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vreg_256 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub2_sub3_sub4_sub5
- ; CHECK-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
- %0:vgpr(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
- %1:vgpr(s128) = COPY $vgpr8_vgpr9_vgpr10_vgpr11
- %2:vgpr(s256) = G_INSERT %0, %1, 64
- S_ENDPGM 0, implicit %2
-...
-
----
-
-name: insert_v_s256_v_s128_96
-legalized: true
-regBankSelected: true
-
-body: |
- bb.0:
- liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11
-
- ; CHECK-LABEL: name: insert_v_s256_v_s128_96
- ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_128 = COPY $vgpr8_vgpr9_vgpr10_vgpr11
- ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vreg_256 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub3_sub4_sub5_sub6
- ; CHECK-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
- %0:vgpr(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
- %1:vgpr(s128) = COPY $vgpr8_vgpr9_vgpr10_vgpr11
- %2:vgpr(s256) = G_INSERT %0, %1, 96
- S_ENDPGM 0, implicit %2
-...
-
----
-
-name: insert_v_s256_v_s128_128
-legalized: true
-regBankSelected: true
-
-body: |
- bb.0:
- liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11
-
- ; CHECK-LABEL: name: insert_v_s256_v_s128_128
- ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_128 = COPY $vgpr8_vgpr9_vgpr10_vgpr11
- ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vreg_256 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub4_sub5_sub6_sub7
- ; CHECK-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
- %0:vgpr(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
- %1:vgpr(s128) = COPY $vgpr8_vgpr9_vgpr10_vgpr11
- %2:vgpr(s256) = G_INSERT %0, %1, 128
- S_ENDPGM 0, implicit %2
-...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir
index 15fee3d567f44..c239f9ab94de1 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir
@@ -187,9 +187,8 @@ body: |
; GCN-NEXT: [[C:%[0-9]+]]:_(p5) = G_CONSTANT i32 -1
; GCN-NEXT: [[C1:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
; GCN-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY]](p0)
- ; GCN-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[PTRTOINT]](s64)
- ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; GCN-NEXT: [[INTTOPTR:%[0-9]+]]:_(p5) = G_INTTOPTR [[COPY1]](s32)
+ ; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[PTRTOINT]](s64)
+ ; GCN-NEXT: [[INTTOPTR:%[0-9]+]]:_(p5) = G_INTTOPTR [[TRUNC]](s32)
; GCN-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](p0), [[C1]]
; GCN-NEXT: [[SELECT:%[0-9]+]]:_(p5) = G_SELECT [[ICMP]](s1), [[INTTOPTR]], [[C]]
; GCN-NEXT: $vgpr0 = COPY [[SELECT]](p5)
@@ -259,9 +258,8 @@ body: |
; GCN-NEXT: [[C:%[0-9]+]]:_(p3) = G_CONSTANT i32 -1
; GCN-NEXT: [[C1:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
; GCN-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY]](p0)
- ; GCN-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[PTRTOINT]](s64)
- ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; GCN-NEXT: [[INTTOPTR:%[0-9]+]]:_(p3) = G_INTTOPTR [[COPY1]](s32)
+ ; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[PTRTOINT]](s64)
+ ; GCN-NEXT: [[INTTOPTR:%[0-9]+]]:_(p3) = G_INTTOPTR [[TRUNC]](s32)
; GCN-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](p0), [[C1]]
; GCN-NEXT: [[SELECT:%[0-9]+]]:_(p3) = G_SELECT [[ICMP]](s1), [[INTTOPTR]], [[C]]
; GCN-NEXT: $vgpr0 = COPY [[SELECT]](p3)
@@ -333,15 +331,13 @@ body: |
; GCN-NEXT: [[C:%[0-9]+]]:_(p3) = G_CONSTANT i32 -1
; GCN-NEXT: [[C1:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
; GCN-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[UV]](p0)
- ; GCN-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[PTRTOINT]](s64)
- ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; GCN-NEXT: [[INTTOPTR:%[0-9]+]]:_(p3) = G_INTTOPTR [[COPY1]](s32)
+ ; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[PTRTOINT]](s64)
+ ; GCN-NEXT: [[INTTOPTR:%[0-9]+]]:_(p3) = G_INTTOPTR [[TRUNC]](s32)
; GCN-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](p0), [[C1]]
; GCN-NEXT: [[SELECT:%[0-9]+]]:_(p3) = G_SELECT [[ICMP]](s1), [[INTTOPTR]], [[C]]
; GCN-NEXT: [[PTRTOINT1:%[0-9]+]]:_(s64) = G_PTRTOINT [[UV1]](p0)
- ; GCN-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[PTRTOINT1]](s64)
- ; GCN-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV4]](s32)
- ; GCN-NEXT: [[INTTOPTR1:%[0-9]+]]:_(p3) = G_INTTOPTR [[COPY2]](s32)
+ ; GCN-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[PTRTOINT1]](s64)
+ ; GCN-NEXT: [[INTTOPTR1:%[0-9]+]]:_(p3) = G_INTTOPTR [[TRUNC1]](s32)
; GCN-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](p0), [[C1]]
; GCN-NEXT: [[SELECT1:%[0-9]+]]:_(p3) = G_SELECT [[ICMP1]](s1), [[INTTOPTR1]], [[C]]
; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p3>) = G_BUILD_VECTOR [[SELECT]](p3), [[SELECT1]](p3)
@@ -423,9 +419,8 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; GCN-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY]](p4)
- ; GCN-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[PTRTOINT]](s64)
- ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; GCN-NEXT: [[INTTOPTR:%[0-9]+]]:_(p6) = G_INTTOPTR [[COPY1]](s32)
+ ; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[PTRTOINT]](s64)
+ ; GCN-NEXT: [[INTTOPTR:%[0-9]+]]:_(p6) = G_INTTOPTR [[TRUNC]](s32)
; GCN-NEXT: $vgpr0 = COPY [[INTTOPTR]](p6)
%0:_(p4) = COPY $vgpr0_vgpr1
%1:_(p6) = G_ADDRSPACE_CAST %0
@@ -483,9 +478,8 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; GCN-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY]](p0)
- ; GCN-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[PTRTOINT]](s64)
- ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; GCN-NEXT: [[INTTOPTR:%[0-9]+]]:_(p6) = G_INTTOPTR [[COPY1]](s32)
+ ; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[PTRTOINT]](s64)
+ ; GCN-NEXT: [[INTTOPTR:%[0-9]+]]:_(p6) = G_INTTOPTR [[TRUNC]](s32)
; GCN-NEXT: $vgpr0 = COPY [[INTTOPTR]](p6)
%0:_(p0) = COPY $vgpr0_vgpr1
%1:_(p6) = G_ADDRSPACE_CAST %0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
index 6460dd35fd658..b679d783751e4 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
@@ -151,13 +151,11 @@ body: |
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96)
; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
; CHECK-NEXT: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
; CHECK-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s96)
; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV6]](s32), [[UV7]](s32)
; CHECK-NEXT: [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s96)
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV11]](s32)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[MV]], [[MV1]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV5]], [[UV11]]
; CHECK-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND]](s64)
; CHECK-NEXT: [[MV2:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[UV12]](s32), [[UV13]](s32), [[AND1]](s32)
; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[MV2]](s96)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
index c63b09acc28bf..4d55b2981280d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
@@ -11,9 +11,8 @@ body: |
; CHECK: liveins: $vgpr0_vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; CHECK-NEXT: $vgpr0 = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK-NEXT: $vgpr0 = COPY [[TRUNC]](s32)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = G_EXTRACT %0, 0
$vgpr0 = COPY %1
@@ -28,9 +27,10 @@ body: |
; CHECK: liveins: $vgpr0_vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; CHECK-NEXT: $vgpr0 = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[C]](s32)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)
+ ; CHECK-NEXT: $vgpr0 = COPY [[TRUNC]](s32)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = G_EXTRACT %0, 32
$vgpr0 = COPY %1
@@ -84,9 +84,8 @@ body: |
; CHECK: liveins: $vgpr0_vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; CHECK-NEXT: $vgpr0 = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK-NEXT: $vgpr0 = COPY [[TRUNC]](s32)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s48) = G_TRUNC %0
%2:_(s32) = G_EXTRACT %1, 0
@@ -104,8 +103,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s96) = COPY $vgpr0_vgpr1_vgpr2
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; CHECK-NEXT: $vgpr0 = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)
%0:_(s96) = COPY $vgpr0_vgpr1_vgpr2
%1:_(s32) = G_EXTRACT %0, 0
$vgpr0 = COPY %1
@@ -121,8 +119,15 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s96) = COPY $vgpr0_vgpr1_vgpr2
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; CHECK-NEXT: $vgpr0 = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
+ ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV2]](s32), [[DEF]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[MV]], [[C]](s32)
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[MV1]], [[C]](s32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]]
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[OR]](s64)
+ ; CHECK-NEXT: $vgpr0 = COPY [[TRUNC]](s32)
%0:_(s96) = COPY $vgpr0_vgpr1_vgpr2
%1:_(s32) = G_EXTRACT %0, 32
$vgpr0 = COPY %1
@@ -138,8 +143,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s96) = COPY $vgpr0_vgpr1_vgpr2
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; CHECK-NEXT: $vgpr0 = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: $vgpr0 = COPY [[UV2]](s32)
%0:_(s96) = COPY $vgpr0_vgpr1_vgpr2
%1:_(s32) = G_EXTRACT %0, 64
$vgpr0 = COPY %1
@@ -154,9 +158,8 @@ body: |
; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s128)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; CHECK-NEXT: $vgpr0 = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s128)
+ ; CHECK-NEXT: $vgpr0 = COPY [[TRUNC]](s32)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s32) = G_EXTRACT %0, 0
$vgpr0 = COPY %1
@@ -171,9 +174,13 @@ body: |
; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s128)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; CHECK-NEXT: $vgpr0 = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C]](s32)
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C]](s32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]]
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[OR]](s64)
+ ; CHECK-NEXT: $vgpr0 = COPY [[TRUNC]](s32)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s32) = G_EXTRACT %0, 32
$vgpr0 = COPY %1
@@ -188,9 +195,9 @@ body: |
; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s128)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; CHECK-NEXT: $vgpr0 = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[UV1]](s64)
+ ; CHECK-NEXT: $vgpr0 = COPY [[TRUNC]](s32)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s32) = G_EXTRACT %0, 64
$vgpr0 = COPY %1
@@ -205,9 +212,11 @@ body: |
; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s128)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; CHECK-NEXT: $vgpr0 = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[C]](s32)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)
+ ; CHECK-NEXT: $vgpr0 = COPY [[TRUNC]](s32)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s32) = G_EXTRACT %0, 96
$vgpr0 = COPY %1
@@ -325,9 +334,13 @@ body: |
; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s128)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; CHECK-NEXT: $vgpr0 = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C]](s32)
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C]](s32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]]
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[OR]](s64)
+ ; CHECK-NEXT: $vgpr0 = COPY [[TRUNC]](s32)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s32) = G_EXTRACT %0, 32
$vgpr0 = COPY %1
@@ -342,9 +355,9 @@ body: |
; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s128)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; CHECK-NEXT: $vgpr0 = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[UV1]](s64)
+ ; CHECK-NEXT: $vgpr0 = COPY [[TRUNC]](s32)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s32) = G_EXTRACT %0, 64
$vgpr0 = COPY %1
@@ -359,9 +372,11 @@ body: |
; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s128)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; CHECK-NEXT: $vgpr0 = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[C]](s32)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)
+ ; CHECK-NEXT: $vgpr0 = COPY [[TRUNC]](s32)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s32) = G_EXTRACT %0, 96
$vgpr0 = COPY %1
@@ -1298,8 +1313,8 @@ body: |
; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C]](s32)
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C]](s32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]]
@@ -1320,8 +1335,8 @@ body: |
; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
- ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[UV]](s64)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s128)
+ ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[TRUNC]](s64)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s64) = G_EXTRACT %0, 0
$vgpr0_vgpr1 = COPY %1
@@ -1336,8 +1351,8 @@ body: |
; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C]](s32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C1]](s32)
@@ -1357,9 +1372,12 @@ body: |
; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s128)
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV1]](s32), [[UV2]](s32)
- ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C]](s32)
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C]](s32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]]
+ ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[OR]](s64)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s64) = G_EXTRACT %0, 32
$vgpr0_vgpr1 = COPY %1
@@ -1391,9 +1409,8 @@ body: |
; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s128)
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32), [[UV2]](s32)
- ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[MV]](s96)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s96) = G_TRUNC [[COPY]](s128)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[TRUNC]](s96)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s96) = G_EXTRACT %0, 0
$vgpr0_vgpr1_vgpr2 = COPY %1
@@ -1408,9 +1425,15 @@ body: |
; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s128)
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[UV1]](s32), [[UV2]](s32), [[UV3]](s32)
- ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[MV]](s96)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C]](s32)
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C]](s32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]]
+ ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[C]](s32)
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[LSHR1]](s64)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s96) = G_TRUNC [[MV]](s128)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[TRUNC]](s96)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s96) = G_EXTRACT %0, 32
$vgpr0_vgpr1_vgpr2 = COPY %1
@@ -1426,11 +1449,103 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY]](p0)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[PTRTOINT]](s64)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p3) = G_INTTOPTR [[COPY1]](s32)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[PTRTOINT]](s64)
+ ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p3) = G_INTTOPTR [[TRUNC]](s32)
; CHECK-NEXT: $vgpr0 = COPY [[INTTOPTR]](p3)
%0:_(p0) = COPY $vgpr0_vgpr1
%1:_(p3) = G_EXTRACT %0, 0
$vgpr0 = COPY %1
...
+
+---
+name: test_extract_s90_s128_offset9
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1_vgpr2_vgpr3
+
+ ; CHECK-LABEL: name: test_extract_s90_s128_offset9
+ ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 9
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 55
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C1]](s32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]]
+ ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[C]](s32)
+ ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LSHR1]](s64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C2]](s32)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](s32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 2
+ ; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[C3]](s16)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 4
+ ; CHECK-NEXT: [[LSHR4:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[C4]](s16)
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s16) = G_CONSTANT i16 6
+ ; CHECK-NEXT: [[LSHR5:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[C5]](s16)
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
+ ; CHECK-NEXT: [[LSHR6:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[C6]](s16)
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s16) = G_CONSTANT i16 10
+ ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s16) = G_CONSTANT i16 12
+ ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s16) = G_CONSTANT i16 14
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s16) = G_CONSTANT i16 3
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C10]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[LSHR3]], [[C10]]
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[AND1]], [[C3]](s16)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND]], [[SHL1]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s16) = G_AND [[LSHR4]], [[C10]]
+ ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s16) = G_SHL [[AND2]], [[C4]](s16)
+ ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s16) = G_OR [[OR1]], [[SHL2]]
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s16) = G_AND [[LSHR5]], [[C10]]
+ ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s16) = G_SHL [[AND3]], [[C5]](s16)
+ ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s16) = G_OR [[OR2]], [[SHL3]]
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s16) = G_AND [[LSHR6]], [[C10]]
+ ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s16) = G_SHL [[AND4]], [[C6]](s16)
+ ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s16) = G_OR [[OR3]], [[SHL4]]
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[DEF]](s32)
+ ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C10]]
+ ; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s16) = G_SHL [[AND5]], [[C7]](s16)
+ ; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s16) = G_OR [[OR4]], [[SHL5]]
+ ; CHECK-NEXT: [[SHL6:%[0-9]+]]:_(s16) = G_SHL [[AND5]], [[C8]](s16)
+ ; CHECK-NEXT: [[OR6:%[0-9]+]]:_(s16) = G_OR [[OR5]], [[SHL6]]
+ ; CHECK-NEXT: [[SHL7:%[0-9]+]]:_(s16) = G_SHL [[AND5]], [[C9]](s16)
+ ; CHECK-NEXT: [[OR7:%[0-9]+]]:_(s16) = G_OR [[OR6]], [[SHL7]]
+ ; CHECK-NEXT: [[SHL8:%[0-9]+]]:_(s16) = G_SHL [[AND5]], [[C3]](s16)
+ ; CHECK-NEXT: [[OR8:%[0-9]+]]:_(s16) = G_OR [[AND5]], [[SHL8]]
+ ; CHECK-NEXT: [[SHL9:%[0-9]+]]:_(s16) = G_SHL [[AND5]], [[C4]](s16)
+ ; CHECK-NEXT: [[OR9:%[0-9]+]]:_(s16) = G_OR [[OR8]], [[SHL9]]
+ ; CHECK-NEXT: [[SHL10:%[0-9]+]]:_(s16) = G_SHL [[AND5]], [[C5]](s16)
+ ; CHECK-NEXT: [[OR10:%[0-9]+]]:_(s16) = G_OR [[OR9]], [[SHL10]]
+ ; CHECK-NEXT: [[SHL11:%[0-9]+]]:_(s16) = G_SHL [[AND5]], [[C6]](s16)
+ ; CHECK-NEXT: [[OR11:%[0-9]+]]:_(s16) = G_OR [[OR10]], [[SHL11]]
+ ; CHECK-NEXT: [[OR12:%[0-9]+]]:_(s16) = G_OR [[OR11]], [[SHL5]]
+ ; CHECK-NEXT: [[OR13:%[0-9]+]]:_(s16) = G_OR [[OR12]], [[SHL6]]
+ ; CHECK-NEXT: [[OR14:%[0-9]+]]:_(s16) = G_OR [[OR13]], [[SHL7]]
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY [[OR8]](s16)
+ ; CHECK-NEXT: [[OR15:%[0-9]+]]:_(s16) = G_OR [[COPY1]], [[SHL9]]
+ ; CHECK-NEXT: [[OR16:%[0-9]+]]:_(s16) = G_OR [[OR15]], [[SHL10]]
+ ; CHECK-NEXT: [[OR17:%[0-9]+]]:_(s16) = G_OR [[OR16]], [[SHL11]]
+ ; CHECK-NEXT: [[OR18:%[0-9]+]]:_(s16) = G_OR [[OR17]], [[SHL5]]
+ ; CHECK-NEXT: [[OR19:%[0-9]+]]:_(s16) = G_OR [[OR18]], [[SHL6]]
+ ; CHECK-NEXT: [[OR20:%[0-9]+]]:_(s16) = G_OR [[OR19]], [[SHL7]]
+ ; CHECK-NEXT: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[UV2]], [[C11]]
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR7]](s16)
+ ; CHECK-NEXT: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[ZEXT]], [[C2]](s32)
+ ; CHECK-NEXT: [[OR21:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL12]]
+ ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR14]](s16)
+ ; CHECK-NEXT: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[OR20]](s16)
+ ; CHECK-NEXT: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[ZEXT2]], [[C2]](s32)
+ ; CHECK-NEXT: [[OR22:%[0-9]+]]:_(s32) = G_OR [[ZEXT1]], [[SHL13]]
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR21]](s32), [[OR22]](s32)
+ ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s192) = G_MERGE_VALUES [[OR]](s64), [[MV]](s64), [[DEF1]](s64)
+ ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s96) = G_TRUNC [[MV1]](s192)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[TRUNC2]](s96)
+ %0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ %1:_(s90) = G_EXTRACT %0, 9
+ %2:_(s96) = G_ANYEXT %1
+ $vgpr0_vgpr1_vgpr2 = COPY %2
+...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def.mir
index 5cefe0ef89cf0..d8503ecd7df20 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def.mir
@@ -136,8 +136,7 @@ body: |
; CHECK-LABEL: name: test_implicit_def_s448
; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
- ; CHECK-NEXT: $vgpr0 = COPY [[COPY]](s32)
+ ; CHECK-NEXT: $vgpr0 = COPY [[DEF]](s32)
%0:_(s448) = G_IMPLICIT_DEF
%1:_(s32) = G_EXTRACT %0, 0
$vgpr0 = COPY %1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert.mir
index 495740be8d7c8..554340ca88af1 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert.mir
@@ -12,8 +12,12 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; CHECK-NEXT: [[INSERT:%[0-9]+]]:_(s64) = G_INSERT [[COPY]], [[COPY1]](s32), 0
- ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[INSERT]](s64)
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY1]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4294967296
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[ZEXT]]
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY [[OR]](s64)
+ ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[COPY2]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = COPY $vgpr2
%2:_(s64) = G_INSERT %0, %1, 0
@@ -30,8 +34,14 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; CHECK-NEXT: [[INSERT:%[0-9]+]]:_(s64) = G_INSERT [[COPY]], [[COPY1]](s32), 32
- ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[INSERT]](s64)
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY1]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ZEXT]], [[C]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]]
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[SHL]]
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY [[OR]](s64)
+ ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[COPY2]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = COPY $vgpr2
%2:_(s64) = G_INSERT %0, %1, 32
@@ -49,8 +59,14 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; CHECK-NEXT: [[INSERT:%[0-9]+]]:_(s64) = G_INSERT [[COPY]], [[COPY1]](s32), 16
- ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[INSERT]](s64)
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY1]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ZEXT]], [[C]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -281474976645121
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]]
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[SHL]]
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY [[OR]](s64)
+ ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[COPY2]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = COPY $vgpr2
%2:_(s64) = G_INSERT %0, %1, 16
@@ -68,8 +84,23 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s96) = COPY $vgpr0_vgpr1_vgpr2
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; CHECK-NEXT: [[INSERT:%[0-9]+]]:_(s96) = G_INSERT [[COPY]], [[COPY1]](s32), 0
- ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[INSERT]](s96)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
+ ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV2]](s32), [[DEF]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY1]](s32), [[C]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4294967296
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[MV]], [[C2]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[MV1]], [[C3]]
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[MV2]]
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[C1]]
+ ; CHECK-NEXT: [[MV3:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[OR1]](s64)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s128) = COPY [[MV3]](s128)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s96) = G_TRUNC [[COPY2]](s128)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[TRUNC]](s96)
%0:_(s96) = COPY $vgpr0_vgpr1_vgpr2
%1:_(s32) = COPY $vgpr3
%2:_(s96) = G_INSERT %0, %1, 0
@@ -86,8 +117,28 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s96) = COPY $vgpr0_vgpr1_vgpr2
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; CHECK-NEXT: [[INSERT:%[0-9]+]]:_(s96) = G_INSERT [[COPY]], [[COPY1]](s32), 32
- ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[INSERT]](s96)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
+ ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV2]](s32), [[DEF]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY1]](s32), [[C]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[MV2]], [[C2]](s32)
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[C1]], [[C2]](s32)
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[MV2]], [[C2]](s32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]]
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[MV]], [[C3]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[MV1]], [[C4]]
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND]], [[SHL]]
+ ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[OR]]
+ ; CHECK-NEXT: [[MV3:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR1]](s64), [[OR2]](s64)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s128) = COPY [[MV3]](s128)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s96) = G_TRUNC [[COPY2]](s128)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[TRUNC]](s96)
%0:_(s96) = COPY $vgpr0_vgpr1_vgpr2
%1:_(s32) = COPY $vgpr3
%2:_(s96) = G_INSERT %0, %1, 32
@@ -104,8 +155,23 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s96) = COPY $vgpr0_vgpr1_vgpr2
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; CHECK-NEXT: [[INSERT:%[0-9]+]]:_(s96) = G_INSERT [[COPY]], [[COPY1]](s32), 64
- ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[INSERT]](s96)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
+ ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV2]](s32), [[DEF]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY1]](s32), [[C]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4294967296
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[MV]], [[C2]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[MV1]], [[C3]]
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[C1]]
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[MV2]]
+ ; CHECK-NEXT: [[MV3:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[OR1]](s64)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s128) = COPY [[MV3]](s128)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s96) = G_TRUNC [[COPY2]](s128)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[TRUNC]](s96)
%0:_(s96) = COPY $vgpr0_vgpr1_vgpr2
%1:_(s32) = COPY $vgpr3
%2:_(s96) = G_INSERT %0, %1, 64
@@ -122,8 +188,19 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; CHECK-NEXT: [[INSERT:%[0-9]+]]:_(s128) = G_INSERT [[COPY]], [[COPY1]](s32), 0
- ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[INSERT]](s128)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY1]](s32), [[C]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4294967296
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[UV]], [[C2]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[UV1]], [[C3]]
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[MV]]
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[C1]]
+ ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[OR1]](s64)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s128) = COPY [[MV1]](s128)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[COPY2]](s128)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s32) = COPY $vgpr4
%2:_(s128) = G_INSERT %0, %1, 0
@@ -140,8 +217,24 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; CHECK-NEXT: [[INSERT:%[0-9]+]]:_(s128) = G_INSERT [[COPY]], [[COPY1]](s32), 32
- ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[INSERT]](s128)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY1]](s32), [[C]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[MV]], [[C2]](s32)
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[C1]], [[C2]](s32)
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[MV]], [[C2]](s32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]]
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[UV]], [[C3]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[UV1]], [[C4]]
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND]], [[SHL]]
+ ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[OR]]
+ ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR1]](s64), [[OR2]](s64)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s128) = COPY [[MV1]](s128)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[COPY2]](s128)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s32) = COPY $vgpr4
%2:_(s128) = G_INSERT %0, %1, 32
@@ -158,8 +251,19 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; CHECK-NEXT: [[INSERT:%[0-9]+]]:_(s128) = G_INSERT [[COPY]], [[COPY1]](s32), 64
- ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[INSERT]](s128)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY1]](s32), [[C]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4294967296
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[UV]], [[C2]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[UV1]], [[C3]]
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[C1]]
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[MV]]
+ ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[OR1]](s64)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s128) = COPY [[MV1]](s128)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[COPY2]](s128)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s32) = COPY $vgpr4
%2:_(s128) = G_INSERT %0, %1, 64
@@ -176,8 +280,21 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; CHECK-NEXT: [[INSERT:%[0-9]+]]:_(s128) = G_INSERT [[COPY]], [[COPY1]](s32), 96
- ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[INSERT]](s128)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY1]](s32), [[C]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[MV]], [[C2]](s32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[UV]], [[C3]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[UV1]], [[C4]]
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[C1]]
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[SHL]]
+ ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[OR1]](s64)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s128) = COPY [[MV1]](s128)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[COPY2]](s128)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s32) = COPY $vgpr4
%2:_(s128) = G_INSERT %0, %1, 96
@@ -194,8 +311,16 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr4_vgpr5
- ; CHECK-NEXT: [[INSERT:%[0-9]+]]:_(s128) = G_INSERT [[COPY]], [[COPY1]](s64), 0
- ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[INSERT]](s128)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[UV]], [[C]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[UV1]], [[C1]]
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[COPY1]]
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[C]]
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[OR1]](s64)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s128) = COPY [[MV]](s128)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[COPY2]](s128)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s64) = COPY $vgpr4_vgpr5
%2:_(s128) = G_INSERT %0, %1, 0
@@ -212,8 +337,22 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr4_vgpr5
- ; CHECK-NEXT: [[INSERT:%[0-9]+]]:_(s128) = G_INSERT [[COPY]], [[COPY1]](s64), 32
- ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[INSERT]](s128)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C1]](s32)
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[C]], [[C1]](s32)
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[C1]](s32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4294967296
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[UV]], [[C2]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[UV1]], [[C3]]
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND]], [[SHL]]
+ ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[OR]]
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR1]](s64), [[OR2]](s64)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s128) = COPY [[MV]](s128)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[COPY2]](s128)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s64) = COPY $vgpr4_vgpr5
%2:_(s128) = G_INSERT %0, %1, 32
@@ -230,8 +369,16 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr4_vgpr5
- ; CHECK-NEXT: [[INSERT:%[0-9]+]]:_(s128) = G_INSERT [[COPY]], [[COPY1]](s64), 64
- ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[INSERT]](s128)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[UV]], [[C1]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[UV1]], [[C]]
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[C]]
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[COPY1]]
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[OR1]](s64)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s128) = COPY [[MV]](s128)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[COPY2]](s128)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s64) = COPY $vgpr4_vgpr5
%2:_(s128) = G_INSERT %0, %1, 64
@@ -248,8 +395,20 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s96) = COPY $vgpr4_vgpr5_vgpr6
- ; CHECK-NEXT: [[INSERT:%[0-9]+]]:_(s128) = G_INSERT [[COPY]], [[COPY1]](s96), 0
- ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[INSERT]](s128)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s96)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
+ ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV2]](s32), [[C]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4294967296
+ ; CHECK-NEXT: [[UV3:%[0-9]+]]:_(s64), [[UV4:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[UV3]], [[C1]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[UV4]], [[C2]]
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[MV]]
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[MV1]]
+ ; CHECK-NEXT: [[MV2:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[OR1]](s64)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s128) = COPY [[MV2]](s128)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[COPY2]](s128)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s96) = COPY $vgpr4_vgpr5_vgpr6
%2:_(s128) = G_INSERT %0, %1, 0
@@ -266,8 +425,25 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s96) = COPY $vgpr4_vgpr5_vgpr6
- ; CHECK-NEXT: [[INSERT:%[0-9]+]]:_(s128) = G_INSERT [[COPY]], [[COPY1]](s96), 32
- ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[INSERT]](s128)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s96)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
+ ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV2]](s32), [[C]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[MV]], [[C2]](s32)
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[MV1]], [[C2]](s32)
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[MV]], [[C2]](s32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]]
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
+ ; CHECK-NEXT: [[UV3:%[0-9]+]]:_(s64), [[UV4:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[UV3]], [[C3]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[UV4]], [[C1]]
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND]], [[SHL]]
+ ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[OR]]
+ ; CHECK-NEXT: [[MV2:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR1]](s64), [[OR2]](s64)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s128) = COPY [[MV2]](s128)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[COPY2]](s128)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s96) = COPY $vgpr4_vgpr5_vgpr6
%2:_(s128) = G_INSERT %0, %1, 32
@@ -284,8 +460,13 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; CHECK-NEXT: [[INSERT:%[0-9]+]]:_(p0) = G_INSERT [[COPY]], [[COPY1]](s32), 0
- ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[INSERT]](p0)
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY]](p0)
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY1]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4294967296
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[PTRTOINT]], [[C]]
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[ZEXT]]
+ ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[OR]](s64)
+ ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[INTTOPTR]](p0)
%0:_(p0) = COPY $vgpr0_vgpr1
%1:_(s32) = COPY $vgpr2
%2:_(p0) = G_INSERT %0, %1, 0
@@ -302,8 +483,15 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; CHECK-NEXT: [[INSERT:%[0-9]+]]:_(p0) = G_INSERT [[COPY]], [[COPY1]](s32), 32
- ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[INSERT]](p0)
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY]](p0)
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY1]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ZEXT]], [[C]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[PTRTOINT]], [[C1]]
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[SHL]]
+ ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[OR]](s64)
+ ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[INTTOPTR]](p0)
%0:_(p0) = COPY $vgpr0_vgpr1
%1:_(s32) = COPY $vgpr2
%2:_(p0) = G_INSERT %0, %1, 32
@@ -320,8 +508,17 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $vgpr4_vgpr5
- ; CHECK-NEXT: [[INSERT:%[0-9]+]]:_(s128) = G_INSERT [[COPY]], [[COPY1]](p0), 0
- ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[INSERT]](s128)
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY1]](p0)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[UV]], [[C]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[UV1]], [[C1]]
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[PTRTOINT]]
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[C]]
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[OR1]](s64)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s128) = COPY [[MV]](s128)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[COPY2]](s128)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(p0) = COPY $vgpr4_vgpr5
%2:_(s128) = G_INSERT %0, %1, 0
@@ -338,8 +535,23 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $vgpr4_vgpr5
- ; CHECK-NEXT: [[INSERT:%[0-9]+]]:_(s128) = G_INSERT [[COPY]], [[COPY1]](p0), 32
- ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[INSERT]](s128)
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY1]](p0)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[PTRTOINT]], [[C1]](s32)
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[C]], [[C1]](s32)
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[PTRTOINT]], [[C1]](s32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4294967296
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[UV]], [[C2]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[UV1]], [[C3]]
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND]], [[SHL]]
+ ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[OR]]
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR1]](s64), [[OR2]](s64)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s128) = COPY [[MV]](s128)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[COPY2]](s128)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(p0) = COPY $vgpr4_vgpr5
%2:_(s128) = G_INSERT %0, %1, 32
@@ -356,8 +568,17 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $vgpr4_vgpr5
- ; CHECK-NEXT: [[INSERT:%[0-9]+]]:_(s128) = G_INSERT [[COPY]], [[COPY1]](p0), 64
- ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[INSERT]](s128)
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY1]](p0)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[UV]], [[C1]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[UV1]], [[C]]
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[C]]
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[PTRTOINT]]
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[OR1]](s64)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s128) = COPY [[MV]](s128)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[COPY2]](s128)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(p0) = COPY $vgpr4_vgpr5
%2:_(s128) = G_INSERT %0, %1, 64
@@ -375,9 +596,23 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; CHECK-NEXT: [[INSERT:%[0-9]+]]:_(s128) = G_INSERT [[COPY]], [[TRUNC]](s16), 0
- ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[INSERT]](s128)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY1]](s32), [[DEF]](s32)
+ ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[MV]], [[C]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF1]], [[C1]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -65536
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[UV]], [[C2]]
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[UV1]], [[C3]]
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND2]], [[AND]]
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND3]], [[AND1]]
+ ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[OR1]](s64)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s128) = COPY [[MV1]](s128)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[COPY2]](s128)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s32) = COPY $vgpr4
%2:_(s16) = G_TRUNC %1
@@ -396,9 +631,29 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; CHECK-NEXT: [[INSERT:%[0-9]+]]:_(s128) = G_INSERT [[COPY]], [[TRUNC]](s16), 16
- ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[INSERT]](s128)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY1]](s32), [[DEF]](s32)
+ ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[MV]], [[C]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF1]], [[C1]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[AND]], [[C2]](s32)
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[AND1]], [[C2]](s32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 48
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND]], [[C3]](s32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]]
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4294901761
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[UV]], [[C4]]
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[UV1]], [[C5]]
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND2]], [[SHL]]
+ ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[AND3]], [[OR]]
+ ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR1]](s64), [[OR2]](s64)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s128) = COPY [[MV1]](s128)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[COPY2]](s128)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s32) = COPY $vgpr4
%2:_(s16) = G_TRUNC %1
@@ -417,9 +672,28 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; CHECK-NEXT: [[INSERT:%[0-9]+]]:_(s128) = G_INSERT [[COPY]], [[TRUNC]](s16), 32
- ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[INSERT]](s128)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY1]](s32), [[DEF]](s32)
+ ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[MV]], [[C]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF1]], [[C1]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[AND]], [[C2]](s32)
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[AND1]], [[C2]](s32)
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND]], [[C2]](s32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]]
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -281470681743361
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[UV]], [[C3]]
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[UV1]], [[C4]]
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND2]], [[SHL]]
+ ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[AND3]], [[OR]]
+ ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR1]](s64), [[OR2]](s64)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s128) = COPY [[MV1]](s128)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[COPY2]](s128)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s32) = COPY $vgpr4
%2:_(s16) = G_TRUNC %1
@@ -438,9 +712,23 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; CHECK-NEXT: [[INSERT:%[0-9]+]]:_(s128) = G_INSERT [[COPY]], [[TRUNC]](s16), 112
- ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[INSERT]](s128)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY1]](s32), [[DEF]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[MV]], [[C]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 48
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[AND]], [[C2]](s32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 281474976710655
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[UV]], [[C3]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[UV1]], [[C4]]
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[C1]]
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND2]], [[SHL]]
+ ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[OR1]](s64)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s128) = COPY [[MV1]](s128)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[COPY2]](s128)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s32) = COPY $vgpr4
%2:_(s16) = G_TRUNC %1
@@ -1539,9 +1827,14 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; CHECK-NEXT: [[INSERT:%[0-9]+]]:_(s64) = G_INSERT [[COPY]], [[TRUNC]](s16), 0
- ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[INSERT]](s64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY1]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -65536
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]]
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[AND]]
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY [[OR]](s64)
+ ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[COPY2]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = COPY $vgpr2
%2:_(s16) = G_TRUNC %1
@@ -1559,9 +1852,16 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; CHECK-NEXT: [[INSERT:%[0-9]+]]:_(s64) = G_INSERT [[COPY]], [[TRUNC]](s16), 16
- ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[INSERT]](s64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY1]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[AND]], [[C1]](s32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4294901761
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C2]]
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[SHL]]
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY [[OR]](s64)
+ ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[COPY2]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = COPY $vgpr2
%2:_(s16) = G_TRUNC %1
@@ -1579,9 +1879,16 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; CHECK-NEXT: [[INSERT:%[0-9]+]]:_(s64) = G_INSERT [[COPY]], [[TRUNC]](s16), 32
- ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[INSERT]](s64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY1]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[AND]], [[C1]](s32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -281470681743361
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C2]]
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[SHL]]
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY [[OR]](s64)
+ ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[COPY2]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = COPY $vgpr2
%2:_(s16) = G_TRUNC %1
@@ -1599,9 +1906,16 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; CHECK-NEXT: [[INSERT:%[0-9]+]]:_(s64) = G_INSERT [[COPY]], [[TRUNC]](s16), 48
- ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[INSERT]](s64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY1]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 48
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[AND]], [[C1]](s32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 281474976710655
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C2]]
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[SHL]]
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY [[OR]](s64)
+ ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[COPY2]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = COPY $vgpr2
%2:_(s16) = G_TRUNC %1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
index a5a76bb18e557..84ff95404f365 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
@@ -1365,9 +1365,26 @@ body: |
; CI-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD1]](<3 x s32>)
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<7 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32), [[UV4]](s32), [[UV5]](s32), [[UV6]](s32)
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(s224) = G_BITCAST [[BUILD_VECTOR]](<7 x s32>)
- ; CI-NEXT: [[DEF:%[0-9]+]]:_(s256) = G_IMPLICIT_DEF
- ; CI-NEXT: [[INSERT:%[0-9]+]]:_(s256) = G_INSERT [[DEF]], [[BITCAST]](s224), 0
- ; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[INSERT]](s256)
+ ; CI-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+ ; CI-NEXT: [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BITCAST]](s224)
+ ; CI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CI-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV7]](s32), [[UV8]](s32)
+ ; CI-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV9]](s32), [[UV10]](s32)
+ ; CI-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV11]](s32), [[UV12]](s32)
+ ; CI-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV13]](s32), [[C1]](s32)
+ ; CI-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CI-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4294967296
+ ; CI-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
+ ; CI-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
+ ; CI-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
+ ; CI-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C3]]
+ ; CI-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[MV]]
+ ; CI-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[MV1]]
+ ; CI-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[AND2]], [[MV2]]
+ ; CI-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[AND3]], [[MV3]]
+ ; CI-NEXT: [[MV4:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[OR]](s64), [[OR1]](s64), [[OR2]](s64), [[OR3]](s64)
+ ; CI-NEXT: [[COPY1:%[0-9]+]]:_(s256) = COPY [[MV4]](s256)
+ ; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[COPY1]](s256)
;
; VI-LABEL: name: test_load_constant_s224_align4
; VI: liveins: $vgpr0_vgpr1
@@ -1381,9 +1398,26 @@ body: |
; VI-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD1]](<3 x s32>)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<7 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32), [[UV4]](s32), [[UV5]](s32), [[UV6]](s32)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(s224) = G_BITCAST [[BUILD_VECTOR]](<7 x s32>)
- ; VI-NEXT: [[DEF:%[0-9]+]]:_(s256) = G_IMPLICIT_DEF
- ; VI-NEXT: [[INSERT:%[0-9]+]]:_(s256) = G_INSERT [[DEF]], [[BITCAST]](s224), 0
- ; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[INSERT]](s256)
+ ; VI-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+ ; VI-NEXT: [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BITCAST]](s224)
+ ; VI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; VI-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV7]](s32), [[UV8]](s32)
+ ; VI-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV9]](s32), [[UV10]](s32)
+ ; VI-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV11]](s32), [[UV12]](s32)
+ ; VI-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV13]](s32), [[C1]](s32)
+ ; VI-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; VI-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4294967296
+ ; VI-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
+ ; VI-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
+ ; VI-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
+ ; VI-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C3]]
+ ; VI-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[MV]]
+ ; VI-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[MV1]]
+ ; VI-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[AND2]], [[MV2]]
+ ; VI-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[AND3]], [[MV3]]
+ ; VI-NEXT: [[MV4:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[OR]](s64), [[OR1]](s64), [[OR2]](s64), [[OR3]](s64)
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(s256) = COPY [[MV4]](s256)
+ ; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[COPY1]](s256)
;
; GFX9-LABEL: name: test_load_constant_s224_align4
; GFX9: liveins: $vgpr0_vgpr1
@@ -1397,9 +1431,26 @@ body: |
; GFX9-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD1]](<3 x s32>)
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<7 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32), [[UV4]](s32), [[UV5]](s32), [[UV6]](s32)
; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(s224) = G_BITCAST [[BUILD_VECTOR]](<7 x s32>)
- ; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s256) = G_IMPLICIT_DEF
- ; GFX9-NEXT: [[INSERT:%[0-9]+]]:_(s256) = G_INSERT [[DEF]], [[BITCAST]](s224), 0
- ; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[INSERT]](s256)
+ ; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+ ; GFX9-NEXT: [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BITCAST]](s224)
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; GFX9-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV7]](s32), [[UV8]](s32)
+ ; GFX9-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV9]](s32), [[UV10]](s32)
+ ; GFX9-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV11]](s32), [[UV12]](s32)
+ ; GFX9-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV13]](s32), [[C1]](s32)
+ ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4294967296
+ ; GFX9-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
+ ; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
+ ; GFX9-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
+ ; GFX9-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C3]]
+ ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[MV]]
+ ; GFX9-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[MV1]]
+ ; GFX9-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[AND2]], [[MV2]]
+ ; GFX9-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[AND3]], [[MV3]]
+ ; GFX9-NEXT: [[MV4:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[OR]](s64), [[OR1]](s64), [[OR2]](s64), [[OR3]](s64)
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s256) = COPY [[MV4]](s256)
+ ; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[COPY1]](s256)
%0:_(p4) = COPY $vgpr0_vgpr1
%1:_(s224) = G_LOAD %0 :: (load (s224), align 4, addrspace 4)
%2:_(s256) = G_IMPLICIT_DEF
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
index f1c9a77987f30..e06ea9e97babb 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
@@ -2410,9 +2410,26 @@ body: |
; CI-NEXT: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p0) :: (load (s32) from unknown-address + 24)
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<7 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32), [[LOAD4]](s32), [[LOAD5]](s32), [[LOAD6]](s32)
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(s224) = G_BITCAST [[BUILD_VECTOR]](<7 x s32>)
- ; CI-NEXT: [[DEF:%[0-9]+]]:_(s256) = G_IMPLICIT_DEF
- ; CI-NEXT: [[INSERT:%[0-9]+]]:_(s256) = G_INSERT [[DEF]], [[BITCAST]](s224), 0
- ; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[INSERT]](s256)
+ ; CI-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+ ; CI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BITCAST]](s224)
+ ; CI-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CI-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
+ ; CI-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV2]](s32), [[UV3]](s32)
+ ; CI-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV4]](s32), [[UV5]](s32)
+ ; CI-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV6]](s32), [[C6]](s32)
+ ; CI-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CI-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4294967296
+ ; CI-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C7]]
+ ; CI-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C7]]
+ ; CI-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C7]]
+ ; CI-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C8]]
+ ; CI-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[MV]]
+ ; CI-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[MV1]]
+ ; CI-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[AND2]], [[MV2]]
+ ; CI-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[AND3]], [[MV3]]
+ ; CI-NEXT: [[MV4:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[OR]](s64), [[OR1]](s64), [[OR2]](s64), [[OR3]](s64)
+ ; CI-NEXT: [[COPY1:%[0-9]+]]:_(s256) = COPY [[MV4]](s256)
+ ; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[COPY1]](s256)
;
; VI-LABEL: name: test_load_flat_s224_align4
; VI: liveins: $vgpr0_vgpr1
@@ -2439,9 +2456,26 @@ body: |
; VI-NEXT: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p0) :: (load (s32) from unknown-address + 24)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<7 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32), [[LOAD4]](s32), [[LOAD5]](s32), [[LOAD6]](s32)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(s224) = G_BITCAST [[BUILD_VECTOR]](<7 x s32>)
- ; VI-NEXT: [[DEF:%[0-9]+]]:_(s256) = G_IMPLICIT_DEF
- ; VI-NEXT: [[INSERT:%[0-9]+]]:_(s256) = G_INSERT [[DEF]], [[BITCAST]](s224), 0
- ; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[INSERT]](s256)
+ ; VI-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+ ; VI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BITCAST]](s224)
+ ; VI-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; VI-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
+ ; VI-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV2]](s32), [[UV3]](s32)
+ ; VI-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV4]](s32), [[UV5]](s32)
+ ; VI-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV6]](s32), [[C6]](s32)
+ ; VI-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; VI-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4294967296
+ ; VI-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C7]]
+ ; VI-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C7]]
+ ; VI-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C7]]
+ ; VI-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C8]]
+ ; VI-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[MV]]
+ ; VI-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[MV1]]
+ ; VI-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[AND2]], [[MV2]]
+ ; VI-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[AND3]], [[MV3]]
+ ; VI-NEXT: [[MV4:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[OR]](s64), [[OR1]](s64), [[OR2]](s64), [[OR3]](s64)
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(s256) = COPY [[MV4]](s256)
+ ; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[COPY1]](s256)
;
; GFX9PLUS-LABEL: name: test_load_flat_s224_align4
; GFX9PLUS: liveins: $vgpr0_vgpr1
@@ -2455,9 +2489,26 @@ body: |
; GFX9PLUS-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD1]](<3 x s32>)
; GFX9PLUS-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<7 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32), [[UV4]](s32), [[UV5]](s32), [[UV6]](s32)
; GFX9PLUS-NEXT: [[BITCAST:%[0-9]+]]:_(s224) = G_BITCAST [[BUILD_VECTOR]](<7 x s32>)
- ; GFX9PLUS-NEXT: [[DEF:%[0-9]+]]:_(s256) = G_IMPLICIT_DEF
- ; GFX9PLUS-NEXT: [[INSERT:%[0-9]+]]:_(s256) = G_INSERT [[DEF]], [[BITCAST]](s224), 0
- ; GFX9PLUS-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[INSERT]](s256)
+ ; GFX9PLUS-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+ ; GFX9PLUS-NEXT: [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BITCAST]](s224)
+ ; GFX9PLUS-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; GFX9PLUS-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV7]](s32), [[UV8]](s32)
+ ; GFX9PLUS-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV9]](s32), [[UV10]](s32)
+ ; GFX9PLUS-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV11]](s32), [[UV12]](s32)
+ ; GFX9PLUS-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV13]](s32), [[C1]](s32)
+ ; GFX9PLUS-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; GFX9PLUS-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4294967296
+ ; GFX9PLUS-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
+ ; GFX9PLUS-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
+ ; GFX9PLUS-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
+ ; GFX9PLUS-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C3]]
+ ; GFX9PLUS-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[MV]]
+ ; GFX9PLUS-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[MV1]]
+ ; GFX9PLUS-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[AND2]], [[MV2]]
+ ; GFX9PLUS-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[AND3]], [[MV3]]
+ ; GFX9PLUS-NEXT: [[MV4:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[OR]](s64), [[OR1]](s64), [[OR2]](s64), [[OR3]](s64)
+ ; GFX9PLUS-NEXT: [[COPY1:%[0-9]+]]:_(s256) = COPY [[MV4]](s256)
+ ; GFX9PLUS-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[COPY1]](s256)
;
; GFX11PLUS-LABEL: name: test_load_flat_s224_align4
; GFX11PLUS: liveins: $vgpr0_vgpr1
@@ -2471,9 +2522,26 @@ body: |
; GFX11PLUS-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD1]](<3 x s32>)
; GFX11PLUS-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<7 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32), [[UV4]](s32), [[UV5]](s32), [[UV6]](s32)
; GFX11PLUS-NEXT: [[BITCAST:%[0-9]+]]:_(s224) = G_BITCAST [[BUILD_VECTOR]](<7 x s32>)
- ; GFX11PLUS-NEXT: [[DEF:%[0-9]+]]:_(s256) = G_IMPLICIT_DEF
- ; GFX11PLUS-NEXT: [[INSERT:%[0-9]+]]:_(s256) = G_INSERT [[DEF]], [[BITCAST]](s224), 0
- ; GFX11PLUS-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[INSERT]](s256)
+ ; GFX11PLUS-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+ ; GFX11PLUS-NEXT: [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BITCAST]](s224)
+ ; GFX11PLUS-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; GFX11PLUS-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV7]](s32), [[UV8]](s32)
+ ; GFX11PLUS-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV9]](s32), [[UV10]](s32)
+ ; GFX11PLUS-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV11]](s32), [[UV12]](s32)
+ ; GFX11PLUS-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV13]](s32), [[C1]](s32)
+ ; GFX11PLUS-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; GFX11PLUS-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4294967296
+ ; GFX11PLUS-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
+ ; GFX11PLUS-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
+ ; GFX11PLUS-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
+ ; GFX11PLUS-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C3]]
+ ; GFX11PLUS-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[MV]]
+ ; GFX11PLUS-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[MV1]]
+ ; GFX11PLUS-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[AND2]], [[MV2]]
+ ; GFX11PLUS-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[AND3]], [[MV3]]
+ ; GFX11PLUS-NEXT: [[MV4:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[OR]](s64), [[OR1]](s64), [[OR2]](s64), [[OR3]](s64)
+ ; GFX11PLUS-NEXT: [[COPY1:%[0-9]+]]:_(s256) = COPY [[MV4]](s256)
+ ; GFX11PLUS-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[COPY1]](s256)
;
; GFX12-LABEL: name: test_load_flat_s224_align4
; GFX12: liveins: $vgpr0_vgpr1
@@ -2487,9 +2555,26 @@ body: |
; GFX12-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD1]](<3 x s32>)
; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<7 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32), [[UV4]](s32), [[UV5]](s32), [[UV6]](s32)
; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(s224) = G_BITCAST [[BUILD_VECTOR]](<7 x s32>)
- ; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s256) = G_IMPLICIT_DEF
- ; GFX12-NEXT: [[INSERT:%[0-9]+]]:_(s256) = G_INSERT [[DEF]], [[BITCAST]](s224), 0
- ; GFX12-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[INSERT]](s256)
+ ; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+ ; GFX12-NEXT: [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BITCAST]](s224)
+ ; GFX12-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; GFX12-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV7]](s32), [[UV8]](s32)
+ ; GFX12-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV9]](s32), [[UV10]](s32)
+ ; GFX12-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV11]](s32), [[UV12]](s32)
+ ; GFX12-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV13]](s32), [[C1]](s32)
+ ; GFX12-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; GFX12-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4294967296
+ ; GFX12-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
+ ; GFX12-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
+ ; GFX12-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
+ ; GFX12-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C3]]
+ ; GFX12-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[MV]]
+ ; GFX12-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[MV1]]
+ ; GFX12-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[AND2]], [[MV2]]
+ ; GFX12-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[AND3]], [[MV3]]
+ ; GFX12-NEXT: [[MV4:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[OR]](s64), [[OR1]](s64), [[OR2]](s64), [[OR3]](s64)
+ ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(s256) = COPY [[MV4]](s256)
+ ; GFX12-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[COPY1]](s256)
;
; UNALIGNED_GFX9PLUS-LABEL: name: test_load_flat_s224_align4
; UNALIGNED_GFX9PLUS: liveins: $vgpr0_vgpr1
@@ -2503,9 +2588,26 @@ body: |
; UNALIGNED_GFX9PLUS-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD1]](<3 x s32>)
; UNALIGNED_GFX9PLUS-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<7 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32), [[UV4]](s32), [[UV5]](s32), [[UV6]](s32)
; UNALIGNED_GFX9PLUS-NEXT: [[BITCAST:%[0-9]+]]:_(s224) = G_BITCAST [[BUILD_VECTOR]](<7 x s32>)
- ; UNALIGNED_GFX9PLUS-NEXT: [[DEF:%[0-9]+]]:_(s256) = G_IMPLICIT_DEF
- ; UNALIGNED_GFX9PLUS-NEXT: [[INSERT:%[0-9]+]]:_(s256) = G_INSERT [[DEF]], [[BITCAST]](s224), 0
- ; UNALIGNED_GFX9PLUS-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[INSERT]](s256)
+ ; UNALIGNED_GFX9PLUS-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+ ; UNALIGNED_GFX9PLUS-NEXT: [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BITCAST]](s224)
+ ; UNALIGNED_GFX9PLUS-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; UNALIGNED_GFX9PLUS-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV7]](s32), [[UV8]](s32)
+ ; UNALIGNED_GFX9PLUS-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV9]](s32), [[UV10]](s32)
+ ; UNALIGNED_GFX9PLUS-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV11]](s32), [[UV12]](s32)
+ ; UNALIGNED_GFX9PLUS-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV13]](s32), [[C1]](s32)
+ ; UNALIGNED_GFX9PLUS-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; UNALIGNED_GFX9PLUS-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4294967296
+ ; UNALIGNED_GFX9PLUS-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
+ ; UNALIGNED_GFX9PLUS-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
+ ; UNALIGNED_GFX9PLUS-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
+ ; UNALIGNED_GFX9PLUS-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C3]]
+ ; UNALIGNED_GFX9PLUS-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[MV]]
+ ; UNALIGNED_GFX9PLUS-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[MV1]]
+ ; UNALIGNED_GFX9PLUS-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[AND2]], [[MV2]]
+ ; UNALIGNED_GFX9PLUS-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[AND3]], [[MV3]]
+ ; UNALIGNED_GFX9PLUS-NEXT: [[MV4:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[OR]](s64), [[OR1]](s64), [[OR2]](s64), [[OR3]](s64)
+ ; UNALIGNED_GFX9PLUS-NEXT: [[COPY1:%[0-9]+]]:_(s256) = COPY [[MV4]](s256)
+ ; UNALIGNED_GFX9PLUS-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[COPY1]](s256)
;
; UNALIGNED_GFX11PLUS-LABEL: name: test_load_flat_s224_align4
; UNALIGNED_GFX11PLUS: liveins: $vgpr0_vgpr1
@@ -2519,9 +2621,26 @@ body: |
; UNALIGNED_GFX11PLUS-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD1]](<3 x s32>)
; UNALIGNED_GFX11PLUS-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<7 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32), [[UV4]](s32), [[UV5]](s32), [[UV6]](s32)
; UNALIGNED_GFX11PLUS-NEXT: [[BITCAST:%[0-9]+]]:_(s224) = G_BITCAST [[BUILD_VECTOR]](<7 x s32>)
- ; UNALIGNED_GFX11PLUS-NEXT: [[DEF:%[0-9]+]]:_(s256) = G_IMPLICIT_DEF
- ; UNALIGNED_GFX11PLUS-NEXT: [[INSERT:%[0-9]+]]:_(s256) = G_INSERT [[DEF]], [[BITCAST]](s224), 0
- ; UNALIGNED_GFX11PLUS-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[INSERT]](s256)
+ ; UNALIGNED_GFX11PLUS-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+ ; UNALIGNED_GFX11PLUS-NEXT: [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BITCAST]](s224)
+ ; UNALIGNED_GFX11PLUS-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; UNALIGNED_GFX11PLUS-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV7]](s32), [[UV8]](s32)
+ ; UNALIGNED_GFX11PLUS-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV9]](s32), [[UV10]](s32)
+ ; UNALIGNED_GFX11PLUS-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV11]](s32), [[UV12]](s32)
+ ; UNALIGNED_GFX11PLUS-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV13]](s32), [[C1]](s32)
+ ; UNALIGNED_GFX11PLUS-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; UNALIGNED_GFX11PLUS-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4294967296
+ ; UNALIGNED_GFX11PLUS-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
+ ; UNALIGNED_GFX11PLUS-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
+ ; UNALIGNED_GFX11PLUS-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
+ ; UNALIGNED_GFX11PLUS-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C3]]
+ ; UNALIGNED_GFX11PLUS-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[MV]]
+ ; UNALIGNED_GFX11PLUS-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[MV1]]
+ ; UNALIGNED_GFX11PLUS-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[AND2]], [[MV2]]
+ ; UNALIGNED_GFX11PLUS-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[AND3]], [[MV3]]
+ ; UNALIGNED_GFX11PLUS-NEXT: [[MV4:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[OR]](s64), [[OR1]](s64), [[OR2]](s64), [[OR3]](s64)
+ ; UNALIGNED_GFX11PLUS-NEXT: [[COPY1:%[0-9]+]]:_(s256) = COPY [[MV4]](s256)
+ ; UNALIGNED_GFX11PLUS-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[COPY1]](s256)
;
; UNALIGNED_GFX12-LABEL: name: test_load_flat_s224_align4
; UNALIGNED_GFX12: liveins: $vgpr0_vgpr1
@@ -2535,9 +2654,26 @@ body: |
; UNALIGNED_GFX12-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD1]](<3 x s32>)
; UNALIGNED_GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<7 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32), [[UV4]](s32), [[UV5]](s32), [[UV6]](s32)
; UNALIGNED_GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(s224) = G_BITCAST [[BUILD_VECTOR]](<7 x s32>)
- ; UNALIGNED_GFX12-NEXT: [[DEF:%[0-9]+]]:_(s256) = G_IMPLICIT_DEF
- ; UNALIGNED_GFX12-NEXT: [[INSERT:%[0-9]+]]:_(s256) = G_INSERT [[DEF]], [[BITCAST]](s224), 0
- ; UNALIGNED_GFX12-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[INSERT]](s256)
+ ; UNALIGNED_GFX12-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+ ; UNALIGNED_GFX12-NEXT: [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BITCAST]](s224)
+ ; UNALIGNED_GFX12-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; UNALIGNED_GFX12-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV7]](s32), [[UV8]](s32)
+ ; UNALIGNED_GFX12-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV9]](s32), [[UV10]](s32)
+ ; UNALIGNED_GFX12-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV11]](s32), [[UV12]](s32)
+ ; UNALIGNED_GFX12-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV13]](s32), [[C1]](s32)
+ ; UNALIGNED_GFX12-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; UNALIGNED_GFX12-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4294967296
+ ; UNALIGNED_GFX12-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
+ ; UNALIGNED_GFX12-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
+ ; UNALIGNED_GFX12-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
+ ; UNALIGNED_GFX12-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C3]]
+ ; UNALIGNED_GFX12-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[MV]]
+ ; UNALIGNED_GFX12-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[MV1]]
+ ; UNALIGNED_GFX12-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[AND2]], [[MV2]]
+ ; UNALIGNED_GFX12-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[AND3]], [[MV3]]
+ ; UNALIGNED_GFX12-NEXT: [[MV4:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[OR]](s64), [[OR1]](s64), [[OR2]](s64), [[OR3]](s64)
+ ; UNALIGNED_GFX12-NEXT: [[COPY1:%[0-9]+]]:_(s256) = COPY [[MV4]](s256)
+ ; UNALIGNED_GFX12-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[COPY1]](s256)
%0:_(p0) = COPY $vgpr0_vgpr1
%1:_(s224) = G_LOAD %0 :: (load (s224), align 4, addrspace 0)
%2:_(s256) = G_IMPLICIT_DEF
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
index a15c602e94878..0de6656756d2a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
@@ -2170,9 +2170,26 @@ body: |
; SI-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](<4 x s32>)
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<7 x s32>) = G_BUILD_VECTOR [[UV2]](s32), [[UV3]](s32), [[UV4]](s32), [[UV5]](s32), [[UV]](s32), [[UV1]](s32), [[LOAD2]](s32)
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(s224) = G_BITCAST [[BUILD_VECTOR]](<7 x s32>)
- ; SI-NEXT: [[DEF:%[0-9]+]]:_(s256) = G_IMPLICIT_DEF
- ; SI-NEXT: [[INSERT:%[0-9]+]]:_(s256) = G_INSERT [[DEF]], [[BITCAST]](s224), 0
- ; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[INSERT]](s256)
+ ; SI-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+ ; SI-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BITCAST]](s224)
+ ; SI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; SI-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV6]](s32), [[UV7]](s32)
+ ; SI-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV8]](s32), [[UV9]](s32)
+ ; SI-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV10]](s32), [[UV11]](s32)
+ ; SI-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV12]](s32), [[C2]](s32)
+ ; SI-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; SI-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4294967296
+ ; SI-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C3]]
+ ; SI-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C3]]
+ ; SI-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C3]]
+ ; SI-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C4]]
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[MV]]
+ ; SI-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[MV1]]
+ ; SI-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[AND2]], [[MV2]]
+ ; SI-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[AND3]], [[MV3]]
+ ; SI-NEXT: [[MV4:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[OR]](s64), [[OR1]](s64), [[OR2]](s64), [[OR3]](s64)
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(s256) = COPY [[MV4]](s256)
+ ; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[COPY1]](s256)
;
; CI-HSA-LABEL: name: test_load_global_s224_align4
; CI-HSA: liveins: $vgpr0_vgpr1
@@ -2186,9 +2203,26 @@ body: |
; CI-HSA-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD1]](<3 x s32>)
; CI-HSA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<7 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32), [[UV4]](s32), [[UV5]](s32), [[UV6]](s32)
; CI-HSA-NEXT: [[BITCAST:%[0-9]+]]:_(s224) = G_BITCAST [[BUILD_VECTOR]](<7 x s32>)
- ; CI-HSA-NEXT: [[DEF:%[0-9]+]]:_(s256) = G_IMPLICIT_DEF
- ; CI-HSA-NEXT: [[INSERT:%[0-9]+]]:_(s256) = G_INSERT [[DEF]], [[BITCAST]](s224), 0
- ; CI-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[INSERT]](s256)
+ ; CI-HSA-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+ ; CI-HSA-NEXT: [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BITCAST]](s224)
+ ; CI-HSA-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CI-HSA-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV7]](s32), [[UV8]](s32)
+ ; CI-HSA-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV9]](s32), [[UV10]](s32)
+ ; CI-HSA-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV11]](s32), [[UV12]](s32)
+ ; CI-HSA-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV13]](s32), [[C1]](s32)
+ ; CI-HSA-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CI-HSA-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4294967296
+ ; CI-HSA-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
+ ; CI-HSA-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
+ ; CI-HSA-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
+ ; CI-HSA-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C3]]
+ ; CI-HSA-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[MV]]
+ ; CI-HSA-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[MV1]]
+ ; CI-HSA-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[AND2]], [[MV2]]
+ ; CI-HSA-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[AND3]], [[MV3]]
+ ; CI-HSA-NEXT: [[MV4:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[OR]](s64), [[OR1]](s64), [[OR2]](s64), [[OR3]](s64)
+ ; CI-HSA-NEXT: [[COPY1:%[0-9]+]]:_(s256) = COPY [[MV4]](s256)
+ ; CI-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[COPY1]](s256)
;
; CI-MESA-LABEL: name: test_load_global_s224_align4
; CI-MESA: liveins: $vgpr0_vgpr1
@@ -2202,9 +2236,26 @@ body: |
; CI-MESA-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD1]](<3 x s32>)
; CI-MESA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<7 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32), [[UV4]](s32), [[UV5]](s32), [[UV6]](s32)
; CI-MESA-NEXT: [[BITCAST:%[0-9]+]]:_(s224) = G_BITCAST [[BUILD_VECTOR]](<7 x s32>)
- ; CI-MESA-NEXT: [[DEF:%[0-9]+]]:_(s256) = G_IMPLICIT_DEF
- ; CI-MESA-NEXT: [[INSERT:%[0-9]+]]:_(s256) = G_INSERT [[DEF]], [[BITCAST]](s224), 0
- ; CI-MESA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[INSERT]](s256)
+ ; CI-MESA-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+ ; CI-MESA-NEXT: [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BITCAST]](s224)
+ ; CI-MESA-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CI-MESA-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV7]](s32), [[UV8]](s32)
+ ; CI-MESA-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV9]](s32), [[UV10]](s32)
+ ; CI-MESA-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV11]](s32), [[UV12]](s32)
+ ; CI-MESA-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV13]](s32), [[C1]](s32)
+ ; CI-MESA-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CI-MESA-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4294967296
+ ; CI-MESA-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
+ ; CI-MESA-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
+ ; CI-MESA-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
+ ; CI-MESA-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C3]]
+ ; CI-MESA-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[MV]]
+ ; CI-MESA-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[MV1]]
+ ; CI-MESA-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[AND2]], [[MV2]]
+ ; CI-MESA-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[AND3]], [[MV3]]
+ ; CI-MESA-NEXT: [[MV4:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[OR]](s64), [[OR1]](s64), [[OR2]](s64), [[OR3]](s64)
+ ; CI-MESA-NEXT: [[COPY1:%[0-9]+]]:_(s256) = COPY [[MV4]](s256)
+ ; CI-MESA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[COPY1]](s256)
;
; VI-LABEL: name: test_load_global_s224_align4
; VI: liveins: $vgpr0_vgpr1
@@ -2218,9 +2269,26 @@ body: |
; VI-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD1]](<3 x s32>)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<7 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32), [[UV4]](s32), [[UV5]](s32), [[UV6]](s32)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(s224) = G_BITCAST [[BUILD_VECTOR]](<7 x s32>)
- ; VI-NEXT: [[DEF:%[0-9]+]]:_(s256) = G_IMPLICIT_DEF
- ; VI-NEXT: [[INSERT:%[0-9]+]]:_(s256) = G_INSERT [[DEF]], [[BITCAST]](s224), 0
- ; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[INSERT]](s256)
+ ; VI-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+ ; VI-NEXT: [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BITCAST]](s224)
+ ; VI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; VI-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV7]](s32), [[UV8]](s32)
+ ; VI-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV9]](s32), [[UV10]](s32)
+ ; VI-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV11]](s32), [[UV12]](s32)
+ ; VI-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV13]](s32), [[C1]](s32)
+ ; VI-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; VI-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4294967296
+ ; VI-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
+ ; VI-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
+ ; VI-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
+ ; VI-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C3]]
+ ; VI-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[MV]]
+ ; VI-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[MV1]]
+ ; VI-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[AND2]], [[MV2]]
+ ; VI-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[AND3]], [[MV3]]
+ ; VI-NEXT: [[MV4:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[OR]](s64), [[OR1]](s64), [[OR2]](s64), [[OR3]](s64)
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(s256) = COPY [[MV4]](s256)
+ ; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[COPY1]](s256)
;
; GFX9-HSA-LABEL: name: test_load_global_s224_align4
; GFX9-HSA: liveins: $vgpr0_vgpr1
@@ -2234,9 +2302,26 @@ body: |
; GFX9-HSA-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD1]](<3 x s32>)
; GFX9-HSA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<7 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32), [[UV4]](s32), [[UV5]](s32), [[UV6]](s32)
; GFX9-HSA-NEXT: [[BITCAST:%[0-9]+]]:_(s224) = G_BITCAST [[BUILD_VECTOR]](<7 x s32>)
- ; GFX9-HSA-NEXT: [[DEF:%[0-9]+]]:_(s256) = G_IMPLICIT_DEF
- ; GFX9-HSA-NEXT: [[INSERT:%[0-9]+]]:_(s256) = G_INSERT [[DEF]], [[BITCAST]](s224), 0
- ; GFX9-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[INSERT]](s256)
+ ; GFX9-HSA-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+ ; GFX9-HSA-NEXT: [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BITCAST]](s224)
+ ; GFX9-HSA-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; GFX9-HSA-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV7]](s32), [[UV8]](s32)
+ ; GFX9-HSA-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV9]](s32), [[UV10]](s32)
+ ; GFX9-HSA-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV11]](s32), [[UV12]](s32)
+ ; GFX9-HSA-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV13]](s32), [[C1]](s32)
+ ; GFX9-HSA-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; GFX9-HSA-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4294967296
+ ; GFX9-HSA-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
+ ; GFX9-HSA-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
+ ; GFX9-HSA-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
+ ; GFX9-HSA-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C3]]
+ ; GFX9-HSA-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[MV]]
+ ; GFX9-HSA-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[MV1]]
+ ; GFX9-HSA-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[AND2]], [[MV2]]
+ ; GFX9-HSA-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[AND3]], [[MV3]]
+ ; GFX9-HSA-NEXT: [[MV4:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[OR]](s64), [[OR1]](s64), [[OR2]](s64), [[OR3]](s64)
+ ; GFX9-HSA-NEXT: [[COPY1:%[0-9]+]]:_(s256) = COPY [[MV4]](s256)
+ ; GFX9-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[COPY1]](s256)
;
; GFX9-MESA-LABEL: name: test_load_global_s224_align4
; GFX9-MESA: liveins: $vgpr0_vgpr1
@@ -2250,9 +2335,26 @@ body: |
; GFX9-MESA-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD1]](<3 x s32>)
; GFX9-MESA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<7 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32), [[UV4]](s32), [[UV5]](s32), [[UV6]](s32)
; GFX9-MESA-NEXT: [[BITCAST:%[0-9]+]]:_(s224) = G_BITCAST [[BUILD_VECTOR]](<7 x s32>)
- ; GFX9-MESA-NEXT: [[DEF:%[0-9]+]]:_(s256) = G_IMPLICIT_DEF
- ; GFX9-MESA-NEXT: [[INSERT:%[0-9]+]]:_(s256) = G_INSERT [[DEF]], [[BITCAST]](s224), 0
- ; GFX9-MESA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[INSERT]](s256)
+ ; GFX9-MESA-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+ ; GFX9-MESA-NEXT: [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BITCAST]](s224)
+ ; GFX9-MESA-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; GFX9-MESA-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV7]](s32), [[UV8]](s32)
+ ; GFX9-MESA-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV9]](s32), [[UV10]](s32)
+ ; GFX9-MESA-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV11]](s32), [[UV12]](s32)
+ ; GFX9-MESA-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV13]](s32), [[C1]](s32)
+ ; GFX9-MESA-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; GFX9-MESA-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4294967296
+ ; GFX9-MESA-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
+ ; GFX9-MESA-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
+ ; GFX9-MESA-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
+ ; GFX9-MESA-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C3]]
+ ; GFX9-MESA-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[MV]]
+ ; GFX9-MESA-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[MV1]]
+ ; GFX9-MESA-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[AND2]], [[MV2]]
+ ; GFX9-MESA-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[AND3]], [[MV3]]
+ ; GFX9-MESA-NEXT: [[MV4:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[OR]](s64), [[OR1]](s64), [[OR2]](s64), [[OR3]](s64)
+ ; GFX9-MESA-NEXT: [[COPY1:%[0-9]+]]:_(s256) = COPY [[MV4]](s256)
+ ; GFX9-MESA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[COPY1]](s256)
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s224) = G_LOAD %0 :: (load (s224), align 4, addrspace 1)
%2:_(s256) = G_IMPLICIT_DEF
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
index c446f5537bbf1..bef6e69de07bd 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
@@ -151,13 +151,11 @@ body: |
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96)
; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
; CHECK-NEXT: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
; CHECK-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s96)
; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV6]](s32), [[UV7]](s32)
; CHECK-NEXT: [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s96)
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV11]](s32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[MV]], [[MV1]]
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[COPY2]], [[COPY3]]
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[UV5]], [[UV11]]
; CHECK-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[OR]](s64)
; CHECK-NEXT: [[MV2:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[UV12]](s32), [[UV13]](s32), [[OR1]](s32)
; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[MV2]](s96)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir
index 9708910f23f85..eace05a17adc7 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir
@@ -180,13 +180,11 @@ body: |
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96)
; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
; CHECK-NEXT: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96)
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
; CHECK-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s96)
; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV6]](s32), [[UV7]](s32)
; CHECK-NEXT: [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s96)
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV11]](s32)
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[MV]], [[MV1]]
- ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[COPY3]], [[COPY4]]
+ ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[UV5]], [[UV11]]
; CHECK-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SELECT]](s64)
; CHECK-NEXT: [[MV2:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[UV12]](s32), [[UV13]](s32), [[SELECT1]](s32)
; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[MV2]](s96)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir
index 9430fd94a40d2..41f32964c55ff 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir
@@ -151,13 +151,11 @@ body: |
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96)
; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
; CHECK-NEXT: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
; CHECK-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s96)
; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV6]](s32), [[UV7]](s32)
; CHECK-NEXT: [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s96)
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV11]](s32)
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[MV]], [[MV1]]
- ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[COPY2]], [[COPY3]]
+ ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[UV5]], [[UV11]]
; CHECK-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64)
; CHECK-NEXT: [[MV2:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[UV12]](s32), [[UV13]](s32), [[XOR1]](s32)
; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[MV2]](s96)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract.mir
deleted file mode 100644
index 85cb851b6bc3d..0000000000000
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract.mir
+++ /dev/null
@@ -1,85 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
-
----
-name: extract_lo32_i64_s
-legalized: true
-
-body: |
- bb.0:
- liveins: $sgpr0_sgpr1
- ; CHECK-LABEL: name: extract_lo32_i64_s
- ; CHECK: liveins: $sgpr0_sgpr1
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:sgpr(s32) = G_EXTRACT [[COPY]](s64), 0
- %0:_(s64) = COPY $sgpr0_sgpr1
- %1:_(s32) = G_EXTRACT %0, 0
-...
-
----
-name: extract_lo32_i64_v
-legalized: true
-
-body: |
- bb.0:
- liveins: $vgpr0_vgpr1
- ; CHECK-LABEL: name: extract_lo32_i64_v
- ; CHECK: liveins: $vgpr0_vgpr1
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:vgpr(s32) = G_EXTRACT [[COPY]](s64), 0
- %0:_(s64) = COPY $vgpr0_vgpr1
- %1:_(s32) = G_EXTRACT %0, 0
-...
-
----
-name: extract_s32_0_s1024_v
-legalized: true
-
-body: |
- bb.0:
- liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
- ; CHECK-LABEL: name: extract_s32_0_s1024_v
- ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s1024) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:vgpr(s32) = G_EXTRACT [[COPY]](s1024), 0
- %0:_(s1024) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
- %1:_(s32) = G_EXTRACT %0, 0
-...
-
----
-name: extract_s32_0_s1024_s
-legalized: true
-
-body: |
- bb.0:
- liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
- ; CHECK-LABEL: name: extract_s32_0_s1024_s
- ; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s1024) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:sgpr(s32) = G_EXTRACT [[COPY]](s1024), 0
- %0:_(s1024) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
- %1:_(s32) = G_EXTRACT %0, 0
-...
-
----
-name: extract_lo32_i64_a
-legalized: true
-
-body: |
- bb.0:
- liveins: $agpr0_agpr1
- ; CHECK-LABEL: name: extract_lo32_i64_a
- ; CHECK: liveins: $agpr0_agpr1
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:agpr(s64) = COPY $agpr0_agpr1
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:agpr(s32) = G_EXTRACT [[COPY]](s64), 0
- ; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](s32)
- %0:_(s64) = COPY $agpr0_agpr1
- %1:_(s32) = G_EXTRACT %0, 0
- S_ENDPGM 0, implicit %1
-...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert.mir
deleted file mode 100644
index 55f6fa8d3e0ed..0000000000000
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert.mir
+++ /dev/null
@@ -1,187 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
-
----
-name: insert_lo32_i64_ss
-legalized: true
-
-body: |
- bb.0:
- liveins: $sgpr0_sgpr1, $sgpr2
- ; CHECK-LABEL: name: insert_lo32_i64_ss
- ; CHECK: liveins: $sgpr0_sgpr1, $sgpr2
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
- ; CHECK-NEXT: [[INSERT:%[0-9]+]]:sgpr(s64) = G_INSERT [[COPY]], [[COPY1]](s32), 0
- %0:_(s64) = COPY $sgpr0_sgpr1
- %1:_(s32) = COPY $sgpr2
- %2:_(s64) = G_INSERT %0, %1, 0
-...
-
----
-name: insert_lo32_i64_sv
-legalized: true
-
-body: |
- bb.0:
- liveins: $sgpr0_sgpr1, $vgpr2
- ; CHECK-LABEL: name: insert_lo32_i64_sv
- ; CHECK: liveins: $sgpr0_sgpr1, $vgpr2
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
- ; CHECK-NEXT: [[INSERT:%[0-9]+]]:vgpr(s64) = G_INSERT [[COPY2]], [[COPY1]](s32), 0
- %0:_(s64) = COPY $sgpr0_sgpr1
- %1:_(s32) = COPY $vgpr2
- %2:_(s64) = G_INSERT %0, %1, 0
-...
----
-name: insert_lo32_i64_vs
-legalized: true
-
-body: |
- bb.0:
- liveins: $vgpr0_vgpr1, $sgpr2
- ; CHECK-LABEL: name: insert_lo32_i64_vs
- ; CHECK: liveins: $vgpr0_vgpr1, $sgpr2
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[INSERT:%[0-9]+]]:vgpr(s64) = G_INSERT [[COPY]], [[COPY2]](s32), 0
- %0:_(s64) = COPY $vgpr0_vgpr1
- %1:_(s32) = COPY $sgpr2
- %2:_(s64) = G_INSERT %0, %1, 0
-...
----
-name: insert_lo32_i64_vv
-legalized: true
-
-body: |
- bb.0:
- liveins: $vgpr0_vgpr1, $vgpr2
- ; CHECK-LABEL: name: insert_lo32_i64_vv
- ; CHECK: liveins: $vgpr0_vgpr1, $vgpr2
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
- ; CHECK-NEXT: [[INSERT:%[0-9]+]]:sgpr(s64) = G_INSERT [[COPY]], [[COPY1]](s32), 0
- %0:_(s64) = COPY $sgpr0_sgpr1
- %1:_(s32) = COPY $sgpr2
- %2:_(s64) = G_INSERT %0, %1, 0
-...
-
----
-name: insert_lo32_i96_v
-legalized: true
-
-body: |
- bb.0:
- liveins: $vgpr0_vgpr1_vgpr2, $vgpr3
- ; CHECK-LABEL: name: insert_lo32_i96_v
- ; CHECK: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s96) = COPY $vgpr0_vgpr1_vgpr2
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr3
- ; CHECK-NEXT: [[INSERT:%[0-9]+]]:vgpr(s96) = G_INSERT [[COPY]], [[COPY1]](s32), 0
- %0:_(s96) = COPY $vgpr0_vgpr1_vgpr2
- %1:_(s32) = COPY $vgpr3
- %2:_(s96) = G_INSERT %0, %1, 0
-...
-
----
-name: insert_lo32_i64_aa
-legalized: true
-
-body: |
- bb.0:
- liveins: $agpr0_agpr1, $agpr2
- ; CHECK-LABEL: name: insert_lo32_i64_aa
- ; CHECK: liveins: $agpr0_agpr1, $agpr2
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:agpr(s64) = COPY $agpr0_agpr1
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:agpr(s32) = COPY $agpr2
- ; CHECK-NEXT: [[INSERT:%[0-9]+]]:agpr(s64) = G_INSERT [[COPY]], [[COPY1]](s32), 0
- %0:_(s64) = COPY $agpr0_agpr1
- %1:_(s32) = COPY $agpr2
- %2:_(s64) = G_INSERT %0, %1, 0
-...
-
----
-name: insert_lo32_i64_av
-legalized: true
-
-body: |
- bb.0:
- liveins: $agpr0_agpr1, $vgpr2
- ; CHECK-LABEL: name: insert_lo32_i64_av
- ; CHECK: liveins: $agpr0_agpr1, $vgpr2
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:agpr(s64) = COPY $agpr0_agpr1
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
- ; CHECK-NEXT: [[INSERT:%[0-9]+]]:vgpr(s64) = G_INSERT [[COPY2]], [[COPY1]](s32), 0
- %0:_(s64) = COPY $agpr0_agpr1
- %1:_(s32) = COPY $vgpr2
- %2:_(s64) = G_INSERT %0, %1, 0
-...
----
-name: insert_lo32_i64_va
-legalized: true
-
-body: |
- bb.0:
- liveins: $vgpr0_vgpr1, $agpr2
- ; CHECK-LABEL: name: insert_lo32_i64_va
- ; CHECK: liveins: $vgpr0_vgpr1, $agpr2
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:agpr(s32) = COPY $agpr2
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[INSERT:%[0-9]+]]:vgpr(s64) = G_INSERT [[COPY]], [[COPY2]](s32), 0
- %0:_(s64) = COPY $vgpr0_vgpr1
- %1:_(s32) = COPY $agpr2
- %2:_(s64) = G_INSERT %0, %1, 0
-...
-
----
-name: insert_lo32_i64_as
-legalized: true
-
-body: |
- bb.0:
- liveins: $agpr0_agpr1, $sgpr2
- ; CHECK-LABEL: name: insert_lo32_i64_as
- ; CHECK: liveins: $agpr0_agpr1, $sgpr2
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:agpr(s64) = COPY $agpr0_agpr1
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[INSERT:%[0-9]+]]:vgpr(s64) = G_INSERT [[COPY2]], [[COPY3]](s32), 0
- %0:_(s64) = COPY $agpr0_agpr1
- %1:_(s32) = COPY $sgpr2
- %2:_(s64) = G_INSERT %0, %1, 0
-...
----
-name: insert_lo32_i64_sa
-legalized: true
-
-body: |
- bb.0:
- liveins: $sgpr0_sgpr1, $agpr2
- ; CHECK-LABEL: name: insert_lo32_i64_sa
- ; CHECK: liveins: $sgpr0_sgpr1, $agpr2
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:agpr(s32) = COPY $agpr2
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[INSERT:%[0-9]+]]:vgpr(s64) = G_INSERT [[COPY2]], [[COPY3]](s32), 0
- %0:_(s64) = COPY $sgpr0_sgpr1
- %1:_(s32) = COPY $agpr2
- %2:_(s64) = G_INSERT %0, %1, 0
-...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-merge-values.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-merge-values.mir
index e22df46b505a5..ac84146da0f98 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-merge-values.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-merge-values.mir
@@ -12,16 +12,14 @@ body: |
; CHECK-LABEL: name: merge_s64_s32_s32_ss
; CHECK: liveins: $sgpr0, $sgpr1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:sgpr(s32) = G_EXTRACT [[COPY]](s64), 0
- ; CHECK-NEXT: [[EXTRACT1:%[0-9]+]]:sgpr(s32) = G_EXTRACT [[COPY]](s64), 32
- ; CHECK-NEXT: [[MV:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[EXTRACT]](s32), [[EXTRACT1]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
; CHECK-NEXT: S_ENDPGM 0, implicit [[MV]](s64)
- %0:_(s64) = COPY $sgpr0_sgpr1
- %1:_(s32) = G_EXTRACT %0, 0
- %2:_(s32) = G_EXTRACT %0, 32
- %3:_(s64) = G_MERGE_VALUES %1, %2
- S_ENDPGM 0, implicit %3
+ %0:_(s32) = COPY $sgpr0
+ %1:_(s32) = COPY $sgpr1
+ %2:_(s64) = G_MERGE_VALUES %0, %1
+ S_ENDPGM 0, implicit %2
...
---
@@ -34,16 +32,14 @@ body: |
; CHECK-LABEL: name: merge_s64_s32_s32_s64
; CHECK: liveins: $vgpr0, $vgpr1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:vgpr(s32) = G_EXTRACT [[COPY]](s64), 0
- ; CHECK-NEXT: [[EXTRACT1:%[0-9]+]]:vgpr(s32) = G_EXTRACT [[COPY]](s64), 32
- ; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[EXTRACT]](s32), [[EXTRACT1]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
; CHECK-NEXT: S_ENDPGM 0, implicit [[MV]](s64)
- %0:_(s64) = COPY $vgpr0_vgpr1
- %1:_(s32) = G_EXTRACT %0, 0
- %2:_(s32) = G_EXTRACT %0, 32
- %3:_(s64) = G_MERGE_VALUES %1, %2
- S_ENDPGM 0, implicit %3
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = COPY $vgpr1
+ %2:_(s64) = G_MERGE_VALUES %0, %1
+ S_ENDPGM 0, implicit %2
...
---
>From cfc9ca0be2ed3765268605eb00b99637a2ae5dbb Mon Sep 17 00:00:00 2001
From: Vang Thao <vang.thao at amd.com>
Date: Fri, 6 Mar 2026 01:48:39 -0800
Subject: [PATCH 5/6] Do easy cases with custom unmerge/merge
---
.../CodeGen/GlobalISel/LegalizerHelper.cpp | 25 +-
.../lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 105 +++-
llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h | 2 +
.../GlobalISel/artifact-combiner-extract.mir | 29 +-
.../AMDGPU/GlobalISel/legalize-and.mir | 18 +-
.../AMDGPU/GlobalISel/legalize-extract.mir | 137 ++---
.../GlobalISel/legalize-implicit-def.mir | 5 +-
.../AMDGPU/GlobalISel/legalize-insert.mir | 501 ++++++++----------
.../GlobalISel/legalize-load-constant.mir | 66 +--
.../AMDGPU/GlobalISel/legalize-load-flat.mir | 176 +-----
.../GlobalISel/legalize-load-global.mir | 132 +----
.../CodeGen/AMDGPU/GlobalISel/legalize-or.mir | 18 +-
.../AMDGPU/GlobalISel/legalize-select.mir | 18 +-
.../AMDGPU/GlobalISel/legalize-xor.mir | 18 +-
14 files changed, 527 insertions(+), 723 deletions(-)
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index fb2da824de04b..3f2de2fe95d8e 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -9484,9 +9484,22 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerInsert(MachineInstr &MI) {
LLT DstTy = MRI.getType(Src);
LLT InsertTy = MRI.getType(InsertSrc);
+ const DataLayout &DL = MIRBuilder.getDataLayout();
+ bool IsNonIntegralInsert =
+ InsertTy.isPointerOrPointerVector() &&
+ DL.isNonIntegralAddressSpace(InsertTy.getAddressSpace());
+ bool IsNonIntegralDst = DstTy.isPointerOrPointerVector() &&
+ DL.isNonIntegralAddressSpace(DstTy.getAddressSpace());
+
// Insert sub-vector or one element
- if (DstTy.isVector() && !InsertTy.isPointer()) {
+ if (DstTy.isVector()) {
LLT EltTy = DstTy.getElementType();
+
+ if ((IsNonIntegralInsert || IsNonIntegralDst) && InsertTy != EltTy) {
+ LLVM_DEBUG(dbgs() << "Not casting non-integral address space integer\n");
+ return UnableToLegalize;
+ }
+
unsigned EltSize = EltTy.getSizeInBits();
unsigned InsertSize = InsertTy.getSizeInBits();
@@ -9508,6 +9521,10 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerInsert(MachineInstr &MI) {
DstElts.push_back(UnmergeInsertSrc.getReg(i));
}
} else {
+ if (InsertTy.isPointer() && !EltTy.isPointer())
+ InsertSrc = MIRBuilder.buildPtrToInt(EltTy, InsertSrc).getReg(0);
+ else if (!InsertTy.isPointer() && EltTy.isPointer())
+ InsertSrc = MIRBuilder.buildIntToPtr(EltTy, InsertSrc).getReg(0);
DstElts.push_back(InsertSrc);
++Idx;
}
@@ -9527,11 +9544,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerInsert(MachineInstr &MI) {
(DstTy.isVector() && DstTy.getElementType() != InsertTy))
return UnableToLegalize;
- const DataLayout &DL = MIRBuilder.getDataLayout();
- if ((DstTy.isPointer() &&
- DL.isNonIntegralAddressSpace(DstTy.getAddressSpace())) ||
- (InsertTy.isPointer() &&
- DL.isNonIntegralAddressSpace(InsertTy.getAddressSpace()))) {
+ if (IsNonIntegralDst || IsNonIntegralInsert) {
LLVM_DEBUG(dbgs() << "Not casting non-integral address space integer\n");
return UnableToLegalize;
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index d55f312c2e9cb..5756c046b4028 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -1938,13 +1938,21 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
return Query.Types[0] != EltTy;
});
- for (unsigned Op : {G_INSERT, G_EXTRACT}) {
- unsigned BigTyIdx = Op == G_INSERT ? 0 : 1;
- unsigned LitTyIdx = Op == G_INSERT ? 1 : 0;
+ for (unsigned Op : {G_EXTRACT, G_INSERT}) {
+ unsigned BigTyIdx = Op == G_EXTRACT ? 1 : 0;
+ unsigned LitTyIdx = Op == G_EXTRACT ? 0 : 1;
getActionDefinitionsBuilder(Op)
.lowerIf([=](const LegalityQuery &Query) {
+ return Query.Types[BigTyIdx].isVector();
+ })
+ .customIf([=](const LegalityQuery &Query) {
+ // Generic lower is not aware of subregs and can produce inefficient
+ // shift+trunc/mask sequences. We can instead use custom lowering
+ // for simple 32-bit aligned cases and use unmerge/merge.
const LLT BigTy = Query.Types[BigTyIdx];
- return BigTy.isVector();
+ const LLT LitTy = Query.Types[LitTyIdx];
+ return BigTy.getSizeInBits() % 32 == 0 &&
+ LitTy.getSizeInBits() % 32 == 0;
})
.widenScalarIf(
[=](const LegalityQuery &Query) {
@@ -2237,6 +2245,10 @@ bool AMDGPULegalizerInfo::legalizeCustom(
case TargetOpcode::G_FMINIMUMNUM:
case TargetOpcode::G_FMAXIMUMNUM:
return legalizeMinNumMaxNum(Helper, MI);
+ case TargetOpcode::G_EXTRACT:
+ return legalizeExtract(Helper, MI);
+ case TargetOpcode::G_INSERT:
+ return legalizeInsert(Helper, MI);
case TargetOpcode::G_EXTRACT_VECTOR_ELT:
return legalizeExtractVectorElt(MI, MRI, B);
case TargetOpcode::G_INSERT_VECTOR_ELT:
@@ -2872,6 +2884,91 @@ bool AMDGPULegalizerInfo::legalizeMinNumMaxNum(LegalizerHelper &Helper,
return Helper.lowerFMinNumMaxNum(MI) == LegalizerHelper::Legalized;
}
+bool AMDGPULegalizerInfo::legalizeExtract(LegalizerHelper &Helper,
+ MachineInstr &MI) const {
+ MachineIRBuilder &B = Helper.MIRBuilder;
+ MachineRegisterInfo &MRI = *B.getMRI();
+ Register DstReg = MI.getOperand(0).getReg();
+ Register SrcReg = MI.getOperand(1).getReg();
+ uint64_t Offset = MI.getOperand(2).getImm();
+
+ // Fall back to generic lowering for offset 0 (trivial trunc) and
+ // non-32-bit-aligned cases which require shift+trunc sequences
+ // that generic code handles correctly.
+ if (Offset == 0 || Offset % 32 != 0)
+ return Helper.lowerExtract(MI) == LegalizerHelper::Legalized;
+
+ const LLT DstTy = MRI.getType(DstReg);
+ unsigned StartIdx = Offset / 32;
+ unsigned DstCount = DstTy.getSizeInBits() / 32;
+ auto Unmerge = B.buildUnmerge(LLT::scalar(32), SrcReg);
+
+ if (DstCount == 1) {
+ if (DstTy.isPointer())
+ B.buildIntToPtr(DstReg, Unmerge.getReg(StartIdx));
+ else
+ MRI.replaceRegWith(DstReg, Unmerge.getReg(StartIdx));
+ } else {
+ SmallVector<Register, 8> MergeVec;
+ for (unsigned I = 0; I < DstCount; ++I)
+ MergeVec.push_back(Unmerge.getReg(StartIdx + I));
+ B.buildMergeLikeInstr(DstReg, MergeVec);
+ }
+
+ MI.eraseFromParent();
+ return true;
+}
+
+bool AMDGPULegalizerInfo::legalizeInsert(LegalizerHelper &Helper,
+ MachineInstr &MI) const {
+ MachineIRBuilder &B = Helper.MIRBuilder;
+ MachineRegisterInfo &MRI = *B.getMRI();
+ Register DstReg = MI.getOperand(0).getReg();
+ Register SrcReg = MI.getOperand(1).getReg();
+ Register InsertSrc = MI.getOperand(2).getReg();
+ uint64_t Offset = MI.getOperand(3).getImm();
+
+ unsigned DstSize = MRI.getType(DstReg).getSizeInBits();
+ const LLT InsertTy = MRI.getType(InsertSrc);
+ unsigned InsertSize = InsertTy.getSizeInBits();
+
+ // Fall back to generic lowering for non-32-bit-aligned cases which
+ // require shift+mask sequences that generic code handles correctly.
+ if (Offset % 32 != 0 || DstSize % 32 != 0 || InsertSize % 32 != 0)
+ return Helper.lowerInsert(MI) == LegalizerHelper::Legalized;
+
+ const LLT S32 = LLT::scalar(32);
+ unsigned DstCount = DstSize / 32;
+ unsigned InsertCount = InsertSize / 32;
+ unsigned StartIdx = Offset / 32;
+
+ auto SrcUnmerge = B.buildUnmerge(S32, SrcReg);
+
+ SmallVector<Register, 8> MergeVec;
+ for (unsigned I = 0; I < StartIdx; ++I)
+ MergeVec.push_back(SrcUnmerge.getReg(I));
+
+ if (InsertCount == 1) {
+ // Merge-like instructions require same source types. Convert pointer
+ // to scalar when inserting a pointer value into a scalar.
+ if (InsertTy.isPointer())
+ InsertSrc = B.buildPtrToInt(S32, InsertSrc).getReg(0);
+ MergeVec.push_back(InsertSrc);
+ } else {
+ auto InsertUnmerge = B.buildUnmerge(S32, InsertSrc);
+ for (unsigned I = 0; I < InsertCount; ++I)
+ MergeVec.push_back(InsertUnmerge.getReg(I));
+ }
+
+ for (unsigned I = StartIdx + InsertCount; I < DstCount; ++I)
+ MergeVec.push_back(SrcUnmerge.getReg(I));
+
+ B.buildMergeLikeInstr(DstReg, MergeVec);
+
+ MI.eraseFromParent();
+ return true;
+}
+
bool AMDGPULegalizerInfo::legalizeExtractVectorElt(
MachineInstr &MI, MachineRegisterInfo &MRI,
MachineIRBuilder &B) const {
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
index 1224ee7ac60be..f0f3febd1fae5 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
@@ -56,6 +56,8 @@ class AMDGPULegalizerInfo final : public LegalizerInfo {
bool legalizeFPTOI(MachineInstr &MI, MachineRegisterInfo &MRI,
MachineIRBuilder &B, bool Signed) const;
bool legalizeMinNumMaxNum(LegalizerHelper &Helper, MachineInstr &MI) const;
+ bool legalizeExtract(LegalizerHelper &Helper, MachineInstr &MI) const;
+ bool legalizeInsert(LegalizerHelper &Helper, MachineInstr &MI) const;
bool legalizeExtractVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
MachineIRBuilder &B) const;
bool legalizeInsertVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-extract.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-extract.mir
index b88febd5cd980..870207bf5a069 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-extract.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-extract.mir
@@ -86,8 +86,9 @@ name: extract_s32_merge_s128_s64_s64_offset32
body: |
bb.0:
; CHECK-LABEL: name: extract_s32_merge_s128_s64_s64_offset32
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: $vgpr0 = COPY [[C]](s32)
+ ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64)
+ ; CHECK-NEXT: $vgpr0 = COPY [[UV1]](s32)
%0:_(s64) = G_CONSTANT i64 0
%1:_(s64) = G_CONSTANT i64 1
%2:_(s128) = G_MERGE_VALUES %0, %1
@@ -117,8 +118,8 @@ body: |
bb.0:
; CHECK-LABEL: name: extract_s32_merge_s128_s64_s64_offset96
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: $vgpr0 = COPY [[C1]](s32)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64)
+ ; CHECK-NEXT: $vgpr0 = COPY [[UV1]](s32)
%0:_(s64) = G_CONSTANT i64 0
%1:_(s64) = G_CONSTANT i64 1
%2:_(s128) = G_MERGE_VALUES %0, %1
@@ -171,11 +172,10 @@ body: |
; CHECK-LABEL: name: extract_s64_merge_s128_s64_s64_offset32
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[C]], [[C2]](s32)
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[C1]], [[C2]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]]
- ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[OR]](s64)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64)
+ ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C1]](s64)
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV1]](s32), [[UV2]](s32)
+ ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
%0:_(s64) = G_CONSTANT i64 0
%1:_(s64) = G_CONSTANT i64 1
%2:_(s128) = G_MERGE_VALUES %0, %1
@@ -266,17 +266,10 @@ name: extract_s64_merge_s96_s32_s32_s32_offset32
body: |
bb.0:
; CHECK-LABEL: name: extract_s64_merge_s96_s32_s32_s32_offset32
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C]](s32), [[C1]](s32)
- ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C2]](s32), [[DEF]](s32)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[MV]], [[C3]](s32)
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[MV1]], [[C3]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]]
- ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[OR]](s64)
+ ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
%0:_(s32) = G_CONSTANT i32 0
%1:_(s32) = G_CONSTANT i32 1
%2:_(s32) = G_CONSTANT i32 1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
index b679d783751e4..8a16a0df8056a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
@@ -148,17 +148,15 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s96) = COPY $vgpr0_vgpr1_vgpr2
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s96) = COPY $vgpr3_vgpr4_vgpr5
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s96)
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96)
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
- ; CHECK-NEXT: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96)
- ; CHECK-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s96)
- ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV6]](s32), [[UV7]](s32)
- ; CHECK-NEXT: [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s96)
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[MV]], [[MV1]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV5]], [[UV11]]
- ; CHECK-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND]](s64)
- ; CHECK-NEXT: [[MV2:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[UV12]](s32), [[UV13]](s32), [[AND1]](s32)
- ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[MV2]](s96)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s64) = G_TRUNC [[COPY1]](s96)
+ ; CHECK-NEXT: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s96)
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[TRUNC]], [[TRUNC1]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV2]], [[UV5]]
+ ; CHECK-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND]](s64)
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[UV6]](s32), [[UV7]](s32), [[AND1]](s32)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[MV]](s96)
%0:_(s96) = COPY $vgpr0_vgpr1_vgpr2
%1:_(s96) = COPY $vgpr3_vgpr4_vgpr5
%2:_(s96) = G_AND %0, %1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
index 4d55b2981280d..fcd114dd3b6e3 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck %s
---
name: test_extract_s32_s64_offset0
@@ -27,10 +27,8 @@ body: |
; CHECK: liveins: $vgpr0_vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[C]](s32)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)
- ; CHECK-NEXT: $vgpr0 = COPY [[TRUNC]](s32)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
+ ; CHECK-NEXT: $vgpr0 = COPY [[UV1]](s32)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = G_EXTRACT %0, 32
$vgpr0 = COPY %1
@@ -102,8 +100,8 @@ body: |
; CHECK: liveins: $vgpr0_vgpr1_vgpr2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s96) = COPY $vgpr0_vgpr1_vgpr2
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96)
- ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s96)
+ ; CHECK-NEXT: $vgpr0 = COPY [[TRUNC]](s32)
%0:_(s96) = COPY $vgpr0_vgpr1_vgpr2
%1:_(s32) = G_EXTRACT %0, 0
$vgpr0 = COPY %1
@@ -119,15 +117,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s96) = COPY $vgpr0_vgpr1_vgpr2
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96)
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
- ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV2]](s32), [[DEF]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[MV]], [[C]](s32)
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[MV1]], [[C]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]]
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[OR]](s64)
- ; CHECK-NEXT: $vgpr0 = COPY [[TRUNC]](s32)
+ ; CHECK-NEXT: $vgpr0 = COPY [[UV1]](s32)
%0:_(s96) = COPY $vgpr0_vgpr1_vgpr2
%1:_(s32) = G_EXTRACT %0, 32
$vgpr0 = COPY %1
@@ -174,13 +164,8 @@ body: |
; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C]](s32)
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]]
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[OR]](s64)
- ; CHECK-NEXT: $vgpr0 = COPY [[TRUNC]](s32)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s128)
+ ; CHECK-NEXT: $vgpr0 = COPY [[UV1]](s32)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s32) = G_EXTRACT %0, 32
$vgpr0 = COPY %1
@@ -195,9 +180,8 @@ body: |
; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[UV1]](s64)
- ; CHECK-NEXT: $vgpr0 = COPY [[TRUNC]](s32)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s128)
+ ; CHECK-NEXT: $vgpr0 = COPY [[UV2]](s32)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s32) = G_EXTRACT %0, 64
$vgpr0 = COPY %1
@@ -212,11 +196,8 @@ body: |
; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[C]](s32)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)
- ; CHECK-NEXT: $vgpr0 = COPY [[TRUNC]](s32)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s128)
+ ; CHECK-NEXT: $vgpr0 = COPY [[UV3]](s32)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s32) = G_EXTRACT %0, 96
$vgpr0 = COPY %1
@@ -334,13 +315,8 @@ body: |
; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C]](s32)
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]]
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[OR]](s64)
- ; CHECK-NEXT: $vgpr0 = COPY [[TRUNC]](s32)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s128)
+ ; CHECK-NEXT: $vgpr0 = COPY [[UV1]](s32)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s32) = G_EXTRACT %0, 32
$vgpr0 = COPY %1
@@ -355,9 +331,8 @@ body: |
; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[UV1]](s64)
- ; CHECK-NEXT: $vgpr0 = COPY [[TRUNC]](s32)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s128)
+ ; CHECK-NEXT: $vgpr0 = COPY [[UV2]](s32)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s32) = G_EXTRACT %0, 64
$vgpr0 = COPY %1
@@ -372,11 +347,8 @@ body: |
; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[C]](s32)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)
- ; CHECK-NEXT: $vgpr0 = COPY [[TRUNC]](s32)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s128)
+ ; CHECK-NEXT: $vgpr0 = COPY [[UV3]](s32)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s32) = G_EXTRACT %0, 96
$vgpr0 = COPY %1
@@ -1372,12 +1344,9 @@ body: |
; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C]](s32)
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]]
- ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[OR]](s64)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s128)
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV1]](s32), [[UV2]](s32)
+ ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s64) = G_EXTRACT %0, 32
$vgpr0_vgpr1 = COPY %1
@@ -1425,20 +1394,31 @@ body: |
; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C]](s32)
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]]
- ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[C]](s32)
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[LSHR1]](s64)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s96) = G_TRUNC [[MV]](s128)
- ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[TRUNC]](s96)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s128)
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[UV1]](s32), [[UV2]](s32), [[UV3]](s32)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[MV]](s96)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s96) = G_EXTRACT %0, 32
$vgpr0_vgpr1_vgpr2 = COPY %1
...
+---
+name: test_extract_s96_s288_offset96
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8
+
+ ; CHECK-LABEL: name: test_extract_s96_s288_offset96
+ ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s288) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s96), [[UV1:%[0-9]+]]:_(s96), [[UV2:%[0-9]+]]:_(s96) = G_UNMERGE_VALUES [[COPY]](s288)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[UV1]](s96)
+ %0:_(s288) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8
+ %1:_(s96) = G_EXTRACT %0, 96
+ $vgpr0_vgpr1_vgpr2 = COPY %1
+...
+
---
name: test_extract_p3_p0_offset0
body: |
@@ -1457,6 +1437,41 @@ body: |
$vgpr0 = COPY %1
...
+---
+name: test_extract_s32_p0_offset32
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: test_extract_s32_p0_offset32
+ ; CHECK: liveins: $vgpr0_vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](p0)
+ ; CHECK-NEXT: $vgpr0 = COPY [[UV1]](s32)
+ %0:_(p0) = COPY $vgpr0_vgpr1
+ %1:_(s32) = G_EXTRACT %0, 32
+ $vgpr0 = COPY %1
+...
+
+---
+name: test_extract_p3_s64_offset32
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: test_extract_p3_s64_offset32
+ ; CHECK: liveins: $vgpr0_vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
+ ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p3) = G_INTTOPTR [[UV1]](s32)
+ ; CHECK-NEXT: $vgpr0 = COPY [[INTTOPTR]](p3)
+ %0:_(s64) = COPY $vgpr0_vgpr1
+ %1:_(p3) = G_EXTRACT %0, 32
+ $vgpr0 = COPY %1
+...
+
---
name: test_extract_s90_s128_offset9
body: |
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def.mir
index d8503ecd7df20..ca5475bbdbc8c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def.mir
@@ -135,8 +135,9 @@ body: |
bb.0:
; CHECK-LABEL: name: test_implicit_def_s448
- ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: $vgpr0 = COPY [[DEF]](s32)
+ ; CHECK: [[DEF:%[0-9]+]]:_(s512) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[DEF]](s512)
+ ; CHECK-NEXT: $vgpr0 = COPY [[TRUNC]](s32)
%0:_(s448) = G_IMPLICIT_DEF
%1:_(s32) = G_EXTRACT %0, 0
$vgpr0 = COPY %1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert.mir
index 554340ca88af1..1a6b7e0dcacca 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -run-pass=legalizer %s -o - | FileCheck %s
---
name: test_insert_s64_s32_offset0
@@ -12,12 +12,9 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY1]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4294967296
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[ZEXT]]
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY [[OR]](s64)
- ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[COPY2]](s64)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY1]](s32), [[UV1]](s32)
+ ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = COPY $vgpr2
%2:_(s64) = G_INSERT %0, %1, 0
@@ -34,14 +31,9 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY1]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ZEXT]], [[C]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]]
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[SHL]]
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY [[OR]](s64)
- ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[COPY2]](s64)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[COPY1]](s32)
+ ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = COPY $vgpr2
%2:_(s64) = G_INSERT %0, %1, 32
@@ -85,22 +77,8 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s96) = COPY $vgpr0_vgpr1_vgpr2
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr3
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96)
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
- ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV2]](s32), [[DEF]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY1]](s32), [[C]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4294967296
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[MV]], [[C2]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[MV1]], [[C3]]
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[MV2]]
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[C1]]
- ; CHECK-NEXT: [[MV3:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[OR1]](s64)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s128) = COPY [[MV3]](s128)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s96) = G_TRUNC [[COPY2]](s128)
- ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[TRUNC]](s96)
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[COPY1]](s32), [[UV1]](s32), [[UV2]](s32)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[MV]](s96)
%0:_(s96) = COPY $vgpr0_vgpr1_vgpr2
%1:_(s32) = COPY $vgpr3
%2:_(s96) = G_INSERT %0, %1, 0
@@ -118,27 +96,8 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s96) = COPY $vgpr0_vgpr1_vgpr2
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr3
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96)
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
- ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV2]](s32), [[DEF]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY1]](s32), [[C]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[MV2]], [[C2]](s32)
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[C1]], [[C2]](s32)
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[MV2]], [[C2]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]]
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[MV]], [[C3]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[MV1]], [[C4]]
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND]], [[SHL]]
- ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[OR]]
- ; CHECK-NEXT: [[MV3:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR1]](s64), [[OR2]](s64)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s128) = COPY [[MV3]](s128)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s96) = G_TRUNC [[COPY2]](s128)
- ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[TRUNC]](s96)
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[UV]](s32), [[COPY1]](s32), [[UV2]](s32)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[MV]](s96)
%0:_(s96) = COPY $vgpr0_vgpr1_vgpr2
%1:_(s32) = COPY $vgpr3
%2:_(s96) = G_INSERT %0, %1, 32
@@ -156,22 +115,8 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s96) = COPY $vgpr0_vgpr1_vgpr2
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr3
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96)
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
- ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV2]](s32), [[DEF]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY1]](s32), [[C]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4294967296
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[MV]], [[C2]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[MV1]], [[C3]]
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[C1]]
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[MV2]]
- ; CHECK-NEXT: [[MV3:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[OR1]](s64)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s128) = COPY [[MV3]](s128)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s96) = G_TRUNC [[COPY2]](s128)
- ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[TRUNC]](s96)
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32), [[COPY1]](s32)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[MV]](s96)
%0:_(s96) = COPY $vgpr0_vgpr1_vgpr2
%1:_(s32) = COPY $vgpr3
%2:_(s96) = G_INSERT %0, %1, 64
@@ -188,19 +133,9 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY1]](s32), [[C]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4294967296
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[UV]], [[C2]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[UV1]], [[C3]]
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[MV]]
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[C1]]
- ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[OR1]](s64)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s128) = COPY [[MV1]](s128)
- ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[COPY2]](s128)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s128)
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY1]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s32) = COPY $vgpr4
%2:_(s128) = G_INSERT %0, %1, 0
@@ -217,24 +152,9 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY1]](s32), [[C]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[MV]], [[C2]](s32)
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[C1]], [[C2]](s32)
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[MV]], [[C2]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]]
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[UV]], [[C3]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[UV1]], [[C4]]
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND]], [[SHL]]
- ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[OR]]
- ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR1]](s64), [[OR2]](s64)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s128) = COPY [[MV1]](s128)
- ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[COPY2]](s128)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s128)
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[UV]](s32), [[COPY1]](s32), [[UV2]](s32), [[UV3]](s32)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s32) = COPY $vgpr4
%2:_(s128) = G_INSERT %0, %1, 32
@@ -251,19 +171,9 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY1]](s32), [[C]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4294967296
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[UV]], [[C2]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[UV1]], [[C3]]
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[C1]]
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[MV]]
- ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[OR1]](s64)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s128) = COPY [[MV1]](s128)
- ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[COPY2]](s128)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s128)
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32), [[COPY1]](s32), [[UV3]](s32)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s32) = COPY $vgpr4
%2:_(s128) = G_INSERT %0, %1, 64
@@ -280,21 +190,9 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY1]](s32), [[C]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[MV]], [[C2]](s32)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[UV]], [[C3]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[UV1]], [[C4]]
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[C1]]
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[SHL]]
- ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[OR1]](s64)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s128) = COPY [[MV1]](s128)
- ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[COPY2]](s128)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s128)
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[COPY1]](s32)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s32) = COPY $vgpr4
%2:_(s128) = G_INSERT %0, %1, 96
@@ -311,16 +209,10 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr4_vgpr5
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[UV]], [[C]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[UV1]], [[C1]]
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[COPY1]]
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[C]]
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[OR1]](s64)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s128) = COPY [[MV]](s128)
- ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[COPY2]](s128)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s128)
+ ; CHECK-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64)
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[UV4]](s32), [[UV5]](s32), [[UV2]](s32), [[UV3]](s32)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s64) = COPY $vgpr4_vgpr5
%2:_(s128) = G_INSERT %0, %1, 0
@@ -337,22 +229,10 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr4_vgpr5
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C1]](s32)
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[C]], [[C1]](s32)
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[C1]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]]
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4294967296
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[UV]], [[C2]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[UV1]], [[C3]]
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND]], [[SHL]]
- ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[OR]]
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR1]](s64), [[OR2]](s64)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s128) = COPY [[MV]](s128)
- ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[COPY2]](s128)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s128)
+ ; CHECK-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64)
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[UV]](s32), [[UV4]](s32), [[UV5]](s32), [[UV3]](s32)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s64) = COPY $vgpr4_vgpr5
%2:_(s128) = G_INSERT %0, %1, 32
@@ -369,16 +249,10 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr4_vgpr5
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[UV]], [[C1]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[UV1]], [[C]]
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[C]]
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[COPY1]]
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[OR1]](s64)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s128) = COPY [[MV]](s128)
- ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[COPY2]](s128)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s128)
+ ; CHECK-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64)
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32), [[UV4]](s32), [[UV5]](s32)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s64) = COPY $vgpr4_vgpr5
%2:_(s128) = G_INSERT %0, %1, 64
@@ -395,20 +269,10 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s96) = COPY $vgpr4_vgpr5_vgpr6
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s96)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
- ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV2]](s32), [[C]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4294967296
- ; CHECK-NEXT: [[UV3:%[0-9]+]]:_(s64), [[UV4:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[UV3]], [[C1]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[UV4]], [[C2]]
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[MV]]
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[MV1]]
- ; CHECK-NEXT: [[MV2:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[OR1]](s64)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s128) = COPY [[MV2]](s128)
- ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[COPY2]](s128)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s128)
+ ; CHECK-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s96)
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[UV4]](s32), [[UV5]](s32), [[UV6]](s32), [[UV3]](s32)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s96) = COPY $vgpr4_vgpr5_vgpr6
%2:_(s128) = G_INSERT %0, %1, 0
@@ -425,25 +289,10 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s96) = COPY $vgpr4_vgpr5_vgpr6
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s96)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
- ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV2]](s32), [[C]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[MV]], [[C2]](s32)
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[MV1]], [[C2]](s32)
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[MV]], [[C2]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]]
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
- ; CHECK-NEXT: [[UV3:%[0-9]+]]:_(s64), [[UV4:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[UV3]], [[C3]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[UV4]], [[C1]]
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND]], [[SHL]]
- ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[OR]]
- ; CHECK-NEXT: [[MV2:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR1]](s64), [[OR2]](s64)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s128) = COPY [[MV2]](s128)
- ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[COPY2]](s128)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s128)
+ ; CHECK-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s96)
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[UV]](s32), [[UV4]](s32), [[UV5]](s32), [[UV6]](s32)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s96) = COPY $vgpr4_vgpr5_vgpr6
%2:_(s128) = G_INSERT %0, %1, 32
@@ -460,13 +309,9 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY]](p0)
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY1]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4294967296
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[PTRTOINT]], [[C]]
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[ZEXT]]
- ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[OR]](s64)
- ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[INTTOPTR]](p0)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](p0)
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY1]](s32), [[UV1]](s32)
+ ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[MV]](p0)
%0:_(p0) = COPY $vgpr0_vgpr1
%1:_(s32) = COPY $vgpr2
%2:_(p0) = G_INSERT %0, %1, 0
@@ -483,15 +328,9 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY]](p0)
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY1]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ZEXT]], [[C]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[PTRTOINT]], [[C1]]
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[SHL]]
- ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[OR]](s64)
- ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[INTTOPTR]](p0)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](p0)
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[UV]](s32), [[COPY1]](s32)
+ ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[MV]](p0)
%0:_(p0) = COPY $vgpr0_vgpr1
%1:_(s32) = COPY $vgpr2
%2:_(p0) = G_INSERT %0, %1, 32
@@ -508,17 +347,10 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $vgpr4_vgpr5
- ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY1]](p0)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[UV]], [[C]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[UV1]], [[C1]]
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[PTRTOINT]]
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[C]]
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[OR1]](s64)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s128) = COPY [[MV]](s128)
- ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[COPY2]](s128)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s128)
+ ; CHECK-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](p0)
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[UV4]](s32), [[UV5]](s32), [[UV2]](s32), [[UV3]](s32)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(p0) = COPY $vgpr4_vgpr5
%2:_(s128) = G_INSERT %0, %1, 0
@@ -535,23 +367,10 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $vgpr4_vgpr5
- ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY1]](p0)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[PTRTOINT]], [[C1]](s32)
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[C]], [[C1]](s32)
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[PTRTOINT]], [[C1]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]]
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4294967296
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[UV]], [[C2]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[UV1]], [[C3]]
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND]], [[SHL]]
- ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[OR]]
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR1]](s64), [[OR2]](s64)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s128) = COPY [[MV]](s128)
- ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[COPY2]](s128)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s128)
+ ; CHECK-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](p0)
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[UV]](s32), [[UV4]](s32), [[UV5]](s32), [[UV3]](s32)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(p0) = COPY $vgpr4_vgpr5
%2:_(s128) = G_INSERT %0, %1, 32
@@ -568,23 +387,37 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $vgpr4_vgpr5
- ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY1]](p0)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[UV]], [[C1]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[UV1]], [[C]]
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[C]]
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[PTRTOINT]]
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[OR1]](s64)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s128) = COPY [[MV]](s128)
- ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[COPY2]](s128)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s128)
+ ; CHECK-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](p0)
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32), [[UV4]](s32), [[UV5]](s32)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(p0) = COPY $vgpr4_vgpr5
%2:_(s128) = G_INSERT %0, %1, 64
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %2
...
+---
+name: test_insert_s64_p3_offset32
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2
+
+ ; CHECK-LABEL: name: test_insert_s64_p3_offset32
+ ; CHECK: liveins: $vgpr0_vgpr1, $vgpr2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p3) = COPY $vgpr2
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY1]](p3)
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[PTRTOINT]](s32)
+ ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
+ %0:_(s64) = COPY $vgpr0_vgpr1
+ %1:_(p3) = COPY $vgpr2
+ %2:_(s64) = G_INSERT %0, %1, 32
+ $vgpr0_vgpr1 = COPY %2
+...
+
---
name: test_insert_s128_s16_offset0
body: |
@@ -1118,8 +951,10 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $vgpr4_vgpr5
- ; CHECK-NEXT: [[INSERT:%[0-9]+]]:_(<4 x s32>) = G_INSERT [[COPY]], [[COPY1]](p0), 0
- ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[INSERT]](<4 x s32>)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
+ ; CHECK-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](p0)
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV4]](s32), [[UV5]](s32), [[UV2]](s32), [[UV3]](s32)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
%0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(p0) = COPY $vgpr4_vgpr5
%2:_(<4 x s32>) = G_INSERT %0, %1, 0
@@ -1136,8 +971,10 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $vgpr4_vgpr5
- ; CHECK-NEXT: [[INSERT:%[0-9]+]]:_(<4 x s32>) = G_INSERT [[COPY]], [[COPY1]](p0), 32
- ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[INSERT]](<4 x s32>)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
+ ; CHECK-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](p0)
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV4]](s32), [[UV5]](s32), [[UV3]](s32)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
%0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(p0) = COPY $vgpr4_vgpr5
%2:_(<4 x s32>) = G_INSERT %0, %1, 32
@@ -1154,14 +991,140 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $vgpr4_vgpr5
- ; CHECK-NEXT: [[INSERT:%[0-9]+]]:_(<4 x s32>) = G_INSERT [[COPY]], [[COPY1]](p0), 64
- ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[INSERT]](<4 x s32>)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
+ ; CHECK-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](p0)
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV4]](s32), [[UV5]](s32)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
%0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(p0) = COPY $vgpr4_vgpr5
%2:_(<4 x s32>) = G_INSERT %0, %1, 64
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %2
...
+---
+name: test_insert_v2s64_p0_offset0
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5
+
+ ; CHECK-LABEL: name: test_insert_v2s64_p0_offset0
+ ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $vgpr4_vgpr5
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY1]](p0)
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[PTRTOINT]](s64), [[UV1]](s64)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
+ %0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ %1:_(p0) = COPY $vgpr4_vgpr5
+ %2:_(<2 x s64>) = G_INSERT %0, %1, 0
+ $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %2
+...
+
+---
+name: test_insert_v2p0_p0_offset0
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5
+
+ ; CHECK-LABEL: name: test_insert_v2p0_p0_offset0
+ ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x p0>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $vgpr4_vgpr5
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(p0), [[UV1:%[0-9]+]]:_(p0) = G_UNMERGE_VALUES [[COPY]](<2 x p0>)
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p0>) = G_BUILD_VECTOR [[COPY1]](p0), [[UV1]](p0)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x p0>)
+ %0:_(<2 x p0>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ %1:_(p0) = COPY $vgpr4_vgpr5
+ %2:_(<2 x p0>) = G_INSERT %0, %1, 0
+ $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %2
+...
+
+---
+name: test_insert_v4p3_p3_offset0
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
+
+ ; CHECK-LABEL: name: test_insert_v4p3_p3_offset0
+ ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x p3>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p3) = COPY $vgpr4
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(p3), [[UV1:%[0-9]+]]:_(p3), [[UV2:%[0-9]+]]:_(p3), [[UV3:%[0-9]+]]:_(p3) = G_UNMERGE_VALUES [[COPY]](<4 x p3>)
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x p3>) = G_BUILD_VECTOR [[COPY1]](p3), [[UV1]](p3), [[UV2]](p3), [[UV3]](p3)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x p3>)
+ %0:_(<4 x p3>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ %1:_(p3) = COPY $vgpr4
+ %2:_(<4 x p3>) = G_INSERT %0, %1, 0
+ $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %2
+...
+
+---
+name: test_insert_v4p3_s32_offset0
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
+
+ ; CHECK-LABEL: name: test_insert_v4p3_s32_offset0
+ ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x p3>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr4
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(p3), [[UV1:%[0-9]+]]:_(p3), [[UV2:%[0-9]+]]:_(p3), [[UV3:%[0-9]+]]:_(p3) = G_UNMERGE_VALUES [[COPY]](<4 x p3>)
+ ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p3) = G_INTTOPTR [[COPY1]](s32)
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x p3>) = G_BUILD_VECTOR [[INTTOPTR]](p3), [[UV1]](p3), [[UV2]](p3), [[UV3]](p3)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x p3>)
+ %0:_(<4 x p3>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ %1:_(s32) = COPY $vgpr4
+ %2:_(<4 x p3>) = G_INSERT %0, %1, 0
+ $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %2
+...
+
+---
+name: test_insert_v4p0_v2p0_offset0
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11
+
+ ; CHECK-LABEL: name: test_insert_v4p0_v2p0_offset0
+ ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x p0>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x p0>) = COPY $vgpr8_vgpr9_vgpr10_vgpr11
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(p0), [[UV1:%[0-9]+]]:_(p0), [[UV2:%[0-9]+]]:_(p0), [[UV3:%[0-9]+]]:_(p0) = G_UNMERGE_VALUES [[COPY]](<4 x p0>)
+ ; CHECK-NEXT: [[UV4:%[0-9]+]]:_(p0), [[UV5:%[0-9]+]]:_(p0) = G_UNMERGE_VALUES [[COPY1]](<2 x p0>)
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x p0>) = G_BUILD_VECTOR [[UV4]](p0), [[UV5]](p0), [[UV2]](p0), [[UV3]](p0)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x p0>)
+ %0:_(<4 x p0>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+ %1:_(<2 x p0>) = COPY $vgpr8_vgpr9_vgpr10_vgpr11
+ %2:_(<4 x p0>) = G_INSERT %0, %1, 0
+ $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY %2
+...
+
+---
+name: test_insert_v4p0_v2p0_offset64
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11
+
+ ; CHECK-LABEL: name: test_insert_v4p0_v2p0_offset64
+ ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x p0>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x p0>) = COPY $vgpr8_vgpr9_vgpr10_vgpr11
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(p0), [[UV1:%[0-9]+]]:_(p0), [[UV2:%[0-9]+]]:_(p0), [[UV3:%[0-9]+]]:_(p0) = G_UNMERGE_VALUES [[COPY]](<4 x p0>)
+ ; CHECK-NEXT: [[UV4:%[0-9]+]]:_(p0), [[UV5:%[0-9]+]]:_(p0) = G_UNMERGE_VALUES [[COPY1]](<2 x p0>)
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x p0>) = G_BUILD_VECTOR [[UV]](p0), [[UV4]](p0), [[UV5]](p0), [[UV3]](p0)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x p0>)
+ %0:_(<4 x p0>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+ %1:_(<2 x p0>) = COPY $vgpr8_vgpr9_vgpr10_vgpr11
+ %2:_(<4 x p0>) = G_INSERT %0, %1, 64
+ $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY %2
+...
+
---
name: test_insert_v2s16_s16_offset0
body: |
@@ -1936,14 +1899,14 @@ body: |
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -65536
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[AND]]
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
; CHECK-NEXT: $vgpr0 = COPY [[COPY2]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s16) = G_TRUNC %1
- %3:_(s32) = G_INSERT %1, %2, 0
+ %3:_(s32) = G_INSERT %0, %2, 0
$vgpr0 = COPY %3
...
@@ -1963,14 +1926,14 @@ body: |
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C1]](s32)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -131071
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C2]]
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL]]
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
; CHECK-NEXT: $vgpr0 = COPY [[COPY2]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s16) = G_TRUNC %1
- %3:_(s32) = G_INSERT %1, %2, 1
+ %3:_(s32) = G_INSERT %0, %2, 1
$vgpr0 = COPY %3
...
@@ -1990,14 +1953,14 @@ body: |
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C1]](s32)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -16776961
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C2]]
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL]]
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
; CHECK-NEXT: $vgpr0 = COPY [[COPY2]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s16) = G_TRUNC %1
- %3:_(s32) = G_INSERT %1, %2, 8
+ %3:_(s32) = G_INSERT %0, %2, 8
$vgpr0 = COPY %3
...
@@ -2014,15 +1977,15 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C1]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
- ; CHECK-NEXT: $vgpr0 = COPY [[COPY3]](s32)
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C1]](s32)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL]]
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
+ ; CHECK-NEXT: $vgpr0 = COPY [[COPY2]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s16) = G_TRUNC %1
- %3:_(s32) = G_INSERT %1, %2, 16
+ %3:_(s32) = G_INSERT %0, %2, 16
$vgpr0 = COPY %3
...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
index 84ff95404f365..8d3bd6d1704ee 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
@@ -1365,26 +1365,10 @@ body: |
; CI-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD1]](<3 x s32>)
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<7 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32), [[UV4]](s32), [[UV5]](s32), [[UV6]](s32)
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(s224) = G_BITCAST [[BUILD_VECTOR]](<7 x s32>)
- ; CI-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+ ; CI-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CI-NEXT: [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BITCAST]](s224)
- ; CI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CI-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV7]](s32), [[UV8]](s32)
- ; CI-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV9]](s32), [[UV10]](s32)
- ; CI-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV11]](s32), [[UV12]](s32)
- ; CI-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV13]](s32), [[C1]](s32)
- ; CI-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CI-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4294967296
- ; CI-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
- ; CI-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
- ; CI-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
- ; CI-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C3]]
- ; CI-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[MV]]
- ; CI-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[MV1]]
- ; CI-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[AND2]], [[MV2]]
- ; CI-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[AND3]], [[MV3]]
- ; CI-NEXT: [[MV4:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[OR]](s64), [[OR1]](s64), [[OR2]](s64), [[OR3]](s64)
- ; CI-NEXT: [[COPY1:%[0-9]+]]:_(s256) = COPY [[MV4]](s256)
- ; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[COPY1]](s256)
+ ; CI-NEXT: [[MV:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[UV7]](s32), [[UV8]](s32), [[UV9]](s32), [[UV10]](s32), [[UV11]](s32), [[UV12]](s32), [[UV13]](s32), [[DEF]](s32)
+ ; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[MV]](s256)
;
; VI-LABEL: name: test_load_constant_s224_align4
; VI: liveins: $vgpr0_vgpr1
@@ -1398,26 +1382,10 @@ body: |
; VI-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD1]](<3 x s32>)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<7 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32), [[UV4]](s32), [[UV5]](s32), [[UV6]](s32)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(s224) = G_BITCAST [[BUILD_VECTOR]](<7 x s32>)
- ; VI-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+ ; VI-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; VI-NEXT: [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BITCAST]](s224)
- ; VI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; VI-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV7]](s32), [[UV8]](s32)
- ; VI-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV9]](s32), [[UV10]](s32)
- ; VI-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV11]](s32), [[UV12]](s32)
- ; VI-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV13]](s32), [[C1]](s32)
- ; VI-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; VI-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4294967296
- ; VI-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
- ; VI-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
- ; VI-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
- ; VI-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C3]]
- ; VI-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[MV]]
- ; VI-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[MV1]]
- ; VI-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[AND2]], [[MV2]]
- ; VI-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[AND3]], [[MV3]]
- ; VI-NEXT: [[MV4:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[OR]](s64), [[OR1]](s64), [[OR2]](s64), [[OR3]](s64)
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(s256) = COPY [[MV4]](s256)
- ; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[COPY1]](s256)
+ ; VI-NEXT: [[MV:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[UV7]](s32), [[UV8]](s32), [[UV9]](s32), [[UV10]](s32), [[UV11]](s32), [[UV12]](s32), [[UV13]](s32), [[DEF]](s32)
+ ; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[MV]](s256)
;
; GFX9-LABEL: name: test_load_constant_s224_align4
; GFX9: liveins: $vgpr0_vgpr1
@@ -1431,26 +1399,10 @@ body: |
; GFX9-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD1]](<3 x s32>)
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<7 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32), [[UV4]](s32), [[UV5]](s32), [[UV6]](s32)
; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(s224) = G_BITCAST [[BUILD_VECTOR]](<7 x s32>)
- ; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+ ; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; GFX9-NEXT: [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BITCAST]](s224)
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; GFX9-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV7]](s32), [[UV8]](s32)
- ; GFX9-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV9]](s32), [[UV10]](s32)
- ; GFX9-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV11]](s32), [[UV12]](s32)
- ; GFX9-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV13]](s32), [[C1]](s32)
- ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4294967296
- ; GFX9-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
- ; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
- ; GFX9-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
- ; GFX9-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C3]]
- ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[MV]]
- ; GFX9-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[MV1]]
- ; GFX9-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[AND2]], [[MV2]]
- ; GFX9-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[AND3]], [[MV3]]
- ; GFX9-NEXT: [[MV4:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[OR]](s64), [[OR1]](s64), [[OR2]](s64), [[OR3]](s64)
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s256) = COPY [[MV4]](s256)
- ; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[COPY1]](s256)
+ ; GFX9-NEXT: [[MV:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[UV7]](s32), [[UV8]](s32), [[UV9]](s32), [[UV10]](s32), [[UV11]](s32), [[UV12]](s32), [[UV13]](s32), [[DEF]](s32)
+ ; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[MV]](s256)
%0:_(p4) = COPY $vgpr0_vgpr1
%1:_(s224) = G_LOAD %0 :: (load (s224), align 4, addrspace 4)
%2:_(s256) = G_IMPLICIT_DEF
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
index e06ea9e97babb..4da6bc03708bc 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
@@ -2410,26 +2410,10 @@ body: |
; CI-NEXT: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p0) :: (load (s32) from unknown-address + 24)
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<7 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32), [[LOAD4]](s32), [[LOAD5]](s32), [[LOAD6]](s32)
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(s224) = G_BITCAST [[BUILD_VECTOR]](<7 x s32>)
- ; CI-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+ ; CI-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BITCAST]](s224)
- ; CI-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CI-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
- ; CI-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV2]](s32), [[UV3]](s32)
- ; CI-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV4]](s32), [[UV5]](s32)
- ; CI-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV6]](s32), [[C6]](s32)
- ; CI-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CI-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4294967296
- ; CI-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C7]]
- ; CI-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C7]]
- ; CI-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C7]]
- ; CI-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C8]]
- ; CI-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[MV]]
- ; CI-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[MV1]]
- ; CI-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[AND2]], [[MV2]]
- ; CI-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[AND3]], [[MV3]]
- ; CI-NEXT: [[MV4:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[OR]](s64), [[OR1]](s64), [[OR2]](s64), [[OR3]](s64)
- ; CI-NEXT: [[COPY1:%[0-9]+]]:_(s256) = COPY [[MV4]](s256)
- ; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[COPY1]](s256)
+ ; CI-NEXT: [[MV:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32), [[UV4]](s32), [[UV5]](s32), [[UV6]](s32), [[DEF]](s32)
+ ; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[MV]](s256)
;
; VI-LABEL: name: test_load_flat_s224_align4
; VI: liveins: $vgpr0_vgpr1
@@ -2456,26 +2440,10 @@ body: |
; VI-NEXT: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p0) :: (load (s32) from unknown-address + 24)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<7 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32), [[LOAD4]](s32), [[LOAD5]](s32), [[LOAD6]](s32)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(s224) = G_BITCAST [[BUILD_VECTOR]](<7 x s32>)
- ; VI-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+ ; VI-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; VI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BITCAST]](s224)
- ; VI-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; VI-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
- ; VI-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV2]](s32), [[UV3]](s32)
- ; VI-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV4]](s32), [[UV5]](s32)
- ; VI-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV6]](s32), [[C6]](s32)
- ; VI-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; VI-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4294967296
- ; VI-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C7]]
- ; VI-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C7]]
- ; VI-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C7]]
- ; VI-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C8]]
- ; VI-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[MV]]
- ; VI-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[MV1]]
- ; VI-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[AND2]], [[MV2]]
- ; VI-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[AND3]], [[MV3]]
- ; VI-NEXT: [[MV4:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[OR]](s64), [[OR1]](s64), [[OR2]](s64), [[OR3]](s64)
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(s256) = COPY [[MV4]](s256)
- ; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[COPY1]](s256)
+ ; VI-NEXT: [[MV:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32), [[UV4]](s32), [[UV5]](s32), [[UV6]](s32), [[DEF]](s32)
+ ; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[MV]](s256)
;
; GFX9PLUS-LABEL: name: test_load_flat_s224_align4
; GFX9PLUS: liveins: $vgpr0_vgpr1
@@ -2489,26 +2457,10 @@ body: |
; GFX9PLUS-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD1]](<3 x s32>)
; GFX9PLUS-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<7 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32), [[UV4]](s32), [[UV5]](s32), [[UV6]](s32)
; GFX9PLUS-NEXT: [[BITCAST:%[0-9]+]]:_(s224) = G_BITCAST [[BUILD_VECTOR]](<7 x s32>)
- ; GFX9PLUS-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+ ; GFX9PLUS-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; GFX9PLUS-NEXT: [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BITCAST]](s224)
- ; GFX9PLUS-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; GFX9PLUS-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV7]](s32), [[UV8]](s32)
- ; GFX9PLUS-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV9]](s32), [[UV10]](s32)
- ; GFX9PLUS-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV11]](s32), [[UV12]](s32)
- ; GFX9PLUS-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV13]](s32), [[C1]](s32)
- ; GFX9PLUS-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; GFX9PLUS-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4294967296
- ; GFX9PLUS-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
- ; GFX9PLUS-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
- ; GFX9PLUS-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
- ; GFX9PLUS-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C3]]
- ; GFX9PLUS-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[MV]]
- ; GFX9PLUS-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[MV1]]
- ; GFX9PLUS-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[AND2]], [[MV2]]
- ; GFX9PLUS-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[AND3]], [[MV3]]
- ; GFX9PLUS-NEXT: [[MV4:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[OR]](s64), [[OR1]](s64), [[OR2]](s64), [[OR3]](s64)
- ; GFX9PLUS-NEXT: [[COPY1:%[0-9]+]]:_(s256) = COPY [[MV4]](s256)
- ; GFX9PLUS-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[COPY1]](s256)
+ ; GFX9PLUS-NEXT: [[MV:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[UV7]](s32), [[UV8]](s32), [[UV9]](s32), [[UV10]](s32), [[UV11]](s32), [[UV12]](s32), [[UV13]](s32), [[DEF]](s32)
+ ; GFX9PLUS-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[MV]](s256)
;
; GFX11PLUS-LABEL: name: test_load_flat_s224_align4
; GFX11PLUS: liveins: $vgpr0_vgpr1
@@ -2522,26 +2474,10 @@ body: |
; GFX11PLUS-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD1]](<3 x s32>)
; GFX11PLUS-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<7 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32), [[UV4]](s32), [[UV5]](s32), [[UV6]](s32)
; GFX11PLUS-NEXT: [[BITCAST:%[0-9]+]]:_(s224) = G_BITCAST [[BUILD_VECTOR]](<7 x s32>)
- ; GFX11PLUS-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+ ; GFX11PLUS-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; GFX11PLUS-NEXT: [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BITCAST]](s224)
- ; GFX11PLUS-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; GFX11PLUS-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV7]](s32), [[UV8]](s32)
- ; GFX11PLUS-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV9]](s32), [[UV10]](s32)
- ; GFX11PLUS-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV11]](s32), [[UV12]](s32)
- ; GFX11PLUS-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV13]](s32), [[C1]](s32)
- ; GFX11PLUS-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; GFX11PLUS-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4294967296
- ; GFX11PLUS-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
- ; GFX11PLUS-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
- ; GFX11PLUS-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
- ; GFX11PLUS-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C3]]
- ; GFX11PLUS-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[MV]]
- ; GFX11PLUS-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[MV1]]
- ; GFX11PLUS-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[AND2]], [[MV2]]
- ; GFX11PLUS-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[AND3]], [[MV3]]
- ; GFX11PLUS-NEXT: [[MV4:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[OR]](s64), [[OR1]](s64), [[OR2]](s64), [[OR3]](s64)
- ; GFX11PLUS-NEXT: [[COPY1:%[0-9]+]]:_(s256) = COPY [[MV4]](s256)
- ; GFX11PLUS-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[COPY1]](s256)
+ ; GFX11PLUS-NEXT: [[MV:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[UV7]](s32), [[UV8]](s32), [[UV9]](s32), [[UV10]](s32), [[UV11]](s32), [[UV12]](s32), [[UV13]](s32), [[DEF]](s32)
+ ; GFX11PLUS-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[MV]](s256)
;
; GFX12-LABEL: name: test_load_flat_s224_align4
; GFX12: liveins: $vgpr0_vgpr1
@@ -2555,26 +2491,10 @@ body: |
; GFX12-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD1]](<3 x s32>)
; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<7 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32), [[UV4]](s32), [[UV5]](s32), [[UV6]](s32)
; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(s224) = G_BITCAST [[BUILD_VECTOR]](<7 x s32>)
- ; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+ ; GFX12-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; GFX12-NEXT: [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BITCAST]](s224)
- ; GFX12-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; GFX12-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV7]](s32), [[UV8]](s32)
- ; GFX12-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV9]](s32), [[UV10]](s32)
- ; GFX12-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV11]](s32), [[UV12]](s32)
- ; GFX12-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV13]](s32), [[C1]](s32)
- ; GFX12-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; GFX12-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4294967296
- ; GFX12-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
- ; GFX12-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
- ; GFX12-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
- ; GFX12-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C3]]
- ; GFX12-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[MV]]
- ; GFX12-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[MV1]]
- ; GFX12-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[AND2]], [[MV2]]
- ; GFX12-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[AND3]], [[MV3]]
- ; GFX12-NEXT: [[MV4:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[OR]](s64), [[OR1]](s64), [[OR2]](s64), [[OR3]](s64)
- ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(s256) = COPY [[MV4]](s256)
- ; GFX12-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[COPY1]](s256)
+ ; GFX12-NEXT: [[MV:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[UV7]](s32), [[UV8]](s32), [[UV9]](s32), [[UV10]](s32), [[UV11]](s32), [[UV12]](s32), [[UV13]](s32), [[DEF]](s32)
+ ; GFX12-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[MV]](s256)
;
; UNALIGNED_GFX9PLUS-LABEL: name: test_load_flat_s224_align4
; UNALIGNED_GFX9PLUS: liveins: $vgpr0_vgpr1
@@ -2588,26 +2508,10 @@ body: |
; UNALIGNED_GFX9PLUS-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD1]](<3 x s32>)
; UNALIGNED_GFX9PLUS-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<7 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32), [[UV4]](s32), [[UV5]](s32), [[UV6]](s32)
; UNALIGNED_GFX9PLUS-NEXT: [[BITCAST:%[0-9]+]]:_(s224) = G_BITCAST [[BUILD_VECTOR]](<7 x s32>)
- ; UNALIGNED_GFX9PLUS-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+ ; UNALIGNED_GFX9PLUS-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; UNALIGNED_GFX9PLUS-NEXT: [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BITCAST]](s224)
- ; UNALIGNED_GFX9PLUS-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; UNALIGNED_GFX9PLUS-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV7]](s32), [[UV8]](s32)
- ; UNALIGNED_GFX9PLUS-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV9]](s32), [[UV10]](s32)
- ; UNALIGNED_GFX9PLUS-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV11]](s32), [[UV12]](s32)
- ; UNALIGNED_GFX9PLUS-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV13]](s32), [[C1]](s32)
- ; UNALIGNED_GFX9PLUS-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; UNALIGNED_GFX9PLUS-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4294967296
- ; UNALIGNED_GFX9PLUS-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
- ; UNALIGNED_GFX9PLUS-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
- ; UNALIGNED_GFX9PLUS-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
- ; UNALIGNED_GFX9PLUS-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C3]]
- ; UNALIGNED_GFX9PLUS-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[MV]]
- ; UNALIGNED_GFX9PLUS-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[MV1]]
- ; UNALIGNED_GFX9PLUS-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[AND2]], [[MV2]]
- ; UNALIGNED_GFX9PLUS-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[AND3]], [[MV3]]
- ; UNALIGNED_GFX9PLUS-NEXT: [[MV4:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[OR]](s64), [[OR1]](s64), [[OR2]](s64), [[OR3]](s64)
- ; UNALIGNED_GFX9PLUS-NEXT: [[COPY1:%[0-9]+]]:_(s256) = COPY [[MV4]](s256)
- ; UNALIGNED_GFX9PLUS-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[COPY1]](s256)
+ ; UNALIGNED_GFX9PLUS-NEXT: [[MV:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[UV7]](s32), [[UV8]](s32), [[UV9]](s32), [[UV10]](s32), [[UV11]](s32), [[UV12]](s32), [[UV13]](s32), [[DEF]](s32)
+ ; UNALIGNED_GFX9PLUS-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[MV]](s256)
;
; UNALIGNED_GFX11PLUS-LABEL: name: test_load_flat_s224_align4
; UNALIGNED_GFX11PLUS: liveins: $vgpr0_vgpr1
@@ -2621,26 +2525,10 @@ body: |
; UNALIGNED_GFX11PLUS-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD1]](<3 x s32>)
; UNALIGNED_GFX11PLUS-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<7 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32), [[UV4]](s32), [[UV5]](s32), [[UV6]](s32)
; UNALIGNED_GFX11PLUS-NEXT: [[BITCAST:%[0-9]+]]:_(s224) = G_BITCAST [[BUILD_VECTOR]](<7 x s32>)
- ; UNALIGNED_GFX11PLUS-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+ ; UNALIGNED_GFX11PLUS-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; UNALIGNED_GFX11PLUS-NEXT: [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BITCAST]](s224)
- ; UNALIGNED_GFX11PLUS-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; UNALIGNED_GFX11PLUS-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV7]](s32), [[UV8]](s32)
- ; UNALIGNED_GFX11PLUS-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV9]](s32), [[UV10]](s32)
- ; UNALIGNED_GFX11PLUS-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV11]](s32), [[UV12]](s32)
- ; UNALIGNED_GFX11PLUS-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV13]](s32), [[C1]](s32)
- ; UNALIGNED_GFX11PLUS-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; UNALIGNED_GFX11PLUS-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4294967296
- ; UNALIGNED_GFX11PLUS-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
- ; UNALIGNED_GFX11PLUS-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
- ; UNALIGNED_GFX11PLUS-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
- ; UNALIGNED_GFX11PLUS-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C3]]
- ; UNALIGNED_GFX11PLUS-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[MV]]
- ; UNALIGNED_GFX11PLUS-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[MV1]]
- ; UNALIGNED_GFX11PLUS-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[AND2]], [[MV2]]
- ; UNALIGNED_GFX11PLUS-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[AND3]], [[MV3]]
- ; UNALIGNED_GFX11PLUS-NEXT: [[MV4:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[OR]](s64), [[OR1]](s64), [[OR2]](s64), [[OR3]](s64)
- ; UNALIGNED_GFX11PLUS-NEXT: [[COPY1:%[0-9]+]]:_(s256) = COPY [[MV4]](s256)
- ; UNALIGNED_GFX11PLUS-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[COPY1]](s256)
+ ; UNALIGNED_GFX11PLUS-NEXT: [[MV:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[UV7]](s32), [[UV8]](s32), [[UV9]](s32), [[UV10]](s32), [[UV11]](s32), [[UV12]](s32), [[UV13]](s32), [[DEF]](s32)
+ ; UNALIGNED_GFX11PLUS-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[MV]](s256)
;
; UNALIGNED_GFX12-LABEL: name: test_load_flat_s224_align4
; UNALIGNED_GFX12: liveins: $vgpr0_vgpr1
@@ -2654,26 +2542,10 @@ body: |
; UNALIGNED_GFX12-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD1]](<3 x s32>)
; UNALIGNED_GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<7 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32), [[UV4]](s32), [[UV5]](s32), [[UV6]](s32)
; UNALIGNED_GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(s224) = G_BITCAST [[BUILD_VECTOR]](<7 x s32>)
- ; UNALIGNED_GFX12-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+ ; UNALIGNED_GFX12-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; UNALIGNED_GFX12-NEXT: [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BITCAST]](s224)
- ; UNALIGNED_GFX12-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; UNALIGNED_GFX12-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV7]](s32), [[UV8]](s32)
- ; UNALIGNED_GFX12-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV9]](s32), [[UV10]](s32)
- ; UNALIGNED_GFX12-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV11]](s32), [[UV12]](s32)
- ; UNALIGNED_GFX12-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV13]](s32), [[C1]](s32)
- ; UNALIGNED_GFX12-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; UNALIGNED_GFX12-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4294967296
- ; UNALIGNED_GFX12-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
- ; UNALIGNED_GFX12-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
- ; UNALIGNED_GFX12-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
- ; UNALIGNED_GFX12-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C3]]
- ; UNALIGNED_GFX12-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[MV]]
- ; UNALIGNED_GFX12-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[MV1]]
- ; UNALIGNED_GFX12-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[AND2]], [[MV2]]
- ; UNALIGNED_GFX12-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[AND3]], [[MV3]]
- ; UNALIGNED_GFX12-NEXT: [[MV4:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[OR]](s64), [[OR1]](s64), [[OR2]](s64), [[OR3]](s64)
- ; UNALIGNED_GFX12-NEXT: [[COPY1:%[0-9]+]]:_(s256) = COPY [[MV4]](s256)
- ; UNALIGNED_GFX12-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[COPY1]](s256)
+ ; UNALIGNED_GFX12-NEXT: [[MV:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[UV7]](s32), [[UV8]](s32), [[UV9]](s32), [[UV10]](s32), [[UV11]](s32), [[UV12]](s32), [[UV13]](s32), [[DEF]](s32)
+ ; UNALIGNED_GFX12-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[MV]](s256)
%0:_(p0) = COPY $vgpr0_vgpr1
%1:_(s224) = G_LOAD %0 :: (load (s224), align 4, addrspace 0)
%2:_(s256) = G_IMPLICIT_DEF
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
index 0de6656756d2a..ea6832d417b84 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
@@ -2170,26 +2170,10 @@ body: |
; SI-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](<4 x s32>)
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<7 x s32>) = G_BUILD_VECTOR [[UV2]](s32), [[UV3]](s32), [[UV4]](s32), [[UV5]](s32), [[UV]](s32), [[UV1]](s32), [[LOAD2]](s32)
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(s224) = G_BITCAST [[BUILD_VECTOR]](<7 x s32>)
- ; SI-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+ ; SI-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; SI-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BITCAST]](s224)
- ; SI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; SI-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV6]](s32), [[UV7]](s32)
- ; SI-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV8]](s32), [[UV9]](s32)
- ; SI-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV10]](s32), [[UV11]](s32)
- ; SI-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV12]](s32), [[C2]](s32)
- ; SI-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; SI-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4294967296
- ; SI-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C3]]
- ; SI-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C3]]
- ; SI-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C3]]
- ; SI-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C4]]
- ; SI-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[MV]]
- ; SI-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[MV1]]
- ; SI-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[AND2]], [[MV2]]
- ; SI-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[AND3]], [[MV3]]
- ; SI-NEXT: [[MV4:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[OR]](s64), [[OR1]](s64), [[OR2]](s64), [[OR3]](s64)
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(s256) = COPY [[MV4]](s256)
- ; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[COPY1]](s256)
+ ; SI-NEXT: [[MV:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[UV6]](s32), [[UV7]](s32), [[UV8]](s32), [[UV9]](s32), [[UV10]](s32), [[UV11]](s32), [[UV12]](s32), [[DEF]](s32)
+ ; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[MV]](s256)
;
; CI-HSA-LABEL: name: test_load_global_s224_align4
; CI-HSA: liveins: $vgpr0_vgpr1
@@ -2203,26 +2187,10 @@ body: |
; CI-HSA-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD1]](<3 x s32>)
; CI-HSA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<7 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32), [[UV4]](s32), [[UV5]](s32), [[UV6]](s32)
; CI-HSA-NEXT: [[BITCAST:%[0-9]+]]:_(s224) = G_BITCAST [[BUILD_VECTOR]](<7 x s32>)
- ; CI-HSA-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+ ; CI-HSA-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CI-HSA-NEXT: [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BITCAST]](s224)
- ; CI-HSA-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CI-HSA-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV7]](s32), [[UV8]](s32)
- ; CI-HSA-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV9]](s32), [[UV10]](s32)
- ; CI-HSA-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV11]](s32), [[UV12]](s32)
- ; CI-HSA-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV13]](s32), [[C1]](s32)
- ; CI-HSA-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CI-HSA-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4294967296
- ; CI-HSA-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
- ; CI-HSA-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
- ; CI-HSA-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
- ; CI-HSA-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C3]]
- ; CI-HSA-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[MV]]
- ; CI-HSA-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[MV1]]
- ; CI-HSA-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[AND2]], [[MV2]]
- ; CI-HSA-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[AND3]], [[MV3]]
- ; CI-HSA-NEXT: [[MV4:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[OR]](s64), [[OR1]](s64), [[OR2]](s64), [[OR3]](s64)
- ; CI-HSA-NEXT: [[COPY1:%[0-9]+]]:_(s256) = COPY [[MV4]](s256)
- ; CI-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[COPY1]](s256)
+ ; CI-HSA-NEXT: [[MV:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[UV7]](s32), [[UV8]](s32), [[UV9]](s32), [[UV10]](s32), [[UV11]](s32), [[UV12]](s32), [[UV13]](s32), [[DEF]](s32)
+ ; CI-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[MV]](s256)
;
; CI-MESA-LABEL: name: test_load_global_s224_align4
; CI-MESA: liveins: $vgpr0_vgpr1
@@ -2236,26 +2204,10 @@ body: |
; CI-MESA-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD1]](<3 x s32>)
; CI-MESA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<7 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32), [[UV4]](s32), [[UV5]](s32), [[UV6]](s32)
; CI-MESA-NEXT: [[BITCAST:%[0-9]+]]:_(s224) = G_BITCAST [[BUILD_VECTOR]](<7 x s32>)
- ; CI-MESA-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+ ; CI-MESA-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CI-MESA-NEXT: [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BITCAST]](s224)
- ; CI-MESA-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CI-MESA-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV7]](s32), [[UV8]](s32)
- ; CI-MESA-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV9]](s32), [[UV10]](s32)
- ; CI-MESA-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV11]](s32), [[UV12]](s32)
- ; CI-MESA-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV13]](s32), [[C1]](s32)
- ; CI-MESA-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CI-MESA-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4294967296
- ; CI-MESA-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
- ; CI-MESA-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
- ; CI-MESA-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
- ; CI-MESA-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C3]]
- ; CI-MESA-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[MV]]
- ; CI-MESA-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[MV1]]
- ; CI-MESA-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[AND2]], [[MV2]]
- ; CI-MESA-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[AND3]], [[MV3]]
- ; CI-MESA-NEXT: [[MV4:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[OR]](s64), [[OR1]](s64), [[OR2]](s64), [[OR3]](s64)
- ; CI-MESA-NEXT: [[COPY1:%[0-9]+]]:_(s256) = COPY [[MV4]](s256)
- ; CI-MESA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[COPY1]](s256)
+ ; CI-MESA-NEXT: [[MV:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[UV7]](s32), [[UV8]](s32), [[UV9]](s32), [[UV10]](s32), [[UV11]](s32), [[UV12]](s32), [[UV13]](s32), [[DEF]](s32)
+ ; CI-MESA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[MV]](s256)
;
; VI-LABEL: name: test_load_global_s224_align4
; VI: liveins: $vgpr0_vgpr1
@@ -2269,26 +2221,10 @@ body: |
; VI-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD1]](<3 x s32>)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<7 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32), [[UV4]](s32), [[UV5]](s32), [[UV6]](s32)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(s224) = G_BITCAST [[BUILD_VECTOR]](<7 x s32>)
- ; VI-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+ ; VI-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; VI-NEXT: [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BITCAST]](s224)
- ; VI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; VI-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV7]](s32), [[UV8]](s32)
- ; VI-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV9]](s32), [[UV10]](s32)
- ; VI-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV11]](s32), [[UV12]](s32)
- ; VI-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV13]](s32), [[C1]](s32)
- ; VI-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; VI-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4294967296
- ; VI-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
- ; VI-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
- ; VI-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
- ; VI-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C3]]
- ; VI-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[MV]]
- ; VI-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[MV1]]
- ; VI-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[AND2]], [[MV2]]
- ; VI-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[AND3]], [[MV3]]
- ; VI-NEXT: [[MV4:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[OR]](s64), [[OR1]](s64), [[OR2]](s64), [[OR3]](s64)
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(s256) = COPY [[MV4]](s256)
- ; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[COPY1]](s256)
+ ; VI-NEXT: [[MV:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[UV7]](s32), [[UV8]](s32), [[UV9]](s32), [[UV10]](s32), [[UV11]](s32), [[UV12]](s32), [[UV13]](s32), [[DEF]](s32)
+ ; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[MV]](s256)
;
; GFX9-HSA-LABEL: name: test_load_global_s224_align4
; GFX9-HSA: liveins: $vgpr0_vgpr1
@@ -2302,26 +2238,10 @@ body: |
; GFX9-HSA-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD1]](<3 x s32>)
; GFX9-HSA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<7 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32), [[UV4]](s32), [[UV5]](s32), [[UV6]](s32)
; GFX9-HSA-NEXT: [[BITCAST:%[0-9]+]]:_(s224) = G_BITCAST [[BUILD_VECTOR]](<7 x s32>)
- ; GFX9-HSA-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+ ; GFX9-HSA-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; GFX9-HSA-NEXT: [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BITCAST]](s224)
- ; GFX9-HSA-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; GFX9-HSA-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV7]](s32), [[UV8]](s32)
- ; GFX9-HSA-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV9]](s32), [[UV10]](s32)
- ; GFX9-HSA-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV11]](s32), [[UV12]](s32)
- ; GFX9-HSA-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV13]](s32), [[C1]](s32)
- ; GFX9-HSA-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; GFX9-HSA-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4294967296
- ; GFX9-HSA-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
- ; GFX9-HSA-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
- ; GFX9-HSA-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
- ; GFX9-HSA-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C3]]
- ; GFX9-HSA-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[MV]]
- ; GFX9-HSA-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[MV1]]
- ; GFX9-HSA-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[AND2]], [[MV2]]
- ; GFX9-HSA-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[AND3]], [[MV3]]
- ; GFX9-HSA-NEXT: [[MV4:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[OR]](s64), [[OR1]](s64), [[OR2]](s64), [[OR3]](s64)
- ; GFX9-HSA-NEXT: [[COPY1:%[0-9]+]]:_(s256) = COPY [[MV4]](s256)
- ; GFX9-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[COPY1]](s256)
+ ; GFX9-HSA-NEXT: [[MV:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[UV7]](s32), [[UV8]](s32), [[UV9]](s32), [[UV10]](s32), [[UV11]](s32), [[UV12]](s32), [[UV13]](s32), [[DEF]](s32)
+ ; GFX9-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[MV]](s256)
;
; GFX9-MESA-LABEL: name: test_load_global_s224_align4
; GFX9-MESA: liveins: $vgpr0_vgpr1
@@ -2335,26 +2255,10 @@ body: |
; GFX9-MESA-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD1]](<3 x s32>)
; GFX9-MESA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<7 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32), [[UV4]](s32), [[UV5]](s32), [[UV6]](s32)
; GFX9-MESA-NEXT: [[BITCAST:%[0-9]+]]:_(s224) = G_BITCAST [[BUILD_VECTOR]](<7 x s32>)
- ; GFX9-MESA-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+ ; GFX9-MESA-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; GFX9-MESA-NEXT: [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BITCAST]](s224)
- ; GFX9-MESA-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; GFX9-MESA-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV7]](s32), [[UV8]](s32)
- ; GFX9-MESA-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV9]](s32), [[UV10]](s32)
- ; GFX9-MESA-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV11]](s32), [[UV12]](s32)
- ; GFX9-MESA-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV13]](s32), [[C1]](s32)
- ; GFX9-MESA-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; GFX9-MESA-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4294967296
- ; GFX9-MESA-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
- ; GFX9-MESA-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
- ; GFX9-MESA-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
- ; GFX9-MESA-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C3]]
- ; GFX9-MESA-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[MV]]
- ; GFX9-MESA-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[MV1]]
- ; GFX9-MESA-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[AND2]], [[MV2]]
- ; GFX9-MESA-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[AND3]], [[MV3]]
- ; GFX9-MESA-NEXT: [[MV4:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[OR]](s64), [[OR1]](s64), [[OR2]](s64), [[OR3]](s64)
- ; GFX9-MESA-NEXT: [[COPY1:%[0-9]+]]:_(s256) = COPY [[MV4]](s256)
- ; GFX9-MESA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[COPY1]](s256)
+ ; GFX9-MESA-NEXT: [[MV:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[UV7]](s32), [[UV8]](s32), [[UV9]](s32), [[UV10]](s32), [[UV11]](s32), [[UV12]](s32), [[UV13]](s32), [[DEF]](s32)
+ ; GFX9-MESA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[MV]](s256)
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s224) = G_LOAD %0 :: (load (s224), align 4, addrspace 1)
%2:_(s256) = G_IMPLICIT_DEF
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
index bef6e69de07bd..2545b452d2a89 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
@@ -148,17 +148,15 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s96) = COPY $vgpr0_vgpr1_vgpr2
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s96) = COPY $vgpr3_vgpr4_vgpr5
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s96)
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96)
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
- ; CHECK-NEXT: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96)
- ; CHECK-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s96)
- ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV6]](s32), [[UV7]](s32)
- ; CHECK-NEXT: [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s96)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[MV]], [[MV1]]
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[UV5]], [[UV11]]
- ; CHECK-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[OR]](s64)
- ; CHECK-NEXT: [[MV2:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[UV12]](s32), [[UV13]](s32), [[OR1]](s32)
- ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[MV2]](s96)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s64) = G_TRUNC [[COPY1]](s96)
+ ; CHECK-NEXT: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s96)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[TRUNC]], [[TRUNC1]]
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[UV2]], [[UV5]]
+ ; CHECK-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[OR]](s64)
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[UV6]](s32), [[UV7]](s32), [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[MV]](s96)
%0:_(s96) = COPY $vgpr0_vgpr1_vgpr2
%1:_(s96) = COPY $vgpr3_vgpr4_vgpr5
%2:_(s96) = G_OR %0, %1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir
index eace05a17adc7..bb3258d04f589 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir
@@ -177,17 +177,15 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr6
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY2]](s32), [[C]]
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s96)
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96)
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
- ; CHECK-NEXT: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96)
- ; CHECK-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s96)
- ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV6]](s32), [[UV7]](s32)
- ; CHECK-NEXT: [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s96)
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[MV]], [[MV1]]
- ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[UV5]], [[UV11]]
- ; CHECK-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SELECT]](s64)
- ; CHECK-NEXT: [[MV2:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[UV12]](s32), [[UV13]](s32), [[SELECT1]](s32)
- ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[MV2]](s96)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s64) = G_TRUNC [[COPY1]](s96)
+ ; CHECK-NEXT: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s96)
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[TRUNC]], [[TRUNC1]]
+ ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[UV2]], [[UV5]]
+ ; CHECK-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SELECT]](s64)
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[UV6]](s32), [[UV7]](s32), [[SELECT1]](s32)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[MV]](s96)
%0:_(s96) = COPY $vgpr0_vgpr1_vgpr2
%1:_(s96) = COPY $vgpr3_vgpr4_vgpr5
%2:_(s32) = COPY $vgpr6
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir
index 41f32964c55ff..e2446fe4b03f6 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir
@@ -148,17 +148,15 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s96) = COPY $vgpr0_vgpr1_vgpr2
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s96) = COPY $vgpr3_vgpr4_vgpr5
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s96)
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96)
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
- ; CHECK-NEXT: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96)
- ; CHECK-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s96)
- ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV6]](s32), [[UV7]](s32)
- ; CHECK-NEXT: [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s96)
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[MV]], [[MV1]]
- ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[UV5]], [[UV11]]
- ; CHECK-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64)
- ; CHECK-NEXT: [[MV2:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[UV12]](s32), [[UV13]](s32), [[XOR1]](s32)
- ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[MV2]](s96)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s64) = G_TRUNC [[COPY1]](s96)
+ ; CHECK-NEXT: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s96)
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[TRUNC]], [[TRUNC1]]
+ ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[UV2]], [[UV5]]
+ ; CHECK-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64)
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[UV6]](s32), [[UV7]](s32), [[XOR1]](s32)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[MV]](s96)
%0:_(s96) = COPY $vgpr0_vgpr1_vgpr2
%1:_(s96) = COPY $vgpr3_vgpr4_vgpr5
%2:_(s96) = G_XOR %0, %1
>From cee0adc1986c0f0e6f8f7ac277ba221097d6901c Mon Sep 17 00:00:00 2001
From: Vang Thao <vang.thao at amd.com>
Date: Mon, 9 Mar 2026 09:14:49 -0700
Subject: [PATCH 6/6] Reorder lowering calls, restore test.
---
.../lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 22 +-
.../AMDGPU/GlobalISel/inst-select-extract.mir | 199 +++++++
.../AMDGPU/GlobalISel/inst-select-insert.mir | 506 ++++++++++++++++++
.../AMDGPU/GlobalISel/legalize-and.mir | 18 +-
.../AMDGPU/GlobalISel/legalize-extract.mir | 4 +-
.../GlobalISel/legalize-implicit-def.mir | 5 +-
.../AMDGPU/GlobalISel/legalize-insert.mir | 10 +-
.../CodeGen/AMDGPU/GlobalISel/legalize-or.mir | 18 +-
.../AMDGPU/GlobalISel/legalize-select.mir | 18 +-
.../AMDGPU/GlobalISel/legalize-xor.mir | 18 +-
.../GlobalISel/regbankselect-extract.mir | 85 +++
.../GlobalISel/regbankselect-insert.mir | 187 +++++++
.../GlobalISel/LegalizerHelperTest.cpp | 6 +-
13 files changed, 1037 insertions(+), 59 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extract.mir
create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert.mir
create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract.mir
create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert.mir
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index 5756c046b4028..a0a9a13c9f7e4 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -1942,18 +1942,6 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
unsigned BigTyIdx = Op == G_EXTRACT ? 1 : 0;
unsigned LitTyIdx = Op == G_EXTRACT ? 0 : 1;
getActionDefinitionsBuilder(Op)
- .lowerIf([=](const LegalityQuery &Query) {
- return Query.Types[BigTyIdx].isVector();
- })
- .customIf([=](const LegalityQuery &Query) {
- // Generic lower is not aware of subregs and can produce inefficient
- // shift+trunc/mask sequences. We can instead use custom lowering
- // for simple 32-bit aligned cases and use unmerge/merge.
- const LLT BigTy = Query.Types[BigTyIdx];
- const LLT LitTy = Query.Types[LitTyIdx];
- return BigTy.getSizeInBits() % 32 == 0 &&
- LitTy.getSizeInBits() % 32 == 0;
- })
.widenScalarIf(
[=](const LegalityQuery &Query) {
const LLT BigTy = Query.Types[BigTyIdx];
@@ -1968,6 +1956,16 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
LegalizeMutations::widenScalarOrEltToNextPow2(LitTyIdx, 16))
.moreElementsIf(isSmallOddVector(BigTyIdx), oneMoreElement(BigTyIdx))
.widenScalarToNextPow2(BigTyIdx, 32)
+ .customIf([=](const LegalityQuery &Query) {
+ // Generic lower is not aware of subregs and can produce inefficient
+ // shift+trunc/mask sequences. We can instead use custom lowering
+ // for simple 32-bit aligned cases and use unmerge/merge.
+ const LLT BigTy = Query.Types[BigTyIdx];
+ const LLT LitTy = Query.Types[LitTyIdx];
+ return !BigTy.isVector() &&
+ BigTy.getSizeInBits() % 32 == 0 &&
+ LitTy.getSizeInBits() % 32 == 0;
+ })
.lower();
}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extract.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extract.mir
new file mode 100644
index 0000000000000..b8ef754d5de5e
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extract.mir
@@ -0,0 +1,199 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s
+---
+name: extract512
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: extract512
+ ; CHECK: [[DEF:%[0-9]+]]:sgpr_512 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub7
+ ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub8
+ ; CHECK-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub9
+ ; CHECK-NEXT: [[COPY10:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub10
+ ; CHECK-NEXT: [[COPY11:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub11
+ ; CHECK-NEXT: [[COPY12:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub12
+ ; CHECK-NEXT: [[COPY13:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub13
+ ; CHECK-NEXT: [[COPY14:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub14
+ ; CHECK-NEXT: [[COPY15:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub15
+ ; CHECK-NEXT: $sgpr0 = COPY [[COPY]]
+ ; CHECK-NEXT: $sgpr1 = COPY [[COPY1]]
+ ; CHECK-NEXT: $sgpr2 = COPY [[COPY2]]
+ ; CHECK-NEXT: $sgpr3 = COPY [[COPY3]]
+ ; CHECK-NEXT: $sgpr4 = COPY [[COPY4]]
+ ; CHECK-NEXT: $sgpr5 = COPY [[COPY5]]
+ ; CHECK-NEXT: $sgpr6 = COPY [[COPY6]]
+ ; CHECK-NEXT: $sgpr7 = COPY [[COPY7]]
+ ; CHECK-NEXT: $sgpr8 = COPY [[COPY8]]
+ ; CHECK-NEXT: $sgpr9 = COPY [[COPY9]]
+ ; CHECK-NEXT: $sgpr10 = COPY [[COPY10]]
+ ; CHECK-NEXT: $sgpr11 = COPY [[COPY11]]
+ ; CHECK-NEXT: $sgpr12 = COPY [[COPY12]]
+ ; CHECK-NEXT: $sgpr13 = COPY [[COPY13]]
+ ; CHECK-NEXT: $sgpr14 = COPY [[COPY14]]
+ ; CHECK-NEXT: $sgpr15 = COPY [[COPY15]]
+ ; CHECK-NEXT: SI_RETURN_TO_EPILOG $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $sgpr14, $sgpr15
+ %0:sgpr(s512) = G_IMPLICIT_DEF
+ %1:sgpr(s32) = G_EXTRACT %0:sgpr(s512), 0
+ %2:sgpr(s32) = G_EXTRACT %0:sgpr(s512), 32
+ %3:sgpr(s32) = G_EXTRACT %0:sgpr(s512), 64
+ %4:sgpr(s32) = G_EXTRACT %0:sgpr(s512), 96
+ %5:sgpr(s32) = G_EXTRACT %0:sgpr(s512), 128
+ %6:sgpr(s32) = G_EXTRACT %0:sgpr(s512), 160
+ %7:sgpr(s32) = G_EXTRACT %0:sgpr(s512), 192
+ %8:sgpr(s32) = G_EXTRACT %0:sgpr(s512), 224
+ %9:sgpr(s32) = G_EXTRACT %0:sgpr(s512), 256
+ %10:sgpr(s32) = G_EXTRACT %0:sgpr(s512), 288
+ %11:sgpr(s32) = G_EXTRACT %0:sgpr(s512), 320
+ %12:sgpr(s32) = G_EXTRACT %0:sgpr(s512), 352
+ %13:sgpr(s32) = G_EXTRACT %0:sgpr(s512), 384
+ %14:sgpr(s32) = G_EXTRACT %0:sgpr(s512), 416
+ %15:sgpr(s32) = G_EXTRACT %0:sgpr(s512), 448
+ %16:sgpr(s32) = G_EXTRACT %0:sgpr(s512), 480
+ $sgpr0 = COPY %1:sgpr(s32)
+ $sgpr1 = COPY %2:sgpr(s32)
+ $sgpr2 = COPY %3:sgpr(s32)
+ $sgpr3 = COPY %4:sgpr(s32)
+ $sgpr4 = COPY %5:sgpr(s32)
+ $sgpr5 = COPY %6:sgpr(s32)
+ $sgpr6 = COPY %7:sgpr(s32)
+ $sgpr7 = COPY %8:sgpr(s32)
+ $sgpr8 = COPY %9:sgpr(s32)
+ $sgpr9 = COPY %10:sgpr(s32)
+ $sgpr10 = COPY %11:sgpr(s32)
+ $sgpr11 = COPY %12:sgpr(s32)
+ $sgpr12 = COPY %13:sgpr(s32)
+ $sgpr13 = COPY %14:sgpr(s32)
+ $sgpr14 = COPY %15:sgpr(s32)
+ $sgpr15 = COPY %16:sgpr(s32)
+ SI_RETURN_TO_EPILOG $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $sgpr14, $sgpr15
+...
+
+---
+name: extract_s_s32_s1024
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: extract_s_s32_s1024
+ ; CHECK: [[DEF:%[0-9]+]]:sgpr_1024 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub7
+ ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub8
+ ; CHECK-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub9
+ ; CHECK-NEXT: [[COPY10:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub10
+ ; CHECK-NEXT: [[COPY11:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub11
+ ; CHECK-NEXT: [[COPY12:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub12
+ ; CHECK-NEXT: [[COPY13:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub13
+ ; CHECK-NEXT: [[COPY14:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub14
+ ; CHECK-NEXT: [[COPY15:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub15
+ ; CHECK-NEXT: [[COPY16:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub16
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub17
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub18
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub19
+ ; CHECK-NEXT: [[COPY20:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub20
+ ; CHECK-NEXT: [[COPY21:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub21
+ ; CHECK-NEXT: [[COPY22:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub22
+ ; CHECK-NEXT: [[COPY23:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub23
+ ; CHECK-NEXT: [[COPY24:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub24
+ ; CHECK-NEXT: [[COPY25:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub25
+ ; CHECK-NEXT: [[COPY26:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub26
+ ; CHECK-NEXT: [[COPY27:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub27
+ ; CHECK-NEXT: [[COPY28:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub28
+ ; CHECK-NEXT: [[COPY29:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub29
+ ; CHECK-NEXT: [[COPY30:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub30
+ ; CHECK-NEXT: [[COPY31:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub31
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[DEF]], implicit [[COPY]], implicit [[COPY1]], implicit [[COPY2]], implicit [[COPY3]], implicit [[COPY4]], implicit [[COPY5]], implicit [[COPY6]], implicit [[COPY7]], implicit [[COPY8]], implicit [[COPY9]], implicit [[COPY10]], implicit [[COPY11]], implicit [[COPY12]], implicit [[COPY13]], implicit [[COPY14]], implicit [[COPY15]], implicit [[COPY16]], implicit [[COPY17]], implicit [[COPY18]], implicit [[COPY19]], implicit [[COPY20]], implicit [[COPY21]], implicit [[COPY22]], implicit [[COPY23]], implicit [[COPY24]], implicit [[COPY25]], implicit [[COPY26]], implicit [[COPY27]], implicit [[COPY28]], implicit [[COPY29]], implicit [[COPY30]], implicit [[COPY31]]
+ %0:sgpr(s1024) = G_IMPLICIT_DEF
+ %1:sgpr(s32) = G_EXTRACT %0:sgpr, 0
+ %2:sgpr(s32) = G_EXTRACT %0:sgpr, 32
+ %3:sgpr(s32) = G_EXTRACT %0:sgpr, 64
+ %4:sgpr(s32) = G_EXTRACT %0:sgpr, 96
+ %5:sgpr(s32) = G_EXTRACT %0:sgpr, 128
+ %6:sgpr(s32) = G_EXTRACT %0:sgpr, 160
+ %7:sgpr(s32) = G_EXTRACT %0:sgpr, 192
+ %8:sgpr(s32) = G_EXTRACT %0:sgpr, 224
+ %9:sgpr(s32) = G_EXTRACT %0:sgpr, 256
+ %10:sgpr(s32) = G_EXTRACT %0:sgpr, 288
+ %11:sgpr(s32) = G_EXTRACT %0:sgpr, 320
+ %12:sgpr(s32) = G_EXTRACT %0:sgpr, 352
+ %13:sgpr(s32) = G_EXTRACT %0:sgpr, 384
+ %14:sgpr(s32) = G_EXTRACT %0:sgpr, 416
+ %15:sgpr(s32) = G_EXTRACT %0:sgpr, 448
+ %16:sgpr(s32) = G_EXTRACT %0:sgpr, 480
+
+ %17:sgpr(s32) = G_EXTRACT %0:sgpr, 512
+ %18:sgpr(s32) = G_EXTRACT %0:sgpr, 544
+ %19:sgpr(s32) = G_EXTRACT %0:sgpr, 576
+ %20:sgpr(s32) = G_EXTRACT %0:sgpr, 608
+ %21:sgpr(s32) = G_EXTRACT %0:sgpr, 640
+ %22:sgpr(s32) = G_EXTRACT %0:sgpr, 672
+ %23:sgpr(s32) = G_EXTRACT %0:sgpr, 704
+ %24:sgpr(s32) = G_EXTRACT %0:sgpr, 736
+ %25:sgpr(s32) = G_EXTRACT %0:sgpr, 768
+ %26:sgpr(s32) = G_EXTRACT %0:sgpr, 800
+ %27:sgpr(s32) = G_EXTRACT %0:sgpr, 832
+ %28:sgpr(s32) = G_EXTRACT %0:sgpr, 864
+ %29:sgpr(s32) = G_EXTRACT %0:sgpr, 896
+ %30:sgpr(s32) = G_EXTRACT %0:sgpr, 928
+ %31:sgpr(s32) = G_EXTRACT %0:sgpr, 960
+ %32:sgpr(s32) = G_EXTRACT %0:sgpr, 992
+
+ S_ENDPGM 0, implicit %0, implicit %1, implicit %2, implicit %3, implicit %4, implicit %5, implicit %6, implicit %7, implicit %8, implicit %9, implicit %10, implicit %11, implicit %12, implicit %13, implicit %14, implicit %15, implicit %16, implicit %17, implicit %18, implicit %19, implicit %20, implicit %21, implicit %22, implicit %23, implicit %24, implicit %25, implicit %26, implicit %27, implicit %28, implicit %29, implicit %30, implicit %31, implicit %32
+...
+
+# TODO: Handle offset 32
+---
+name: extract_sgpr_s64_from_s128
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: extract_sgpr_s64_from_s128
+ ; CHECK: [[DEF:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY [[DEF]].sub0_sub1
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY [[DEF]].sub2_sub3
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY]], implicit [[COPY1]]
+ %0:sgpr(s128) = G_IMPLICIT_DEF
+ %1:sgpr(s64) = G_EXTRACT %0, 0
+ %2:sgpr(s64) = G_EXTRACT %0, 64
+ S_ENDPGM 0, implicit %1, implicit %2
+
+...
+
+---
+name: extract_sgpr_s96_from_s128
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1_sgpr2_sgpr3
+ ; CHECK-LABEL: name: extract_sgpr_s96_from_s128
+ ; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_96 = COPY [[COPY]].sub0_sub1_sub2
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY1]]
+ %0:sgpr(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
+ %1:sgpr(s96) = G_EXTRACT %0, 0
+ S_ENDPGM 0, implicit %1
+
+...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert.mir
new file mode 100644
index 0000000000000..3602daa3017e0
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert.mir
@@ -0,0 +1,506 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+
+name: insert_s512_s32
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: insert_s512_s32
+ ; CHECK: [[DEF:%[0-9]+]]:sgpr_512 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[DEF]], [[DEF1]], %subreg.sub0
+ ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG]], [[DEF1]], %subreg.sub1
+ ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG1]], [[DEF1]], %subreg.sub2
+ ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG2]], [[DEF1]], %subreg.sub3
+ ; CHECK-NEXT: [[INSERT_SUBREG4:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG3]], [[DEF1]], %subreg.sub4
+ ; CHECK-NEXT: [[INSERT_SUBREG5:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG4]], [[DEF1]], %subreg.sub5
+ ; CHECK-NEXT: [[INSERT_SUBREG6:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG5]], [[DEF1]], %subreg.sub6
+ ; CHECK-NEXT: [[INSERT_SUBREG7:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG6]], [[DEF1]], %subreg.sub7
+ ; CHECK-NEXT: [[INSERT_SUBREG8:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG7]], [[DEF1]], %subreg.sub8
+ ; CHECK-NEXT: [[INSERT_SUBREG9:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG8]], [[DEF1]], %subreg.sub9
+ ; CHECK-NEXT: [[INSERT_SUBREG10:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG9]], [[DEF1]], %subreg.sub10
+ ; CHECK-NEXT: [[INSERT_SUBREG11:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG10]], [[DEF1]], %subreg.sub11
+ ; CHECK-NEXT: [[INSERT_SUBREG12:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG11]], [[DEF1]], %subreg.sub12
+ ; CHECK-NEXT: [[INSERT_SUBREG13:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG12]], [[DEF1]], %subreg.sub13
+ ; CHECK-NEXT: [[INSERT_SUBREG14:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG13]], [[DEF1]], %subreg.sub14
+ ; CHECK-NEXT: [[INSERT_SUBREG15:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG14]], [[DEF1]], %subreg.sub15
+ ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 = COPY [[INSERT_SUBREG15]]
+ ; CHECK-NEXT: SI_RETURN_TO_EPILOG $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
+ %0:sgpr(s512) = G_IMPLICIT_DEF
+ %1:sgpr(s32) = G_IMPLICIT_DEF
+ %2:sgpr(s512) = G_INSERT %0:sgpr, %1:sgpr(s32), 0
+ %3:sgpr(s512) = G_INSERT %2:sgpr, %1:sgpr(s32), 32
+ %4:sgpr(s512) = G_INSERT %3:sgpr, %1:sgpr(s32), 64
+ %5:sgpr(s512) = G_INSERT %4:sgpr, %1:sgpr(s32), 96
+ %6:sgpr(s512) = G_INSERT %5:sgpr, %1:sgpr(s32), 128
+ %7:sgpr(s512) = G_INSERT %6:sgpr, %1:sgpr(s32), 160
+ %8:sgpr(s512) = G_INSERT %7:sgpr, %1:sgpr(s32), 192
+ %9:sgpr(s512) = G_INSERT %8:sgpr, %1:sgpr(s32), 224
+ %10:sgpr(s512) = G_INSERT %9:sgpr, %1:sgpr(s32), 256
+ %11:sgpr(s512) = G_INSERT %10:sgpr, %1:sgpr(s32), 288
+ %12:sgpr(s512) = G_INSERT %11:sgpr, %1:sgpr(s32), 320
+ %13:sgpr(s512) = G_INSERT %12:sgpr, %1:sgpr(s32), 352
+ %14:sgpr(s512) = G_INSERT %13:sgpr, %1:sgpr(s32), 384
+ %15:sgpr(s512) = G_INSERT %14:sgpr, %1:sgpr(s32), 416
+ %16:sgpr(s512) = G_INSERT %15:sgpr, %1:sgpr(s32), 448
+ %17:sgpr(s512) = G_INSERT %16:sgpr, %1:sgpr(s32), 480
+ $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 = COPY %17:sgpr(s512)
+ SI_RETURN_TO_EPILOG $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
+...
+
+---
+
+name: insert_v_s64_v_s32_0
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2
+ ; CHECK-LABEL: name: insert_v_s64_v_s32_0
+ ; CHECK: liveins: $vgpr0_vgpr1, $vgpr2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vreg_64 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub0
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
+ %0:vgpr(s64) = COPY $vgpr0_vgpr1
+ %1:vgpr(s32) = COPY $vgpr2
+ %2:vgpr(s64) = G_INSERT %0, %1, 0
+ S_ENDPGM 0, implicit %2
+...
+
+---
+
+name: insert_v_s64_v_s32_32
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2
+ ; CHECK-LABEL: name: insert_v_s64_v_s32_32
+ ; CHECK: liveins: $vgpr0_vgpr1, $vgpr2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vreg_64 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub1
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
+ %0:vgpr(s64) = COPY $vgpr0_vgpr1
+ %1:vgpr(s32) = COPY $vgpr2
+ %2:vgpr(s64) = G_INSERT %0, %1, 32
+ S_ENDPGM 0, implicit %2
+...
+
+---
+
+name: insert_s_s64_s_s32_0
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1, $sgpr2
+ ; CHECK-LABEL: name: insert_s_s64_s_s32_0
+ ; CHECK: liveins: $sgpr0_sgpr1, $sgpr2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
+ ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:sreg_64 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub0
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
+ %0:sgpr(s64) = COPY $sgpr0_sgpr1
+ %1:sgpr(s32) = COPY $sgpr2
+ %2:sgpr(s64) = G_INSERT %0, %1, 0
+ S_ENDPGM 0, implicit %2
+...
+
+---
+
+name: insert_s_s64_s_s32_32
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1, $sgpr2
+ ; CHECK-LABEL: name: insert_s_s64_s_s32_32
+ ; CHECK: liveins: $sgpr0_sgpr1, $sgpr2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
+ ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:sreg_64 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub1
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
+ %0:sgpr(s64) = COPY $sgpr0_sgpr1
+ %1:sgpr(s32) = COPY $sgpr2
+ %2:sgpr(s64) = G_INSERT %0, %1, 32
+ S_ENDPGM 0, implicit %2
+...
+
+---
+
+name: insert_s_s64_v_s32_32
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1, $vgpr0
+ ; CHECK-LABEL: name: insert_s_s64_v_s32_32
+ ; CHECK: liveins: $sgpr0_sgpr1, $vgpr0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vreg_64 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub1
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
+ %0:sgpr(s64) = COPY $sgpr0_sgpr1
+ %1:vgpr(s32) = COPY $vgpr2
+ %2:vgpr(s64) = G_INSERT %0, %1, 32
+ S_ENDPGM 0, implicit %2
+...
+
+---
+
+name: insert_v_s64_s_s32_32
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $sgpr0
+ ; CHECK-LABEL: name: insert_v_s64_s_s32_32
+ ; CHECK: liveins: $vgpr0_vgpr1, $sgpr0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vreg_64 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub1
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
+ %0:vgpr(s64) = COPY $vgpr0_vgpr1
+ %1:sgpr(s32) = COPY $sgpr0
+ %2:vgpr(s64) = G_INSERT %0, %1, 32
+ S_ENDPGM 0, implicit %2
+...
+
+---
+
+name: insert_v_s128_v_s64_0
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5
+ ; CHECK-LABEL: name: insert_v_s128_v_s64_0
+ ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_128 = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr4_vgpr5
+ ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vreg_128 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub0_sub1
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
+ %0:vgpr(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ %1:vgpr(s64) = COPY $vgpr4_vgpr5
+ %2:vgpr(s128) = G_INSERT %0, %1, 0
+ S_ENDPGM 0, implicit %2
+...
+
+---
+
+name: insert_v_s128_v_s64_32
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5
+ ; CHECK-LABEL: name: insert_v_s128_v_s64_32
+ ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_128 = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr4_vgpr5
+ ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vreg_128 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub1_sub2
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
+ %0:vgpr(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ %1:vgpr(s64) = COPY $vgpr4_vgpr5
+ %2:vgpr(s128) = G_INSERT %0, %1, 32
+ S_ENDPGM 0, implicit %2
+...
+
+---
+
+name: insert_s_s128_s_s64_0_v2
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5
+ ; CHECK-LABEL: name: insert_s_s128_s_s64_0_v2
+ ; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5
+ ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:sgpr_128 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub0_sub1
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
+ %0:sgpr(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
+ %1:sgpr(s64) = COPY $sgpr4_sgpr5
+ %2:sgpr(s128) = G_INSERT %0, %1, 0
+ S_ENDPGM 0, implicit %2
+...
+
+---
+
+name: insert_s_s128_s_s64_0
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5
+ ; CHECK-LABEL: name: insert_s_s128_s_s64_0
+ ; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5
+ ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:sgpr_128 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub0_sub1
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
+ %0:sgpr(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
+ %1:sgpr(s64) = COPY $sgpr4_sgpr5
+ %2:sgpr(s128) = G_INSERT %0, %1, 0
+ S_ENDPGM 0, implicit %2
+...
+
+# ---
+
+# name: insert_s_s128_s_s64_32
+# legalized: true
+# regBankSelected: true
+
+# body: |
+# bb.0:
+# liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5
+# %0:sgpr(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
+# %1:sgpr(s64) = COPY $sgpr4_sgpr5
+# %2:sgpr(s128) = G_INSERT %0, %1, 32
+# S_ENDPGM 0, implicit %2
+# ...
+
+---
+
+name: insert_s_s128_s_s64_64
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5
+ ; CHECK-LABEL: name: insert_s_s128_s_s64_64
+ ; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5
+ ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:sgpr_128 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub2_sub3
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
+ %0:sgpr(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
+ %1:sgpr(s64) = COPY $sgpr4_sgpr5
+ %2:sgpr(s128) = G_INSERT %0, %1, 64
+ S_ENDPGM 0, implicit %2
+...
+
+---
+
+name: insert_s_v256_v_s64_96
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9
+ ; CHECK-LABEL: name: insert_s_v256_v_s64_96
+ ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr8_vgpr9
+ ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vreg_256 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub3_sub4
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
+ %0:vgpr(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+ %1:vgpr(s64) = COPY $vgpr8_vgpr9
+ %2:vgpr(s256) = G_INSERT %0, %1, 96
+ S_ENDPGM 0, implicit %2
+...
+
+---
+
+name: insert_s_s256_s_s64_128
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9
+ ; CHECK-LABEL: name: insert_s_s256_s_s64_128
+ ; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5
+ ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:sgpr_256 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub4_sub5
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
+ %0:sgpr(s256) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
+ %1:sgpr(s64) = COPY $sgpr4_sgpr5
+ %2:sgpr(s256) = G_INSERT %0, %1, 128
+ S_ENDPGM 0, implicit %2
+...
+
+# ---
+
+# name: insert_s_s256_s_s64_160
+# legalized: true
+# regBankSelected: true
+
+# body: |
+# bb.0:
+# liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9
+# %0:sgpr(s256) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
+# %1:sgpr(s64) = COPY $sgpr4_sgpr5
+# %2:sgpr(s256) = G_INSERT %0, %1, 160
+# S_ENDPGM 0, implicit %2
+# ...
+
+---
+
+name: insert_s_s128_s_s96_0
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5_sgpr6
+ ; CHECK-LABEL: name: insert_s_s128_s_s96_0
+ ; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5_sgpr6
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_96 = COPY $sgpr4_sgpr5_sgpr6
+ ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:sgpr_128 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub0_sub1_sub2
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
+ %0:sgpr(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
+ %1:sgpr(s96) = COPY $sgpr4_sgpr5_sgpr6
+ %2:sgpr(s128) = G_INSERT %0, %1, 0
+ S_ENDPGM 0, implicit %2
+...
+
+---
+
+name: insert_s_s256_s_s128_0
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11
+
+ ; CHECK-LABEL: name: insert_s_s256_s_s128_0
+ ; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_128 = COPY $sgpr8_sgpr9_sgpr10_sgpr11
+ ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:sgpr_256 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub0_sub1_sub2_sub3
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
+ %0:sgpr(s256) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
+ %1:sgpr(s128) = COPY $sgpr8_sgpr9_sgpr10_sgpr11
+ %2:sgpr(s256) = G_INSERT %0, %1, 0
+ S_ENDPGM 0, implicit %2
+...
+
+---
+
+name: insert_v_s256_v_s128_32
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11
+
+ ; CHECK-LABEL: name: insert_v_s256_v_s128_32
+ ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_128 = COPY $vgpr8_vgpr9_vgpr10_vgpr11
+ ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vreg_256 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub1_sub2_sub3_sub4
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
+ %0:vgpr(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+ %1:vgpr(s128) = COPY $vgpr8_vgpr9_vgpr10_vgpr11
+ %2:vgpr(s256) = G_INSERT %0, %1, 32
+ S_ENDPGM 0, implicit %2
+...
+
+---
+
+name: insert_v_s256_v_s128_64
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11
+
+ ; CHECK-LABEL: name: insert_v_s256_v_s128_64
+ ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_128 = COPY $vgpr8_vgpr9_vgpr10_vgpr11
+ ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vreg_256 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub2_sub3_sub4_sub5
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
+ %0:vgpr(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+ %1:vgpr(s128) = COPY $vgpr8_vgpr9_vgpr10_vgpr11
+ %2:vgpr(s256) = G_INSERT %0, %1, 64
+ S_ENDPGM 0, implicit %2
+...
+
+---
+
+name: insert_v_s256_v_s128_96
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11
+
+ ; CHECK-LABEL: name: insert_v_s256_v_s128_96
+ ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_128 = COPY $vgpr8_vgpr9_vgpr10_vgpr11
+ ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vreg_256 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub3_sub4_sub5_sub6
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
+ %0:vgpr(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+ %1:vgpr(s128) = COPY $vgpr8_vgpr9_vgpr10_vgpr11
+ %2:vgpr(s256) = G_INSERT %0, %1, 96
+ S_ENDPGM 0, implicit %2
+...
+
+---
+
+name: insert_v_s256_v_s128_128
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11
+
+ ; CHECK-LABEL: name: insert_v_s256_v_s128_128
+ ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_128 = COPY $vgpr8_vgpr9_vgpr10_vgpr11
+ ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vreg_256 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub4_sub5_sub6_sub7
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
+ %0:vgpr(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+ %1:vgpr(s128) = COPY $vgpr8_vgpr9_vgpr10_vgpr11
+ %2:vgpr(s256) = G_INSERT %0, %1, 128
+ S_ENDPGM 0, implicit %2
+...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
index 8a16a0df8056a..b679d783751e4 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
@@ -148,15 +148,17 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s96) = COPY $vgpr0_vgpr1_vgpr2
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s96) = COPY $vgpr3_vgpr4_vgpr5
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s96)
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96)
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s64) = G_TRUNC [[COPY1]](s96)
- ; CHECK-NEXT: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s96)
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[TRUNC]], [[TRUNC1]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV2]], [[UV5]]
- ; CHECK-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND]](s64)
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[UV6]](s32), [[UV7]](s32), [[AND1]](s32)
- ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[MV]](s96)
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
+ ; CHECK-NEXT: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96)
+ ; CHECK-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s96)
+ ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV6]](s32), [[UV7]](s32)
+ ; CHECK-NEXT: [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s96)
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[MV]], [[MV1]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV5]], [[UV11]]
+ ; CHECK-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND]](s64)
+ ; CHECK-NEXT: [[MV2:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[UV12]](s32), [[UV13]](s32), [[AND1]](s32)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[MV2]](s96)
%0:_(s96) = COPY $vgpr0_vgpr1_vgpr2
%1:_(s96) = COPY $vgpr3_vgpr4_vgpr5
%2:_(s96) = G_AND %0, %1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
index fcd114dd3b6e3..a0d59547f34a6 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
@@ -100,8 +100,8 @@ body: |
; CHECK: liveins: $vgpr0_vgpr1_vgpr2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s96) = COPY $vgpr0_vgpr1_vgpr2
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s96)
- ; CHECK-NEXT: $vgpr0 = COPY [[TRUNC]](s32)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96)
+ ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)
%0:_(s96) = COPY $vgpr0_vgpr1_vgpr2
%1:_(s32) = G_EXTRACT %0, 0
$vgpr0 = COPY %1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def.mir
index ca5475bbdbc8c..d8503ecd7df20 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def.mir
@@ -135,9 +135,8 @@ body: |
bb.0:
; CHECK-LABEL: name: test_implicit_def_s448
- ; CHECK: [[DEF:%[0-9]+]]:_(s512) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[DEF]](s512)
- ; CHECK-NEXT: $vgpr0 = COPY [[TRUNC]](s32)
+ ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: $vgpr0 = COPY [[DEF]](s32)
%0:_(s448) = G_IMPLICIT_DEF
%1:_(s32) = G_EXTRACT %0, 0
$vgpr0 = COPY %1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert.mir
index 1a6b7e0dcacca..f46cc9b66fa15 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert.mir
@@ -1309,15 +1309,7 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST1]](<2 x s16>), [[UV1]](<2 x s16>)
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[COPY1]](<2 x s16>), [[UV1]](<2 x s16>)
; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
%0:_(<4 x s16>) = COPY $vgpr0_vgpr1
%1:_(<3 x s16>) = G_EXTRACT %0, 0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
index 2545b452d2a89..bef6e69de07bd 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
@@ -148,15 +148,17 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s96) = COPY $vgpr0_vgpr1_vgpr2
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s96) = COPY $vgpr3_vgpr4_vgpr5
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s96)
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96)
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s64) = G_TRUNC [[COPY1]](s96)
- ; CHECK-NEXT: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s96)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[TRUNC]], [[TRUNC1]]
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[UV2]], [[UV5]]
- ; CHECK-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[OR]](s64)
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[UV6]](s32), [[UV7]](s32), [[OR1]](s32)
- ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[MV]](s96)
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
+ ; CHECK-NEXT: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96)
+ ; CHECK-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s96)
+ ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV6]](s32), [[UV7]](s32)
+ ; CHECK-NEXT: [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s96)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[MV]], [[MV1]]
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[UV5]], [[UV11]]
+ ; CHECK-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[OR]](s64)
+ ; CHECK-NEXT: [[MV2:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[UV12]](s32), [[UV13]](s32), [[OR1]](s32)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[MV2]](s96)
%0:_(s96) = COPY $vgpr0_vgpr1_vgpr2
%1:_(s96) = COPY $vgpr3_vgpr4_vgpr5
%2:_(s96) = G_OR %0, %1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir
index bb3258d04f589..eace05a17adc7 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir
@@ -177,15 +177,17 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr6
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY2]](s32), [[C]]
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s96)
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96)
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s64) = G_TRUNC [[COPY1]](s96)
- ; CHECK-NEXT: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s96)
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[TRUNC]], [[TRUNC1]]
- ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[UV2]], [[UV5]]
- ; CHECK-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SELECT]](s64)
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[UV6]](s32), [[UV7]](s32), [[SELECT1]](s32)
- ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[MV]](s96)
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
+ ; CHECK-NEXT: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96)
+ ; CHECK-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s96)
+ ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV6]](s32), [[UV7]](s32)
+ ; CHECK-NEXT: [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s96)
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[MV]], [[MV1]]
+ ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[UV5]], [[UV11]]
+ ; CHECK-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SELECT]](s64)
+ ; CHECK-NEXT: [[MV2:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[UV12]](s32), [[UV13]](s32), [[SELECT1]](s32)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[MV2]](s96)
%0:_(s96) = COPY $vgpr0_vgpr1_vgpr2
%1:_(s96) = COPY $vgpr3_vgpr4_vgpr5
%2:_(s32) = COPY $vgpr6
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir
index e2446fe4b03f6..41f32964c55ff 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir
@@ -148,15 +148,17 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s96) = COPY $vgpr0_vgpr1_vgpr2
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s96) = COPY $vgpr3_vgpr4_vgpr5
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s96)
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96)
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s64) = G_TRUNC [[COPY1]](s96)
- ; CHECK-NEXT: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s96)
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[TRUNC]], [[TRUNC1]]
- ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[UV2]], [[UV5]]
- ; CHECK-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64)
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[UV6]](s32), [[UV7]](s32), [[XOR1]](s32)
- ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[MV]](s96)
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
+ ; CHECK-NEXT: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96)
+ ; CHECK-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s96)
+ ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV6]](s32), [[UV7]](s32)
+ ; CHECK-NEXT: [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s96)
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[MV]], [[MV1]]
+ ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[UV5]], [[UV11]]
+ ; CHECK-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64)
+ ; CHECK-NEXT: [[MV2:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[UV12]](s32), [[UV13]](s32), [[XOR1]](s32)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[MV2]](s96)
%0:_(s96) = COPY $vgpr0_vgpr1_vgpr2
%1:_(s96) = COPY $vgpr3_vgpr4_vgpr5
%2:_(s96) = G_XOR %0, %1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract.mir
new file mode 100644
index 0000000000000..85cb851b6bc3d
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract.mir
@@ -0,0 +1,85 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
+
+---
+name: extract_lo32_i64_s
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1
+ ; CHECK-LABEL: name: extract_lo32_i64_s
+ ; CHECK: liveins: $sgpr0_sgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
+ ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:sgpr(s32) = G_EXTRACT [[COPY]](s64), 0
+ %0:_(s64) = COPY $sgpr0_sgpr1
+ %1:_(s32) = G_EXTRACT %0, 0
+...
+
+---
+name: extract_lo32_i64_v
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+ ; CHECK-LABEL: name: extract_lo32_i64_v
+ ; CHECK: liveins: $vgpr0_vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:vgpr(s32) = G_EXTRACT [[COPY]](s64), 0
+ %0:_(s64) = COPY $vgpr0_vgpr1
+ %1:_(s32) = G_EXTRACT %0, 0
+...
+
+---
+name: extract_s32_0_s1024_v
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
+ ; CHECK-LABEL: name: extract_s32_0_s1024_v
+ ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s1024) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
+ ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:vgpr(s32) = G_EXTRACT [[COPY]](s1024), 0
+ %0:_(s1024) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
+ %1:_(s32) = G_EXTRACT %0, 0
+...
+
+---
+name: extract_s32_0_s1024_s
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
+ ; CHECK-LABEL: name: extract_s32_0_s1024_s
+ ; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s1024) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
+ ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:sgpr(s32) = G_EXTRACT [[COPY]](s1024), 0
+ %0:_(s1024) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
+ %1:_(s32) = G_EXTRACT %0, 0
+...
+
+---
+name: extract_lo32_i64_a
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $agpr0_agpr1
+ ; CHECK-LABEL: name: extract_lo32_i64_a
+ ; CHECK: liveins: $agpr0_agpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:agpr(s64) = COPY $agpr0_agpr1
+ ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:agpr(s32) = G_EXTRACT [[COPY]](s64), 0
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[EXTRACT]](s32)
+ %0:_(s64) = COPY $agpr0_agpr1
+ %1:_(s32) = G_EXTRACT %0, 0
+ S_ENDPGM 0, implicit %1
+...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert.mir
new file mode 100644
index 0000000000000..9809d9546639c
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert.mir
@@ -0,0 +1,187 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
+
+---
+name: insert_lo32_i64_ss
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1, $sgpr2
+ ; CHECK-LABEL: name: insert_lo32_i64_ss
+ ; CHECK: liveins: $sgpr0_sgpr1, $sgpr2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
+ ; CHECK-NEXT: [[INSERT:%[0-9]+]]:sgpr(s64) = G_INSERT [[COPY]], [[COPY1]](s32), 0
+ %0:_(s64) = COPY $sgpr0_sgpr1
+ %1:_(s32) = COPY $sgpr2
+ %2:_(s64) = G_INSERT %0, %1, 0
+...
+
+---
+name: insert_lo32_i64_sv
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1, $vgpr2
+ ; CHECK-LABEL: name: insert_lo32_i64_sv
+ ; CHECK: liveins: $sgpr0_sgpr1, $vgpr2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
+ ; CHECK-NEXT: [[INSERT:%[0-9]+]]:vgpr(s64) = G_INSERT [[COPY2]], [[COPY1]](s32), 0
+ %0:_(s64) = COPY $sgpr0_sgpr1
+ %1:_(s32) = COPY $vgpr2
+ %2:_(s64) = G_INSERT %0, %1, 0
+...
+---
+name: insert_lo32_i64_vs
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $sgpr2
+ ; CHECK-LABEL: name: insert_lo32_i64_vs
+ ; CHECK: liveins: $vgpr0_vgpr1, $sgpr2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[INSERT:%[0-9]+]]:vgpr(s64) = G_INSERT [[COPY]], [[COPY2]](s32), 0
+ %0:_(s64) = COPY $vgpr0_vgpr1
+ %1:_(s32) = COPY $sgpr2
+ %2:_(s64) = G_INSERT %0, %1, 0
+...
+---
+name: insert_lo32_i64_vv
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2
+ ; CHECK-LABEL: name: insert_lo32_i64_vv
+ ; CHECK: liveins: $vgpr0_vgpr1, $vgpr2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
+ ; CHECK-NEXT: [[INSERT:%[0-9]+]]:sgpr(s64) = G_INSERT [[COPY]], [[COPY1]](s32), 0
+ %0:_(s64) = COPY $sgpr0_sgpr1
+ %1:_(s32) = COPY $sgpr2
+ %2:_(s64) = G_INSERT %0, %1, 0
+...
+
+---
+name: insert_lo32_i128_v
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
+ ; CHECK-LABEL: name: insert_lo32_i128_v
+ ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr4
+ ; CHECK-NEXT: [[INSERT:%[0-9]+]]:vgpr(s128) = G_INSERT [[COPY]], [[COPY1]](s32), 0
+ %0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ %1:_(s32) = COPY $vgpr4
+ %2:_(s128) = G_INSERT %0, %1, 0
+...
+
+---
+name: insert_lo32_i64_aa
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $agpr0_agpr1, $agpr2
+ ; CHECK-LABEL: name: insert_lo32_i64_aa
+ ; CHECK: liveins: $agpr0_agpr1, $agpr2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:agpr(s64) = COPY $agpr0_agpr1
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:agpr(s32) = COPY $agpr2
+ ; CHECK-NEXT: [[INSERT:%[0-9]+]]:agpr(s64) = G_INSERT [[COPY]], [[COPY1]](s32), 0
+ %0:_(s64) = COPY $agpr0_agpr1
+ %1:_(s32) = COPY $agpr2
+ %2:_(s64) = G_INSERT %0, %1, 0
+...
+
+---
+name: insert_lo32_i64_av
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $agpr0_agpr1, $vgpr2
+ ; CHECK-LABEL: name: insert_lo32_i64_av
+ ; CHECK: liveins: $agpr0_agpr1, $vgpr2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:agpr(s64) = COPY $agpr0_agpr1
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
+ ; CHECK-NEXT: [[INSERT:%[0-9]+]]:vgpr(s64) = G_INSERT [[COPY2]], [[COPY1]](s32), 0
+ %0:_(s64) = COPY $agpr0_agpr1
+ %1:_(s32) = COPY $vgpr2
+ %2:_(s64) = G_INSERT %0, %1, 0
+...
+---
+name: insert_lo32_i64_va
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $agpr2
+ ; CHECK-LABEL: name: insert_lo32_i64_va
+ ; CHECK: liveins: $vgpr0_vgpr1, $agpr2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:agpr(s32) = COPY $agpr2
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[INSERT:%[0-9]+]]:vgpr(s64) = G_INSERT [[COPY]], [[COPY2]](s32), 0
+ %0:_(s64) = COPY $vgpr0_vgpr1
+ %1:_(s32) = COPY $agpr2
+ %2:_(s64) = G_INSERT %0, %1, 0
+...
+
+---
+name: insert_lo32_i64_as
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $agpr0_agpr1, $sgpr2
+ ; CHECK-LABEL: name: insert_lo32_i64_as
+ ; CHECK: liveins: $agpr0_agpr1, $sgpr2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:agpr(s64) = COPY $agpr0_agpr1
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[INSERT:%[0-9]+]]:vgpr(s64) = G_INSERT [[COPY2]], [[COPY3]](s32), 0
+ %0:_(s64) = COPY $agpr0_agpr1
+ %1:_(s32) = COPY $sgpr2
+ %2:_(s64) = G_INSERT %0, %1, 0
+...
+---
+name: insert_lo32_i64_sa
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1, $agpr2
+ ; CHECK-LABEL: name: insert_lo32_i64_sa
+ ; CHECK: liveins: $sgpr0_sgpr1, $agpr2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:agpr(s32) = COPY $agpr2
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[INSERT:%[0-9]+]]:vgpr(s64) = G_INSERT [[COPY2]], [[COPY3]](s32), 0
+ %0:_(s64) = COPY $sgpr0_sgpr1
+ %1:_(s32) = COPY $agpr2
+ %2:_(s64) = G_INSERT %0, %1, 0
+...
diff --git a/llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp b/llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp
index f80082fdd46d0..88567300188ea 100644
--- a/llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp
+++ b/llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp
@@ -3246,7 +3246,7 @@ TEST_F(AArch64GISelMITest, LowerInsert) {
EXPECT_EQ(LegalizerHelper::LegalizeResult::Legalized,
Helper.lower(*InsertV2S32S32, 0, LLT{}));
- EXPECT_EQ(LegalizerHelper::LegalizeResult::UnableToLegalize,
+ EXPECT_EQ(LegalizerHelper::LegalizeResult::Legalized,
Helper.lower(*InsertV2S32P1, 0, LLT{}));
const auto *CheckStr = R"(
@@ -3289,6 +3289,10 @@ TEST_F(AArch64GISelMITest, LowerInsert) {
CHECK: [[V2S32_E0:%[0-9]+]]:_(s32), [[V2S32_E1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[V2S32]]
CHECK: [[BV:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[V2S32_E0]]:_(s32), [[S32]]:_(s32)
+
+ CHECK: [[V2S32_E0:%[0-9]+]]:_(s32), [[V2S32_E1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[V2S32]]
+ CHECK: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[P1]]
+ CHECK: [[BV:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[PTRTOINT]]:_(s32), [[V2S32_E1]]:_(s32)
)";
// Check
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