[llvm] [TableGen] Complete the support for artificial registers (PR #183371)

[Ivan Kosarev via llvm-commits]

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@@ -844,7 +844,30 @@ unsigned CodeGenRegisterClass::getWeight(const CodeGenRegBank &RegBank) const {
 bool CodeGenRegisterClass::Key::operator<(
     const CodeGenRegisterClass::Key &B) const {
   assert(Members && B.Members);
-  return std::tie(*Members, RSI) < std::tie(*B.Members, B.RSI);
+  if (!IgnoreArtificialMembers)
+    return std::tie(*Members, RSI) < std::tie(*B.Members, B.RSI);
+
+  // Do the same lexicographical comparison, but ignoring
+  // artificial registers.
+  auto IA = Members->begin(), EA = Members->end();
+  auto IB = B.Members->begin(), EB = B.Members->end();
+  while (IA != EA && IB != EB) {
+    if ((*IA)->Artificial) {
+      ++IA;
+      continue;
+    }
+    if ((*IB)->Artificial) {
+      ++IB;
+      continue;
+    }
+    if (*IA != *IB)
+      return *IA < *IB;
+    ++IA;
+    ++IB;
+  }
+  if (IA == EA && IB == EB)
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kosarev wrote:

If both the iterators reached their ends, we know there are no any more registers to compare, artificial or not. Otherwise, we know the lists of non-artificial members are not equal and one of the iterators reached the end, so we just need to see which one.

https://github.com/llvm/llvm-project/pull/183371