[llvm] 0da2aec - [SLP]Invalid cost for non-power-of-2 bswaps (#185407)

[via llvm-commits]

Author: Alexey Bataev
Date: 2026-03-09T11:07:09-04:00
New Revision: 0da2aecb01412588c571038d7c887674c291a08f

URL: https://github.com/llvm/llvm-project/commit/0da2aecb01412588c571038d7c887674c291a08f
DIFF: https://github.com/llvm/llvm-project/commit/0da2aecb01412588c571038d7c887674c291a08f.diff

LOG: [SLP]Invalid cost for non-power-of-2 bswaps (#185407)

bswaps are supported only for power-of-2 types, need to disable it for
the default cost model to fix a compiler crash.

Fixes
https://github.com/llvm/llvm-project/pull/184018#issuecomment-4022697189

Added: 
    llvm/test/Transforms/SLPVectorizer/non-power-of-2-bswap.ll

Modified: 
    llvm/include/llvm/Analysis/TargetTransformInfoImpl.h

Removed: 
    


################################################################################
diff  --git a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
index 6e5d7d308be21..62e2ac6afa4af 100644
--- a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
+++ b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
@@ -947,6 +947,10 @@ class TargetTransformInfoImplBase {
     case Intrinsic::ssa_copy:
       // These intrinsics don't actually represent code after lowering.
       return 0;
+    case Intrinsic::bswap:
+      if (!ICA.getReturnType()->isVectorTy() &&
+          !isPowerOf2_64(DL.getTypeSizeInBits(ICA.getReturnType())))
+        return InstructionCost::getInvalid();
     }
     return 1;
   }

diff  --git a/llvm/test/Transforms/SLPVectorizer/non-power-of-2-bswap.ll b/llvm/test/Transforms/SLPVectorizer/non-power-of-2-bswap.ll
new file mode 100644
index 0000000000000..f0369e06d07fc
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/non-power-of-2-bswap.ll
@@ -0,0 +1,55 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
+; RUN: opt -passes=slp-vectorizer -S -slp-vectorize-non-power-of-2 < %s | FileCheck %s
+
+define i64 @bswap_i24(ptr noalias %p, ptr noalias %p1) {
+; CHECK-LABEL: define i64 @bswap_i24(
+; CHECK-SAME: ptr noalias [[P:%.*]], ptr noalias [[P1:%.*]]) {
+; CHECK-NEXT:    [[G2:%.*]] = getelementptr i8, ptr [[P]], i32 2
+; CHECK-NEXT:    [[T2:%.*]] = load i8, ptr [[G2]], align 1
+; CHECK-NEXT:    [[G12:%.*]] = getelementptr i8, ptr [[P1]], i32 2
+; CHECK-NEXT:    [[T12:%.*]] = load i8, ptr [[G12]], align 1
+; CHECK-NEXT:    [[A2:%.*]] = add i8 [[T2]], [[T12]]
+; CHECK-NEXT:    [[Z2:%.*]] = zext i8 [[A2]] to i64
+; CHECK-NEXT:    [[TMP1:%.*]] = load <2 x i8>, ptr [[P]], align 1
+; CHECK-NEXT:    [[TMP2:%.*]] = load <2 x i8>, ptr [[P1]], align 1
+; CHECK-NEXT:    [[TMP3:%.*]] = add <2 x i8> [[TMP1]], [[TMP2]]
+; CHECK-NEXT:    [[TMP4:%.*]] = zext <2 x i8> [[TMP3]] to <2 x i32>
+; CHECK-NEXT:    [[TMP5:%.*]] = shl <2 x i32> [[TMP4]], <i32 16, i32 8>
+; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <2 x i32> [[TMP5]], i32 0
+; CHECK-NEXT:    [[TMP7:%.*]] = zext i32 [[TMP6]] to i64
+; CHECK-NEXT:    [[TMP8:%.*]] = extractelement <2 x i32> [[TMP5]], i32 1
+; CHECK-NEXT:    [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
+; CHECK-NEXT:    [[OR01:%.*]] = or disjoint i64 [[TMP7]], [[TMP9]]
+; CHECK-NEXT:    [[OR012:%.*]] = or disjoint i64 [[OR01]], [[Z2]]
+; CHECK-NEXT:    ret i64 [[OR012]]
+;
+  %g1 = getelementptr i8, ptr %p, i32 1
+  %g2 = getelementptr i8, ptr %p, i32 2
+
+  %t0 = load i8, ptr %p
+  %t1 = load i8, ptr %g1
+  %t2 = load i8, ptr %g2
+
+  %g11 = getelementptr i8, ptr %p1, i32 1
+  %g12 = getelementptr i8, ptr %p1, i32 2
+
+  %t10 = load i8, ptr %p1
+  %t11 = load i8, ptr %g11
+  %t12 = load i8, ptr %g12
+
+  %a0 = add i8 %t0, %t10
+  %a1 = add i8 %t1, %t11
+  %a2 = add i8 %t2, %t12
+
+  %z0 = zext i8 %a0 to i64
+  %z1 = zext i8 %a1 to i64
+  %z2 = zext i8 %a2 to i64
+
+  %sh0 = shl nuw i64 %z0, 16
+  %sh1 = shl nuw nsw i64 %z1, 8
+
+  %or01 = or disjoint i64 %sh0, %sh1
+  %or012 = or disjoint i64 %or01, %z2
+
+  ret i64 %or012
+}