[llvm] [Hexagon] Add new register input/output types for qf instructions (PR #184398)

[Fateme Hosseini via llvm-commits]

fhossein-quic wrote:

> I had earlier used this implementation, but it will be hard to maintain this since at every ISA expansion, we would have to manually add opcodes in these relevant APIs. The query via TSFlags fixes the problem. However, this patch should be good enough for now.

Yeah, this is pretty hard to maintain and doesn’t scale. We need an upstreamable solution instead of TSFlags2. Then we can remove the query‑to‑opcode mechanism.

https://github.com/llvm/llvm-project/pull/184398