[llvm] [AArch64] fuse constant addition after sbb (PR #185117)

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``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp -- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp --diff_from_common_commit
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``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 2c766b29d..f7b407660 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -23368,8 +23368,7 @@ static SDValue performAddWithSBCCombine(SDNode *N, SelectionDAG &DAG) {
   // AArch64 SBC (non-flag-setting) has only one output; no flags guard needed.
   SDLoc DL(N);
   return DAG.getNode(AArch64ISD::SBC, DL, VT, SBC.getOperand(0),
-                     DAG.getNegative(C, DL, VT),
-                     SBC.getOperand(2));
+                     DAG.getNegative(C, DL, VT), SBC.getOperand(2));
 }
 
 static SDValue performAddSubCombine(SDNode *N,

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https://github.com/llvm/llvm-project/pull/185117