[llvm] [TableGen] Complete the support for artificial registers (PR #183371)

[Ivan Kosarev via llvm-commits]

kosarev wrote:

It doesn't reproduce for me.

> ```
> The problem is in commit 21c1ba16edc0 [TableGen] Complete the support for artificial registers.
> 
> Issue: In inferMatchingSuperRegClass(), the SubRegs vector is built by iterating over RC->getMembers() 
> and skipping artificial registers (line 2465-2466 adds if (Super->Artificial) continue;). However, when
> later zipping SubRegs with RC->getMembers() at line 2484, the full member list (including artificial 
> registers) is used. This causes a size mismatch - SubRegs has fewer elements than RC->getMembers() when
> artificial registers are present, leading to a past-the-end iterator dereference in zip_equal().
> 
> The same filtering pattern that was correctly applied in inferSubClassWithSubReg() (lines 2510-2518 in 
> the diff) was not applied to the corresponding code in inferMatchingSuperRegClass().
> ```

The line numbers seem off and the description doesn't match the reality: both `inferSubClassWithSubReg()` and `inferMatchingSuperRegClass()` do the filtering.

Here's the part in `inferMatchingSuperRegClass()` that I understand it refers to, with no other zips in sight:
```c++
      auto IsNotArtificial = [](const CodeGenRegister *R) {
        return !R->Artificial;
      };
      auto NonArtificialMembers =
          make_filter_range(RC->getMembers(), IsNotArtificial);
      for (const auto &[Sub, Super] :
           zip_equal(SubRegs, NonArtificialMembers)) {
```

Do you have any changes in the TableGen sources at all that are not in the mainline?

https://github.com/llvm/llvm-project/pull/183371