[llvm] AMDGPU: Fix selection failure on fast vector rootn (PR #185035)
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 9 02:54:49 PDT 2026
https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/185035
>From 1c1163e5bbba22b7d100c9230d7d3e835182dae4 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Fri, 6 Mar 2026 16:34:33 +0100
Subject: [PATCH] AMDGPU: Fix selection failure on fast vector rootn
This was emitting the raw rcp intrinsic, which will fail for any
vector type. This is an afn context anyway, so just emit fdiv
which will select to rcp but also will undergo type legalization.
---
llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp | 5 +-
.../amdgpu-simplify-libcall-rootn-codegen.ll | 145 ++++++++++++++++++
.../AMDGPU/amdgpu-simplify-libcall-rootn.ll | 84 +++++-----
3 files changed, 189 insertions(+), 45 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-rootn-codegen.ll
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp b/llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp
index 26d6ad4e36b58..a26ad67458359 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp
@@ -1482,7 +1482,10 @@ bool AMDGPULibCalls::expandFastPow(FPMathOperator *FPOp, IRBuilder<> &B,
}
case PowKind::RootN: {
Value *CastY = B.CreateSIToFP(Y, X->getType());
- Value *RcpY = B.CreateUnaryIntrinsic(Intrinsic::amdgcn_rcp, CastY);
+
+ // This is afn anyway, so we will turn into rcp.
+ Value *RcpY = B.CreateFDiv(ConstantFP::get(X->getType(), 1.0), CastY);
+
Value *ExpYLnX = emitFastExpYLnx(B, X, RcpY);
Value *Fixed = emitPowFixup(B, X, Y, ExpYLnX, Kind);
replaceCall(FPOp, Fixed);
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-rootn-codegen.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-rootn-codegen.ll
new file mode 100644
index 0000000000000..5f6a38018be20
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-rootn-codegen.ll
@@ -0,0 +1,145 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: opt -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes=amdgpu-simplifylib,instcombine < %s | llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 | FileCheck %s
+
+; Make sure the output of fast rootn expansion actually codegens in
+; scalar and vector case.
+
+declare float @_Z5rootnfi(float, i32) #0
+declare <2 x float> @_Z5rootnDv2_fDv2_i(<2 x float>, <2 x i32>) #0
+
+define float @test_rootn_afn_f32(float %x, i32 %y) #0 {
+; CHECK-LABEL: test_rootn_afn_f32:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: s_mov_b32 s4, 0x800000
+; CHECK-NEXT: v_cvt_f32_i32_e32 v2, v1
+; CHECK-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 32, vcc
+; CHECK-NEXT: v_ldexp_f32 v4, |v0|, v4
+; CHECK-NEXT: v_log_f32_e32 v4, v4
+; CHECK-NEXT: v_rcp_iflag_f32_e32 v2, v2
+; CHECK-NEXT: v_mov_b32_e32 v3, 0x42000000
+; CHECK-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; CHECK-NEXT: v_sub_f32_e32 v3, v4, v3
+; CHECK-NEXT: v_mul_f32_e32 v2, v2, v3
+; CHECK-NEXT: s_mov_b32 s4, 0xc2fc0000
+; CHECK-NEXT: v_mov_b32_e32 v3, 0x42800000
+; CHECK-NEXT: v_cmp_gt_f32_e32 vcc, s4, v2
+; CHECK-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; CHECK-NEXT: v_add_f32_e32 v2, v2, v3
+; CHECK-NEXT: v_exp_f32_e32 v2, v2
+; CHECK-NEXT: v_not_b32_e32 v3, 63
+; CHECK-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; CHECK-NEXT: s_movk_i32 s4, 0x204
+; CHECK-NEXT: v_ldexp_f32 v2, v2, v3
+; CHECK-NEXT: v_and_b32_e32 v3, 1, v1
+; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
+; CHECK-NEXT: v_cndmask_b32_e64 v3, v0, 1.0, vcc
+; CHECK-NEXT: s_brev_b32 s10, -2
+; CHECK-NEXT: v_cmp_class_f32_e64 s[8:9], v0, s4
+; CHECK-NEXT: v_cmp_eq_f32_e64 s[4:5], 0, v0
+; CHECK-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v1
+; CHECK-NEXT: v_bfi_b32 v2, s10, v2, v3
+; CHECK-NEXT: v_mov_b32_e32 v3, 0x7f800000
+; CHECK-NEXT: s_xor_b64 s[6:7], s[4:5], s[6:7]
+; CHECK-NEXT: v_cndmask_b32_e64 v3, v3, 0, s[6:7]
+; CHECK-NEXT: v_cndmask_b32_e64 v4, v0, 0, vcc
+; CHECK-NEXT: v_bfi_b32 v3, s10, v3, v4
+; CHECK-NEXT: s_or_b64 s[4:5], s[8:9], s[4:5]
+; CHECK-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[4:5]
+; CHECK-NEXT: v_cmp_gt_f32_e64 s[4:5], 0, v0
+; CHECK-NEXT: s_and_b64 s[4:5], s[4:5], vcc
+; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
+; CHECK-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; CHECK-NEXT: s_or_b64 vcc, s[4:5], vcc
+; CHECK-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+ %call = tail call afn float @_Z5rootnfi(float %x, i32 %y)
+ ret float %call
+}
+
+define <2 x float> @test_rootn_afn_v2f32(<2 x float> %x, <2 x i32> %y) #0 {
+; CHECK-LABEL: test_rootn_afn_v2f32:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: s_mov_b32 s4, 0x800000
+; CHECK-NEXT: v_cvt_f32_i32_e32 v5, v3
+; CHECK-NEXT: v_mov_b32_e32 v6, 0x42000000
+; CHECK-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s4
+; CHECK-NEXT: v_cvt_f32_i32_e32 v4, v2
+; CHECK-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc
+; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 32, vcc
+; CHECK-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; CHECK-NEXT: v_ldexp_f32 v8, |v1|, v8
+; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 32, vcc
+; CHECK-NEXT: v_log_f32_e32 v8, v8
+; CHECK-NEXT: v_ldexp_f32 v9, |v0|, v9
+; CHECK-NEXT: v_log_f32_e32 v9, v9
+; CHECK-NEXT: v_rcp_iflag_f32_e32 v5, v5
+; CHECK-NEXT: v_rcp_iflag_f32_e32 v4, v4
+; CHECK-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
+; CHECK-NEXT: v_sub_f32_e32 v7, v8, v7
+; CHECK-NEXT: v_sub_f32_e32 v6, v9, v6
+; CHECK-NEXT: v_mul_f32_e32 v5, v5, v7
+; CHECK-NEXT: s_mov_b32 s4, 0xc2fc0000
+; CHECK-NEXT: v_mul_f32_e32 v4, v4, v6
+; CHECK-NEXT: v_mov_b32_e32 v6, 0x42800000
+; CHECK-NEXT: v_cmp_gt_f32_e32 vcc, s4, v5
+; CHECK-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc
+; CHECK-NEXT: v_cmp_gt_f32_e64 s[4:5], s4, v4
+; CHECK-NEXT: v_add_f32_e32 v5, v5, v7
+; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, v6, s[4:5]
+; CHECK-NEXT: v_exp_f32_e32 v5, v5
+; CHECK-NEXT: v_add_f32_e32 v4, v4, v6
+; CHECK-NEXT: v_exp_f32_e32 v4, v4
+; CHECK-NEXT: v_not_b32_e32 v7, 63
+; CHECK-NEXT: v_cndmask_b32_e32 v6, 0, v7, vcc
+; CHECK-NEXT: v_ldexp_f32 v5, v5, v6
+; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, v7, s[4:5]
+; CHECK-NEXT: v_ldexp_f32 v4, v4, v6
+; CHECK-NEXT: v_and_b32_e32 v6, 1, v3
+; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v6
+; CHECK-NEXT: v_and_b32_e32 v7, 1, v2
+; CHECK-NEXT: v_cndmask_b32_e64 v6, v1, 1.0, vcc
+; CHECK-NEXT: s_brev_b32 s18, -2
+; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v7
+; CHECK-NEXT: v_bfi_b32 v5, s18, v5, v6
+; CHECK-NEXT: v_mov_b32_e32 v6, 0x204
+; CHECK-NEXT: v_cmp_eq_f32_e64 s[10:11], 0, v1
+; CHECK-NEXT: v_cmp_gt_i32_e64 s[14:15], 0, v3
+; CHECK-NEXT: v_cndmask_b32_e64 v7, v0, 1.0, s[4:5]
+; CHECK-NEXT: v_cmp_class_f32_e64 s[6:7], v1, v6
+; CHECK-NEXT: v_cmp_class_f32_e64 s[8:9], v0, v6
+; CHECK-NEXT: v_cmp_eq_f32_e64 s[12:13], 0, v0
+; CHECK-NEXT: v_cmp_gt_i32_e64 s[16:17], 0, v2
+; CHECK-NEXT: v_mov_b32_e32 v6, 0x7f800000
+; CHECK-NEXT: s_xor_b64 s[14:15], s[10:11], s[14:15]
+; CHECK-NEXT: v_bfi_b32 v4, s18, v4, v7
+; CHECK-NEXT: v_cndmask_b32_e64 v7, v6, 0, s[14:15]
+; CHECK-NEXT: s_xor_b64 s[14:15], s[12:13], s[16:17]
+; CHECK-NEXT: v_cndmask_b32_e64 v8, v1, 0, vcc
+; CHECK-NEXT: v_cndmask_b32_e64 v6, v6, 0, s[14:15]
+; CHECK-NEXT: v_cndmask_b32_e64 v9, v0, 0, s[4:5]
+; CHECK-NEXT: v_bfi_b32 v7, s18, v7, v8
+; CHECK-NEXT: s_or_b64 s[6:7], s[6:7], s[10:11]
+; CHECK-NEXT: v_bfi_b32 v6, s18, v6, v9
+; CHECK-NEXT: v_cndmask_b32_e64 v5, v5, v7, s[6:7]
+; CHECK-NEXT: s_or_b64 s[6:7], s[8:9], s[12:13]
+; CHECK-NEXT: v_cndmask_b32_e64 v4, v4, v6, s[6:7]
+; CHECK-NEXT: v_cmp_gt_f32_e64 s[6:7], 0, v1
+; CHECK-NEXT: v_cmp_gt_f32_e64 s[8:9], 0, v0
+; CHECK-NEXT: s_and_b64 s[8:9], s[8:9], s[4:5]
+; CHECK-NEXT: s_and_b64 s[6:7], s[6:7], vcc
+; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
+; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v3
+; CHECK-NEXT: v_mov_b32_e32 v1, 0x7fc00000
+; CHECK-NEXT: s_or_b64 vcc, s[8:9], vcc
+; CHECK-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc
+; CHECK-NEXT: s_or_b64 vcc, s[6:7], s[4:5]
+; CHECK-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+ %call = tail call afn <2 x float> @_Z5rootnDv2_fDv2_i(<2 x float> %x, <2 x i32> %y)
+ ret <2 x float> %call
+}
+
+attributes #0 = { nounwind }
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-rootn.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-rootn.ll
index 00b4583494c75..337ccb4a2d0e9 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-rootn.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-rootn.ll
@@ -271,7 +271,7 @@ define half @test_rootn_f16_1(half %x) {
define half @test_rootn_f16_2(half %x) {
; CHECK-LABEL: define half @test_rootn_f16_2(
; CHECK-SAME: half [[X:%.*]]) {
-; CHECK-NEXT: [[CALL:%.*]] = call half @llvm.sqrt.f16(half [[X]]), !fpmath [[META0:![0-9]+]]
+; CHECK-NEXT: [[CALL:%.*]] = call half @llvm.sqrt.f16(half [[X]]), !fpmath [[META1:![0-9]+]]
; CHECK-NEXT: ret half [[CALL]]
;
%call = tail call half @_Z5rootnDhi(half %x, i32 2)
@@ -307,7 +307,7 @@ define half @test_rootn_f16_neg2(half %x) {
; CHECK-LABEL: define half @test_rootn_f16_neg2(
; CHECK-SAME: half [[X:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = call contract half @llvm.sqrt.f16(half [[X]])
-; CHECK-NEXT: [[__ROOTN2RSQRT:%.*]] = fdiv contract half 0xH3C00, [[TMP1]], !fpmath [[META0]]
+; CHECK-NEXT: [[__ROOTN2RSQRT:%.*]] = fdiv contract half 0xH3C00, [[TMP1]], !fpmath [[META1]]
; CHECK-NEXT: ret half [[__ROOTN2RSQRT]]
;
%call = tail call half @_Z5rootnDhi(half %x, i32 -2)
@@ -356,7 +356,7 @@ define <2 x half> @test_rootn_v2f16_1(<2 x half> %x) {
define <2 x half> @test_rootn_v2f16_2(<2 x half> %x) {
; CHECK-LABEL: define <2 x half> @test_rootn_v2f16_2(
; CHECK-SAME: <2 x half> [[X:%.*]]) {
-; CHECK-NEXT: [[CALL:%.*]] = call <2 x half> @llvm.sqrt.v2f16(<2 x half> [[X]]), !fpmath [[META0]]
+; CHECK-NEXT: [[CALL:%.*]] = call <2 x half> @llvm.sqrt.v2f16(<2 x half> [[X]]), !fpmath [[META1]]
; CHECK-NEXT: ret <2 x half> [[CALL]]
;
%call = tail call <2 x half> @_Z5rootnDv2_DhDv2_i(<2 x half> %x, <2 x i32> <i32 2, i32 2>)
@@ -377,7 +377,7 @@ define <2 x half> @test_rootn_v2f16_neg2(<2 x half> %x) {
; CHECK-LABEL: define <2 x half> @test_rootn_v2f16_neg2(
; CHECK-SAME: <2 x half> [[X:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = call contract <2 x half> @llvm.sqrt.v2f16(<2 x half> [[X]])
-; CHECK-NEXT: [[__ROOTN2RSQRT:%.*]] = fdiv contract <2 x half> splat (half 0xH3C00), [[TMP1]], !fpmath [[META0]]
+; CHECK-NEXT: [[__ROOTN2RSQRT:%.*]] = fdiv contract <2 x half> splat (half 0xH3C00), [[TMP1]], !fpmath [[META1]]
; CHECK-NEXT: ret <2 x half> [[__ROOTN2RSQRT]]
;
%call = tail call <2 x half> @_Z5rootnDv2_DhDv2_i(<2 x half> %x, <2 x i32> <i32 -2, i32 -2>)
@@ -618,7 +618,7 @@ define float @test_rootn_f32__y_2(float %x) {
; CHECK-LABEL: define float @test_rootn_f32__y_2(
; CHECK-SAME: float [[X:%.*]]) {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[CALL:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath [[META0]]
+; CHECK-NEXT: [[CALL:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath [[META1]]
; CHECK-NEXT: ret float [[CALL]]
;
entry:
@@ -630,7 +630,7 @@ define float @test_rootn_f32__y_2_flags(float %x) {
; CHECK-LABEL: define float @test_rootn_f32__y_2_flags(
; CHECK-SAME: float [[X:%.*]]) {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[CALL:%.*]] = call nnan nsz float @llvm.sqrt.f32(float [[X]]), !fpmath [[META0]]
+; CHECK-NEXT: [[CALL:%.*]] = call nnan nsz float @llvm.sqrt.f32(float [[X]]), !fpmath [[META1]]
; CHECK-NEXT: ret float [[CALL]]
;
entry:
@@ -643,7 +643,7 @@ define float @test_rootn_f32__y_2_fpmath_3(float %x) {
; CHECK-LABEL: define float @test_rootn_f32__y_2_fpmath_3(
; CHECK-SAME: float [[X:%.*]]) {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[CALL:%.*]] = call nnan nsz float @llvm.sqrt.f32(float [[X]]), !fpmath [[META1:![0-9]+]]
+; CHECK-NEXT: [[CALL:%.*]] = call nnan nsz float @llvm.sqrt.f32(float [[X]]), !fpmath [[META2:![0-9]+]]
; CHECK-NEXT: ret float [[CALL]]
;
entry:
@@ -655,7 +655,7 @@ define <2 x float> @test_rootn_v2f32__y_2_flags(<2 x float> %x) {
; CHECK-LABEL: define <2 x float> @test_rootn_v2f32__y_2_flags(
; CHECK-SAME: <2 x float> [[X:%.*]]) {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[CALL:%.*]] = call nnan nsz <2 x float> @llvm.sqrt.v2f32(<2 x float> [[X]]), !fpmath [[META0]]
+; CHECK-NEXT: [[CALL:%.*]] = call nnan nsz <2 x float> @llvm.sqrt.v2f32(<2 x float> [[X]]), !fpmath [[META1]]
; CHECK-NEXT: ret <2 x float> [[CALL]]
;
entry:
@@ -667,7 +667,7 @@ define <3 x float> @test_rootn_v3f32__y_2(<3 x float> %x) {
; CHECK-LABEL: define <3 x float> @test_rootn_v3f32__y_2(
; CHECK-SAME: <3 x float> [[X:%.*]]) {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[CALL:%.*]] = call <3 x float> @llvm.sqrt.v3f32(<3 x float> [[X]]), !fpmath [[META0]]
+; CHECK-NEXT: [[CALL:%.*]] = call <3 x float> @llvm.sqrt.v3f32(<3 x float> [[X]]), !fpmath [[META1]]
; CHECK-NEXT: ret <3 x float> [[CALL]]
;
entry:
@@ -679,7 +679,7 @@ define <3 x float> @test_rootn_v3f32__y_2_undef(<3 x float> %x) {
; CHECK-LABEL: define <3 x float> @test_rootn_v3f32__y_2_undef(
; CHECK-SAME: <3 x float> [[X:%.*]]) {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[CALL:%.*]] = call <3 x float> @llvm.sqrt.v3f32(<3 x float> [[X]]), !fpmath [[META0]]
+; CHECK-NEXT: [[CALL:%.*]] = call <3 x float> @llvm.sqrt.v3f32(<3 x float> [[X]]), !fpmath [[META1]]
; CHECK-NEXT: ret <3 x float> [[CALL]]
;
entry:
@@ -691,7 +691,7 @@ define <4 x float> @test_rootn_v4f32__y_2(<4 x float> %x) {
; CHECK-LABEL: define <4 x float> @test_rootn_v4f32__y_2(
; CHECK-SAME: <4 x float> [[X:%.*]]) {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[CALL:%.*]] = call <4 x float> @llvm.sqrt.v4f32(<4 x float> [[X]]), !fpmath [[META0]]
+; CHECK-NEXT: [[CALL:%.*]] = call <4 x float> @llvm.sqrt.v4f32(<4 x float> [[X]]), !fpmath [[META1]]
; CHECK-NEXT: ret <4 x float> [[CALL]]
;
entry:
@@ -703,7 +703,7 @@ define <8 x float> @test_rootn_v8f32__y_2(<8 x float> %x) {
; CHECK-LABEL: define <8 x float> @test_rootn_v8f32__y_2(
; CHECK-SAME: <8 x float> [[X:%.*]]) {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[CALL:%.*]] = call <8 x float> @llvm.sqrt.v8f32(<8 x float> [[X]]), !fpmath [[META0]]
+; CHECK-NEXT: [[CALL:%.*]] = call <8 x float> @llvm.sqrt.v8f32(<8 x float> [[X]]), !fpmath [[META1]]
; CHECK-NEXT: ret <8 x float> [[CALL]]
;
entry:
@@ -715,7 +715,7 @@ define <16 x float> @test_rootn_v16f32__y_2(<16 x float> %x) {
; CHECK-LABEL: define <16 x float> @test_rootn_v16f32__y_2(
; CHECK-SAME: <16 x float> [[X:%.*]]) {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[CALL:%.*]] = call <16 x float> @llvm.sqrt.v16f32(<16 x float> [[X]]), !fpmath [[META0]]
+; CHECK-NEXT: [[CALL:%.*]] = call <16 x float> @llvm.sqrt.v16f32(<16 x float> [[X]]), !fpmath [[META1]]
; CHECK-NEXT: ret <16 x float> [[CALL]]
;
entry:
@@ -775,7 +775,7 @@ define <2 x float> @test_rootn_v2f32__y_nonsplat_2_poison(<2 x float> %x) {
; CHECK-LABEL: define <2 x float> @test_rootn_v2f32__y_nonsplat_2_poison(
; CHECK-SAME: <2 x float> [[X:%.*]]) {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[CALL:%.*]] = call <2 x float> @llvm.sqrt.v2f32(<2 x float> [[X]]), !fpmath [[META0]]
+; CHECK-NEXT: [[CALL:%.*]] = call <2 x float> @llvm.sqrt.v2f32(<2 x float> [[X]]), !fpmath [[META1]]
; CHECK-NEXT: ret <2 x float> [[CALL]]
;
entry:
@@ -884,7 +884,7 @@ define float @test_rootn_f32__y_neg2(float %x) {
; CHECK-SAME: float [[X:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = call contract float @llvm.sqrt.f32(float [[X]])
-; CHECK-NEXT: [[__ROOTN2RSQRT:%.*]] = fdiv contract float 1.000000e+00, [[TMP0]], !fpmath [[META0]]
+; CHECK-NEXT: [[__ROOTN2RSQRT:%.*]] = fdiv contract float 1.000000e+00, [[TMP0]], !fpmath [[META1]]
; CHECK-NEXT: ret float [[__ROOTN2RSQRT]]
;
entry:
@@ -897,7 +897,7 @@ define float @test_rootn_f32__y_neg2__flags(float %x) {
; CHECK-SAME: float [[X:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = call nnan nsz contract float @llvm.sqrt.f32(float [[X]])
-; CHECK-NEXT: [[__ROOTN2RSQRT:%.*]] = fdiv nnan nsz contract float 1.000000e+00, [[TMP0]], !fpmath [[META0]]
+; CHECK-NEXT: [[__ROOTN2RSQRT:%.*]] = fdiv nnan nsz contract float 1.000000e+00, [[TMP0]], !fpmath [[META1]]
; CHECK-NEXT: ret float [[__ROOTN2RSQRT]]
;
entry:
@@ -946,7 +946,7 @@ define <2 x float> @test_rootn_v2f32__y_neg2(<2 x float> %x) {
; CHECK-SAME: <2 x float> [[X:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = call contract <2 x float> @llvm.sqrt.v2f32(<2 x float> [[X]])
-; CHECK-NEXT: [[__ROOTN2RSQRT:%.*]] = fdiv contract <2 x float> splat (float 1.000000e+00), [[TMP0]], !fpmath [[META0]]
+; CHECK-NEXT: [[__ROOTN2RSQRT:%.*]] = fdiv contract <2 x float> splat (float 1.000000e+00), [[TMP0]], !fpmath [[META1]]
; CHECK-NEXT: ret <2 x float> [[__ROOTN2RSQRT]]
;
entry:
@@ -959,7 +959,7 @@ define <2 x float> @test_rootn_v2f32__y_neg2__flags(<2 x float> %x) {
; CHECK-SAME: <2 x float> [[X:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = call nnan nsz contract <2 x float> @llvm.sqrt.v2f32(<2 x float> [[X]])
-; CHECK-NEXT: [[__ROOTN2RSQRT:%.*]] = fdiv nnan nsz contract <2 x float> splat (float 1.000000e+00), [[TMP0]], !fpmath [[META0]]
+; CHECK-NEXT: [[__ROOTN2RSQRT:%.*]] = fdiv nnan nsz contract <2 x float> splat (float 1.000000e+00), [[TMP0]], !fpmath [[META1]]
; CHECK-NEXT: ret <2 x float> [[__ROOTN2RSQRT]]
;
entry:
@@ -1010,7 +1010,7 @@ define float @test_rootn_afn_f32(float %x, i32 %y) {
; NOPRELINK-SAME: float [[X:%.*]], i32 [[Y:%.*]]) {
; NOPRELINK-NEXT: entry:
; NOPRELINK-NEXT: [[TMP0:%.*]] = sitofp i32 [[Y]] to float
-; NOPRELINK-NEXT: [[TMP1:%.*]] = call afn float @llvm.amdgcn.rcp.f32(float [[TMP0]])
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fdiv nnan afn float 1.000000e+00, [[TMP0]]
; NOPRELINK-NEXT: [[TMP2:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.log2.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = fmul afn float [[TMP1]], [[TMP3]]
@@ -1052,7 +1052,7 @@ define <2 x float> @test_rootn_afn_v2f32(<2 x float> %x, <2 x i32> %y) {
; NOPRELINK-SAME: <2 x float> [[X:%.*]], <2 x i32> [[Y:%.*]]) {
; NOPRELINK-NEXT: entry:
; NOPRELINK-NEXT: [[TMP0:%.*]] = sitofp <2 x i32> [[Y]] to <2 x float>
-; NOPRELINK-NEXT: [[TMP1:%.*]] = call afn <2 x float> @llvm.amdgcn.rcp.v2f32(<2 x float> [[TMP0]])
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fdiv nnan afn <2 x float> splat (float 1.000000e+00), [[TMP0]]
; NOPRELINK-NEXT: [[TMP2:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = fmul afn <2 x float> [[TMP1]], [[TMP3]]
@@ -1142,7 +1142,7 @@ define float @test_rootn_afn_nnan_ninf_f32(float %x, i32 %y) {
; NOPRELINK-SAME: float [[X:%.*]], i32 [[Y:%.*]]) {
; NOPRELINK-NEXT: entry:
; NOPRELINK-NEXT: [[TMP0:%.*]] = sitofp i32 [[Y]] to float
-; NOPRELINK-NEXT: [[TMP1:%.*]] = call nnan ninf afn float @llvm.amdgcn.rcp.f32(float [[TMP0]])
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fdiv nnan ninf afn float 1.000000e+00, [[TMP0]]
; NOPRELINK-NEXT: [[TMP2:%.*]] = call nnan ninf afn float @llvm.fabs.f32(float [[X]])
; NOPRELINK-NEXT: [[TMP3:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = fmul nnan ninf afn float [[TMP1]], [[TMP3]]
@@ -1181,7 +1181,7 @@ define <2 x float> @test_rootn_afn_nnan_ninf_v2f32(<2 x float> %x, <2 x i32> %y)
; NOPRELINK-SAME: <2 x float> [[X:%.*]], <2 x i32> [[Y:%.*]]) {
; NOPRELINK-NEXT: entry:
; NOPRELINK-NEXT: [[TMP0:%.*]] = sitofp <2 x i32> [[Y]] to <2 x float>
-; NOPRELINK-NEXT: [[TMP1:%.*]] = call nnan ninf afn <2 x float> @llvm.amdgcn.rcp.v2f32(<2 x float> [[TMP0]])
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fdiv nnan ninf afn <2 x float> splat (float 1.000000e+00), [[TMP0]]
; NOPRELINK-NEXT: [[TMP2:%.*]] = call nnan ninf afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
; NOPRELINK-NEXT: [[TMP3:%.*]] = call nnan ninf afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = fmul nnan ninf afn <2 x float> [[TMP1]], [[TMP3]]
@@ -1280,7 +1280,7 @@ define float @test_rootn_fast_f32_strictfp(float %x, i32 %y) #1 {
; NOPRELINK-SAME: float [[X:%.*]], i32 [[Y:%.*]]) #[[ATTR0]] {
; NOPRELINK-NEXT: entry:
; NOPRELINK-NEXT: [[TMP0:%.*]] = call fast float @llvm.experimental.constrained.sitofp.f32.i32(i32 [[Y]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR0]]
-; NOPRELINK-NEXT: [[TMP1:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP0]]) #[[ATTR0]]
+; NOPRELINK-NEXT: [[TMP1:%.*]] = call fast float @llvm.experimental.constrained.fdiv.f32(float 1.000000e+00, float [[TMP0]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR0]]
; NOPRELINK-NEXT: [[TMP2:%.*]] = call fast float @llvm.fabs.f32(float [[X]]) #[[ATTR0]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call fast float @llvm.log2.f32(float [[TMP2]]) #[[ATTR0]]
; NOPRELINK-NEXT: [[TMP4:%.*]] = call fast float @llvm.experimental.constrained.fmul.f32(float [[TMP1]], float [[TMP3]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR0]]
@@ -1561,10 +1561,9 @@ define <2 x float> @test_rootn_afn_nnan_ninf_v2f32__y_3(<2 x float> %x) {
; NOPRELINK-LABEL: define <2 x float> @test_rootn_afn_nnan_ninf_v2f32__y_3(
; NOPRELINK-SAME: <2 x float> [[X:%.*]]) {
; NOPRELINK-NEXT: entry:
-; NOPRELINK-NEXT: [[TMP0:%.*]] = call nnan ninf afn <2 x float> @llvm.amdgcn.rcp.v2f32(<2 x float> splat (float 3.000000e+00))
; NOPRELINK-NEXT: [[TMP1:%.*]] = call nnan ninf afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
; NOPRELINK-NEXT: [[TMP2:%.*]] = call nnan ninf afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP1]])
-; NOPRELINK-NEXT: [[TMP3:%.*]] = fmul nnan ninf afn <2 x float> [[TMP0]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fmul nnan ninf afn <2 x float> [[TMP2]], splat (float 0x3FD5555560000000)
; NOPRELINK-NEXT: [[TMP4:%.*]] = call nnan ninf afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = call nnan ninf afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP4]], <2 x float> [[X]])
; NOPRELINK-NEXT: [[TMP6:%.*]] = fcmp nnan ninf afn oeq <2 x float> [[X]], zeroinitializer
@@ -1588,10 +1587,9 @@ define <2 x float> @test_rootn_afn_nnan_ninf_v2f32__y_4(<2 x float> %x) {
; NOPRELINK-LABEL: define <2 x float> @test_rootn_afn_nnan_ninf_v2f32__y_4(
; NOPRELINK-SAME: <2 x float> [[X:%.*]]) {
; NOPRELINK-NEXT: entry:
-; NOPRELINK-NEXT: [[TMP0:%.*]] = call nnan ninf afn <2 x float> @llvm.amdgcn.rcp.v2f32(<2 x float> splat (float 4.000000e+00))
; NOPRELINK-NEXT: [[TMP1:%.*]] = call nnan ninf afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
; NOPRELINK-NEXT: [[TMP2:%.*]] = call nnan ninf afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP1]])
-; NOPRELINK-NEXT: [[TMP3:%.*]] = fmul nnan ninf afn <2 x float> [[TMP0]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fmul nnan ninf afn <2 x float> [[TMP2]], splat (float 2.500000e-01)
; NOPRELINK-NEXT: [[TMP4:%.*]] = call nnan ninf afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fcmp nnan ninf afn oeq <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP6:%.*]] = select nnan ninf afn <2 x i1> [[TMP5]], <2 x float> zeroinitializer, <2 x float> [[TMP4]]
@@ -1614,10 +1612,9 @@ define <2 x float> @test_rootn_afn_nnan_ninf_v2f32__y_neg3(<2 x float> %x) {
; NOPRELINK-LABEL: define <2 x float> @test_rootn_afn_nnan_ninf_v2f32__y_neg3(
; NOPRELINK-SAME: <2 x float> [[X:%.*]]) {
; NOPRELINK-NEXT: entry:
-; NOPRELINK-NEXT: [[TMP0:%.*]] = call nnan ninf afn <2 x float> @llvm.amdgcn.rcp.v2f32(<2 x float> splat (float -3.000000e+00))
; NOPRELINK-NEXT: [[TMP1:%.*]] = call nnan ninf afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
; NOPRELINK-NEXT: [[TMP2:%.*]] = call nnan ninf afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP1]])
-; NOPRELINK-NEXT: [[TMP3:%.*]] = fmul nnan ninf afn <2 x float> [[TMP0]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fmul nnan ninf afn <2 x float> [[TMP2]], splat (float 0xBFD5555560000000)
; NOPRELINK-NEXT: [[TMP4:%.*]] = call nnan ninf afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = call nnan ninf afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP4]], <2 x float> [[X]])
; NOPRELINK-NEXT: [[TMP6:%.*]] = fcmp nnan ninf afn une <2 x float> [[X]], zeroinitializer
@@ -1641,10 +1638,9 @@ define <2 x float> @test_rootn_afn_nnan_ninf_v2f32__y_neg4(<2 x float> %x) {
; NOPRELINK-LABEL: define <2 x float> @test_rootn_afn_nnan_ninf_v2f32__y_neg4(
; NOPRELINK-SAME: <2 x float> [[X:%.*]]) {
; NOPRELINK-NEXT: entry:
-; NOPRELINK-NEXT: [[TMP0:%.*]] = call nnan ninf afn <2 x float> @llvm.amdgcn.rcp.v2f32(<2 x float> splat (float -4.000000e+00))
; NOPRELINK-NEXT: [[TMP1:%.*]] = call nnan ninf afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
; NOPRELINK-NEXT: [[TMP2:%.*]] = call nnan ninf afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP1]])
-; NOPRELINK-NEXT: [[TMP3:%.*]] = fmul nnan ninf afn <2 x float> [[TMP0]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fmul nnan ninf afn <2 x float> [[TMP2]], splat (float -2.500000e-01)
; NOPRELINK-NEXT: [[TMP4:%.*]] = call nnan ninf afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fcmp nnan ninf afn une <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP6:%.*]] = select nnan ninf afn <2 x i1> [[TMP5]], <2 x float> [[TMP4]], <2 x float> splat (float 0x7FF0000000000000)
@@ -1667,10 +1663,9 @@ define <2 x float> @test_rootn_afn_nnan_ninf_v2f32__y_5(<2 x float> %x) {
; NOPRELINK-LABEL: define <2 x float> @test_rootn_afn_nnan_ninf_v2f32__y_5(
; NOPRELINK-SAME: <2 x float> [[X:%.*]]) {
; NOPRELINK-NEXT: entry:
-; NOPRELINK-NEXT: [[TMP0:%.*]] = call nnan ninf afn <2 x float> @llvm.amdgcn.rcp.v2f32(<2 x float> splat (float 5.000000e+00))
; NOPRELINK-NEXT: [[TMP1:%.*]] = call nnan ninf afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
; NOPRELINK-NEXT: [[TMP2:%.*]] = call nnan ninf afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP1]])
-; NOPRELINK-NEXT: [[TMP3:%.*]] = fmul nnan ninf afn <2 x float> [[TMP0]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fmul nnan ninf afn <2 x float> [[TMP2]], splat (float 0x3FC99999A0000000)
; NOPRELINK-NEXT: [[TMP4:%.*]] = call nnan ninf afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = call nnan ninf afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP4]], <2 x float> [[X]])
; NOPRELINK-NEXT: [[TMP6:%.*]] = fcmp nnan ninf afn oeq <2 x float> [[X]], zeroinitializer
@@ -1707,7 +1702,7 @@ define float @test_rootn_afn_f32__x_known_positive(float nofpclass(ninf nsub nno
; NOPRELINK-SAME: float nofpclass(ninf nsub nnorm) [[X:%.*]], i32 [[Y:%.*]]) {
; NOPRELINK-NEXT: entry:
; NOPRELINK-NEXT: [[TMP0:%.*]] = sitofp i32 [[Y]] to float
-; NOPRELINK-NEXT: [[TMP1:%.*]] = call afn float @llvm.amdgcn.rcp.f32(float [[TMP0]])
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fdiv nnan afn float 1.000000e+00, [[TMP0]]
; NOPRELINK-NEXT: [[TMP2:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.log2.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = fmul afn float [[TMP1]], [[TMP3]]
@@ -1746,7 +1741,7 @@ define float @test_rootn_afn_ninf_nnan_f32__x_known_positive(float nofpclass(nin
; NOPRELINK-SAME: float nofpclass(ninf nsub nnorm) [[X:%.*]], i32 [[Y:%.*]]) {
; NOPRELINK-NEXT: entry:
; NOPRELINK-NEXT: [[TMP0:%.*]] = sitofp i32 [[Y]] to float
-; NOPRELINK-NEXT: [[TMP1:%.*]] = call nnan ninf afn float @llvm.amdgcn.rcp.f32(float [[TMP0]])
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fdiv nnan ninf afn float 1.000000e+00, [[TMP0]]
; NOPRELINK-NEXT: [[TMP2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[X]])
; NOPRELINK-NEXT: [[TMP3:%.*]] = fmul nnan ninf afn float [[TMP1]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP4:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[TMP3]])
@@ -1836,10 +1831,9 @@ define float @test_fast_rootn_f32_y_known_even(float %x, i32 %y.arg) {
; NOPRELINK-NEXT: entry:
; NOPRELINK-NEXT: [[Y:%.*]] = shl i32 [[Y_ARG]], 1
; NOPRELINK-NEXT: [[TMP0:%.*]] = sitofp i32 [[Y]] to float
-; NOPRELINK-NEXT: [[TMP1:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP0]])
; NOPRELINK-NEXT: [[TMP2:%.*]] = call fast float @llvm.fabs.f32(float [[X]])
; NOPRELINK-NEXT: [[TMP3:%.*]] = call fast float @llvm.log2.f32(float [[TMP2]])
-; NOPRELINK-NEXT: [[TMP4:%.*]] = fmul fast float [[TMP1]], [[TMP3]]
+; NOPRELINK-NEXT: [[TMP4:%.*]] = fdiv fast float [[TMP3]], [[TMP0]]
; NOPRELINK-NEXT: [[TMP5:%.*]] = call fast float @llvm.exp2.f32(float [[TMP4]])
; NOPRELINK-NEXT: [[TMP6:%.*]] = fcmp fast oeq float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP7:%.*]] = icmp slt i32 [[Y]], 0
@@ -1871,9 +1865,9 @@ define float @test_fast_rootn_f32_known_positive_y_known_even(float nofpclass(ni
; NOPRELINK-NEXT: entry:
; NOPRELINK-NEXT: [[Y:%.*]] = shl i32 [[Y_ARG]], 1
; NOPRELINK-NEXT: [[TMP0:%.*]] = sitofp i32 [[Y]] to float
-; NOPRELINK-NEXT: [[TMP1:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP0]])
-; NOPRELINK-NEXT: [[TMP2:%.*]] = call fast float @llvm.log2.f32(float [[X]])
-; NOPRELINK-NEXT: [[TMP3:%.*]] = fmul fast float [[TMP1]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP1:%.*]] = call fast float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[TMP2:%.*]] = call fast float @llvm.log2.f32(float [[TMP1]])
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fdiv fast float [[TMP2]], [[TMP0]]
; NOPRELINK-NEXT: [[TMP4:%.*]] = call fast float @llvm.exp2.f32(float [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fcmp fast oeq float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP6:%.*]] = icmp slt i32 [[Y]], 0
@@ -1972,9 +1966,11 @@ attributes #2 = { noinline }
; NOPRELINK: attributes #[[ATTR3]] = { noinline }
; NOPRELINK: attributes #[[ATTR4]] = { nobuiltin }
;.
-; PRELINK: [[META0]] = !{float 2.000000e+00}
-; PRELINK: [[META1]] = !{float 3.000000e+00}
+; PRELINK: [[META0:![0-9]+]] = !{i32 1, !"amdgpu-libcall-have-fast-pow", i32 1}
+; PRELINK: [[META1]] = !{float 2.000000e+00}
+; PRELINK: [[META2]] = !{float 3.000000e+00}
;.
-; NOPRELINK: [[META0]] = !{float 2.000000e+00}
-; NOPRELINK: [[META1]] = !{float 3.000000e+00}
+; NOPRELINK: [[META0:![0-9]+]] = !{i32 1, !"amdgpu-libcall-have-fast-pow", i32 1}
+; NOPRELINK: [[META1]] = !{float 2.000000e+00}
+; NOPRELINK: [[META2]] = !{float 3.000000e+00}
;.
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